CLAIMS
What is claimed is:
1. A device structure, comprising:
a body, comprising a monocrystalline semiconductor material, adjacent to an isolation
dielectric; a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode
separated from the sidewall by a gate dielectric; a source and a drain coupled to the body on opposite sides of the gate stack; a front-side interconnect metallization layer coupled to at least one of the source, drain, or
gate electrode; and a back-side device layer over a back-side surface of the body, opposite the front-side
interconnect metallization layer, wherein the back-side device layer comprises a
second semiconductor material having a different composition than that of the body;
and a back-side device terminal electrically coupled to the back-side device layer.
2. The structure of claim 1, wherein:
the structure comprises a first field effect transistor (FET) stacked over a second FET; the second semiconductor material is monocrystalline; a second gate stack is coupled to the second semiconductor material; and the back-side device terminal further comprises a source or a drain of the second FET, which is coupled to the second semiconductor material.
3. The structure of claim 2, wherein:
the monocrystalline semiconductor material comprises a first Group IV or Group III-V
semiconductor; and the second semiconductor material comprises a second Group IV or Group III-V
semiconductor.
4. The structure of claim 2, further comprising:

a back-side interconnect metallization layer coupled to the back-side device terminal,
wherein the body and the back-side device layer are located between the front-side interconnect metallization layer and the back-side interconnect metallization layer.
5. The structure of claim 1, wherein the back-side device terminal is in contact with one of
the source or drain of the FET.
6. The structure of claim 1, wherein:
the structure comprises a field effect transistor (FET) stacked over a thin film transistor
(TFT); the second semiconductor material is poly crystalline or amorphous; a second gate stack is coupled to the second semiconductor material; and the back-side device terminal further comprises a source or drain of the TFT, which is
coupled to the second semiconductor material.
7. The structure of claim 6, wherein the back-side device terminal is in contact with one of
the source or drain of the FET.
8. An integrated circuit (IC) structure, comprising:
a transistor body adjacent to a field isolation dielectric, the transistor body comprising a
monocrystalline semiconductor material; a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode
separated from the sidewall by a gate dielectric; a source and a drain coupled to the transistor body on opposite sides of the gate stack; a front-side interconnect metallization layer over a first side of the transistor body and the
field isolation dielectric, the front-side interconnect metallization layer coupled to a
first of the source, drain, or gate electrode; and a back-side interconnect metallization layer over a second side of the bodies and the field
isolation dielectric, the back-side interconnect metallization layer coupled to a second
of the source, drain, or gate electrode, and wherein the back-side interconnect
metallization layer has a different composition than the front-side interconnect
metallization layer.
9. The IC structure of claim 8, wherein:

the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.
10. The IC structure of claim 9, wherein the front-side interconnect metallization layer comprises one or more of Ru, Rh, Pd, Ir, Pt, Au, W, Cr, or Co, and the back-side interconnect metallization layer comprises Cu.
11. The IC structure of claim 10, wherein the back-side interconnect layer is coupled to the source, the front-side interconnect layer is coupled to the gate electrode, and the back-side interconnect metallization layer comprises features having at least one of larger lateral dimensions or greater thickness than the front-side interconnect metallization layer.
12. A method of fabricating a transistor structure, the method comprising:
receiving a donor substrate comprising a first device layer disposed over a back-side carrier
layer, the first device layer comprising a first semiconductor material; forming one or more first device layer features in the first device layer with a field isolation
dielectric adjacent to a sidewall of the first device layer features; forming a first front-side device terminal coupled to a first device layer feature; joining a host substrate with a side of the donor substrate opposite the carrier layer; revealing a back side of the first device layer features by removing at least a portion of the
carrier layer; depositing a second device layer on back side of the first device layer features, the second
device layer comprising a second semiconductor material having a different
composition than the first; and forming a back-side device terminal coupled to the second device layer.
13. The method of claim 12, wherein the method further comprises:
depositing a first source or drain comprising semiconductor on the first device layer features;
and
forming a first contact metal coupled to the first source or drain; and
wherein:

depositing the second device layer further comprises depositing a second source or
drain comprising semiconductor; and forming the back-side device terminal further comprises forming a second contact
metal coupled to the first source or drain.
14. The method of claim 13, wherein:
forming the first device layer features further comprises forming a first transistor channel; forming the first front-side device terminal further comprises forming a first gate electrode; depositing the back-side device layer further comprises depositing a second transistor channel
semiconductor; and forming the back-side device terminal further comprises forming a second gate electrode over
the second transistor channel.
15. The method of claim 14, further comprising:
forming a source or drain contact to the first device layer; and forming a source or drain contact to the second device layer.
16. A method of fabricating an integrated circuit IC strata, the method comprising:
receiving a donor substrate having a device layer comprising a first semiconductor material;
fabricating transistors within the device layer;
forming a front-side interconnect metallization layer, comprising at least a first metal, over a first side of the transistors, the front-side interconnect metallization layer coupled to a first of a source, drain, or gate electrode of one or more of the transistors; and
forming a back-side interconnect metallization layer, comprising at least a second metal, over a second side of the transistors, the back-side interconnect metallization layer coupled to a second of the source, drain, or gate electrode of one or more of the transistors.
17. The method of claim 16, wherein, the host substrate includes a back-side carrier layer,
and the method further comprises: joining the host substrate with a donor substrate, the host substrate to join with the donor
substrate on a side opposite the carrier layer; and revealing a back side of one or more of the transistors by removing at least a portion of the
carrier layer.

18. The method of claim 16, wherein
the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer; or
the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.
19. The method of claim 18, wherein the first metal comprises one or more of Ru, Rh, Pd, Ir, Pt, Au, W, Cr, or Co, and the second metal comprises Cu.
20. The IC method of claim 19, wherein the back-side interconnect layer is coupled to the source, the front-side interconnect layer is coupled to the gate electrode, and the back-side interconnect metallization layer comprises features having at least one of larger lateral dimensions or greater thickness than the front-side interconnect metallization layer.