Claims:1. A transistor structure, comprising:
a semiconductor body extending through an isolation dielectric;
a gate electrode over a channel region of the semiconductor body and extending over a front side of the isolation dielectric;
source and drain regions comprising semiconductor material electrically coupled to the channel region, wherein the source and drain regions include at least one deep source or deep drain region extending to a depth below that of the channel region;
one or more front-side interconnect metallization levels over the front side of the isolation dielectric, and coupled to at least one of the source and drain regions, or to the gate electrode; and
one or more back-side interconnect metallization levels over a back side of the isolation dielectric and electrically coupled to the deep source or deep drain region.
, Description:BACKGROUND
Device density in integrated circuits (ICs) has increased for decades in conformance with Moore’s law. However, as the lateral dimensions of a device structure shrink with each technology generation, it becomes increasingly difficult to further reduce structural dimensions.
Three-dimensional (3D) scaling is now of considerable interest as reductions in z-height (device thickness) offer another avenue of increasing overall device density and IC performance. 3D scaling may be in the form of chip stacking or packaged IC stacking, for example. Known 3D integration techniques are expensive and may offer only incremental improvements in z-height and device density. For example, the majority of the thickness of a chip may be inactive substrate material. A stack of such chips may employ through-substrate via (TSV) technology as a means of vertically interconnecting the chip stack. A TSV typically extends through 20-50 μm, or more, of substrate material and therefore is generally limited to via diameters on the micron-scale. As such, TSV density is limited to far below the density of most device (e.g., transistor, memory) cells. Also, the final z-height of a chip-stack employing TSV technology may be hundreds of microns thicker than the actual device layers employed by the stacked device.
3D scaling may also be in the form of vertically-oriented devices, for example where a transistor channel length is substantially normal to a surface of a chip rather than parallel to that surface for the more common laterally-oriented transistor. One problem faced by many vertically-oriented device architectures is how to fabricate terminals on opposite ends of the device, which can be more readily achieved in laterally-oriented devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified “ideal” forms and geometries for clarity of discussion, but it is nevertheless to be understood that practical implementations may only approximate the illustrated ideals. For example, smooth surfaces and square intersections may be drawn in disregard of finite roughness, corner-rounding, and imperfect angular intersections characteristic of structures formed by nanofabrication techniques. Hence, features drawn with a rectangular cross section in a plane of a reference coordinate system, actual fabricated features may instead have a cross section that is rounded or sloped at one or more ends of the features, which may result in a cross-sectional profile that is non-rectangular (e.g., hourglass-shaped, trapezoidal, etc.). Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements. In the figures:
FIG. 1 is a flow diagram illustrating double-sided device processing methods, in accordance with some embodiments;
FIG. 2A, 2B, 2C, 2D, 2E, 2F, 2G and 2H are plan views of a substrate processed with double-sided device processing methods, in accordance with some embodiments;
FIG. 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, 3I and 3J are cross-sectional views of a substrate processed with double-sided device processing methods, in accordance with some embodiments;
FIG. 4A, 4B, 4C are isometric views further illustrating an intervening layer including both III-N semiconductor and dielectric materials, in accordance with some embodiments;
FIG. 4D is a cross-sectional view further illustrating an intervening layer including both III-V semiconductor and dielectric materials, in accordance with some embodiments;
FIG. 5 is a flow diagram illustrating back-side reveal methods, in accordance with some embodiments;
FIG. 6 is a plan view of a substrate with expanded views of IC die on the substrate, and of a transistor structure on the IC die, in accordance with some embodiments;
FIG. 7 is a flow diagram illustrating back-side processing methods including electrical isolation of transistor semiconductor bodies, in accordance with some embodiments;
FIG. 8A, 8B, 8C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 7 are performed, in accordance with some embodiments;
FIG. 9A, 9B, 9C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 7 are performed, in accordance with some embodiments;
FIG. 10A, 10B, 10C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 7 are performed, in accordance with some embodiments;
FIG. 11A, 11B, 11C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 7 are performed, in accordance with some embodiments;
FIG. 11D, 11E, 11F illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 7 are performed, in accordance with some embodiments;
FIG. 12 is a flow diagram illustrating back-side processing methods including back side transistor source/drain contact metallization, in accordance with some embodiments;
FIG. 13 is a plan view of a transistor structure suitable for forming a back-side transistor source/drain contact metallization, in accordance with some embodiments;
FIG. 14A, 14B, 14C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some embodiments;
FIG. 14D, 14E, 14F illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some alternative embodiments;
FIG. 15A, 15B, 15C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some embodiments;
FIG. 15D, 15E, 15F illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some alternative embodiments;
FIG. 16A, 16B, 16C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some embodiments;
FIG. 16D, 16E, 16F illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 12 are performed, in accordance with some alternative embodiments;
FIG. 17 is a flow diagram illustrating back-side processing methods including back side transistor gate metallization, in accordance with some embodiments;
FIG. 18A, 19A, 20A, 21A, 22A, 23A, 24A and 25A illustrate cross-sectional views of a transistor structure as some front-side fabrication operations are performed, in accordance with some embodiments;
FIG. 18B, 19B, 20B, 21B, 22B, 23B, 24B and 25B illustrate cross-sectional views of a transistor structure as some front-side fabrication operations are performed, in accordance with some embodiments;
FIG. 26A, 26B, 26C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some embodiments;
FIG. 27A, 27B, 27C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some embodiments;
FIG. 28A, 28B, 28C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some embodiments;
FIG. 28D, 28E, 28F illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some alternative embodiments;
FIG. 29A, 29B, 29C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some alternative embodiments;
FIG. 30A, 30B, 30C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some alternative embodiments;
FIG. 31A, 31B, 31C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 17 are performed, in accordance with some alternative embodiments;
FIG. 32 is a flow diagram illustrating back-side processing methods including dielectric spacer replacement, in accordance with some embodiments;
FIG. 33A, 33B, 33C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 32 are performed, in accordance with some alternative embodiments;
FIG. 34A, 34B, 34C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 32 are performed, in accordance with some alternative embodiments;
FIG. 35A, 35B, 35C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 32 are performed, in accordance with some alternative embodiments;
FIG. 36A, 36B, 36C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 32 are performed, in accordance with some alternative embodiments;
FIG. 37A, 37B, 37C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 32 are performed, in accordance with some alternative embodiments;
FIG. 38A illustrates back-side reveal methods, in accordance with some embodiments;
FIG. 38B is a flow diagram illustrating methods for forming non-planar transistor back-side source/drain semiconductor and contact metallization selective to planar transistors, in accordance with some embodiments;
FIG. 38C is a flow diagram illustrating methods for forming non-planar transistor back-side source/drain semiconductor and contact metallization selective to other non-planar transistors, in accordance with some embodiments;
FIG. 39 is a plan view of a non-planar transistor structure lacking one source/drain contact metallization and a planar transistor structure with both source/drain metallizations, in accordance with some embodiments;
FIGS. 40A, 40B, 40C illustrate cross-sectional views of a non-planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIGS. 41A, 41B, 41C illustrate cross-sectional views of a planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIGS. 42A, 42B, 42C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIGS. 43A, 43B, 43C illustrate cross-sectional views of the planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIGS. 44A, 44B, 44C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIGS. 45A, 45B, 45C illustrate cross-sectional views of the planar transistor structure as some operations in the methods illustrated in FIG. 38B are performed, in accordance with some embodiments;
FIG. 46 is a plan view of a non-planar transistor structure lacking one source/drain contact metallization and a non-planar transistor structure with both source/drain metallizations, in accordance with some embodiments;
FIGS. 47A, 47B, 47C illustrate cross-sectional views of a non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 48A, 48B, 48C illustrate cross-sectional views of a non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 49A, 49B, 49C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 50A, 50B, 50C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 51A, 51B, 51C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 52A, 52B, 52C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 53A, 53B, 53C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIGS. 54A, 54B, 54C illustrate cross-sectional views of the non-planar transistor structure as some operations in the methods illustrated in FIG. 38C are performed, in accordance with some embodiments;
FIG. 55 is a flow diagram illustrating back-side processing methods including back-side impurity implantation, in accordance with some embodiments;
FIG. 56A, 56B, and 56C illustrate cross-sectional views of a transistor structure as some operations in the methods illustrated in FIG. 55 are performed, in accordance with some embodiments;
FIG. 57A, 57B, and 57C illustrate cross-sectional views of a transistor structure with a back-side implant, in accordance with some embodiments;
FIG. 58 is a flow diagram illustrating back-side processing methods including epitaxial growth of a semiconductor, in accordance with some embodiments;
FIG. 59A, 59B, 59C illustrate cross-sectional views of a III-N semiconductor device stratum as some operations in the methods illustrated in FIG. 58 are performed, in accordance with some embodiments;
FIG. 60A, 60B, 60C illustrate cross-sectional views of semiconductor device layers as some operations in the methods illustrated in FIG. 58 are performed, in accordance with some embodiments;
FIG. 61A, 61B, 62A, and 62B illustrate cross-sectional views of stacked semiconductor device layers, in accordance with some embodiments;
FIG. 63A, 63B, 64A, and 64B illustrate cross-sectional views of stacked semiconductor device layers, in accordance with some embodiments;
FIG. 65 illustrates a plan view of a vertically-oriented device, in accordance with some embodiments;
FIG. 66 illustrates a cross-sectional view of the vertically-oriented device shown in FIG. 65, in accordance with some embodiments;
FIG. 67A illustrates a cross-sectional view of a stacked 1T1R memory cell, in accordance with some embodiments;
FIG. 67B illustrates a cross-sectional view of a stacked 1T1R memory cell, in accordance with some embodiments;
FIG. 68A illustrates a cross-sectional view of a stacked 1T1R memory cell, in accordance with some embodiments;
FIG. 68B illustrates a cross-sectional view of a stacked 1T1R memory cell, in accordance with some embodiments;
FIG. 69 illustrates a cross-sectional view of a stacked device stratum with an intervening thermal conduit, in accordance with some embodiments;
FIG. 70 is an isometric view of an electrical testing apparatus testing a test die via a back-side, in accordance with some embodiments;
FIG. 71 is an isometric view of an electrical testing apparatus testing test die simultaneously via a back-side and a front-side, in accordance with some embodiments;
FIG. 72 is a flow diagram illustrating an electrical test processing method, in accordance with some embodiments;
FIG. 73 is a plan view of a non-planar transistor structure under electrical test using simultaneous back- and front-side contacts, in accordance with some embodiments;
FIGS. 74A, 74B, 74C illustrate cross-sectional views of non-planar transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIGS. 75A, 75B, 75C illustrate cross-sectional views of non-planar transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIGS. 76A, 76B, 76C illustrate cross-sectional views of non-planar transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIG. 77 is a plan view of a logic transistor structure under electrical test using simultaneous back- and front-side contacts, in accordance with some embodiments;
FIGS. 78A, 78B, 78C illustrate cross-sectional views of logic transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIGS. 79A, 79B, 79C illustrate cross-sectional views of logic transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIGS. 80A, 80B, 80C illustrate cross-sectional views of logic transistor structure contacted by conductive pins for electrical test, in accordance with some embodiments;
FIG. 81 illustrates a mobile computing platform and a data server machine employing an SoC having a plurality of FETs including a double-side interconnection, in accordance with embodiments; and
FIG. 82 is a functional block diagram of an electronic computing device, in accordance with some embodiments.
DETAILED DESCRIPTION
One or more embodiments are described with reference to the enclosed figures. While specific configurations and arrangements are depicted and discussed in detail, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that techniques and/or arrangements described herein may be employed in a variety of other systems and applications other than what is described in detail herein.