INTEGRATED LOW DROPOUT LINEAR VOLTAGE REGULATOR WITH IMPROVED CURRENT LIMITING
Field of the Invention
The invention relates to Integrated low dropout linear voltage regulators. In particular, the invention relates to low dropout linear voltage regulators providing improved current limiting.
Background of the Invention
Linear voltage regulators are widely used in the power supply circuits of electronic designs. In many applications these regulators are required to operate with small input-output voltage differentials. Low dropout (LDO) linear voltage regulators are a class of linear voltage regulators that are specifically designed to provide this capability. Linear voltage regulators, including LDOs, also normally incorporate special circuitry for protecting both the load and the regulator under abnormal conditions such as "overload". The most common protection mechanism used is "current limiting". The vast majority of integrated linear voltage regulators (linear voltage regulators implemented in the form of monolithic integrated circuits incorporate such protection mechanisms.
For implementing current limiting the regulator circuit includes an arrangement to sense the current conducted by the output transistor, and to limit that current to a predetermined safe maximum value when overload occurs, such as an output short-circuit..
The most common method to provide current limiting is by providing a resistor in series with the output and sensing the voltage drop across it. The voltage across the resistor which is proportional to the output current of regulator is compared with a preset voltage. The drive to the output transistor is then limited or cutoff if the sensed voltage exceeds the predefined voltage.
United States patent 4,851,953 describes a low drop out voltage regulator based on this principle. According to this invention a series resistor is inserted in the output current path to sense the output current as shown in figure 1. The voltage drop across this Sense Resistance is proportional to the output current of regulator and is fedback to a Current Limit circuit which controls the drive of the output transistor to limit the current. This arrangement suffers

from the drawback that the sense resistor causes a voltage drop leading to an undesired increase in voltage dropout.
US Patent 4,254,372 describes a current sensing method for Low Dropout regulators. In this method, instead of inserting a resistor in the output path, a sense resistance is inserted in the path of the base current drive of the PNP series pass transistor. The base current is sensed through the sense resistance and is used to control the output current by limiting the base current to a predetermined value corresponding to a maximum allowable load current. However, this arrangement can only be used when the output pass transistor is a Bipolar Junction Transistor (BJT). Modern integrated circuits based on Metal Oxide Semiconductor (MOS) transistors cannot therefore utilize this technique. The technique is also not very convenient for BJT applications owing to the wide variation in current gain between individual series pass transistors.
Object and Summary of the Invention
The object of the invention is to obviate the above disadvantages and provide an LDO linear voltage regulator with improved current limiting.
Another object of this invention is to provide an improved current limiting mechanism that is usable for both MOS and BJT implementations
To achieve the said objectives this invention provide an integrated Low Dropout (LDO) linear voltage regulator providing improved current limiting, comprising:
a 2-input, 1-output difference voltage amplifier consisting of a differential
pair,
a reference voltage source connected to a first input of the difference voltage
amplifier,
an arrangement to sense the output voltage of the voltage regulator and couple
it to the second input of the difference amplifier in a manner that provides
negative feedback,
a series pass transistor connected to the output of the difference voltage
amplifier,
a current sense transistor coupled to the series pass transistor using current
mirroring to monitor the current passing through it,
a reference current source coupled to the output of the current sense transistor,
and
the junction of the current sense transistor and the reference current source
being connected to the difference voltage amplifier in a manner that increases
the apparently sensed voltage as the current through the current sense
transistor exceeds the reference current value.
The difference voltage amplifier is a long-tailed pair having a constant current source for providing the tail current.
The arrangement for sensing the output voltage of the voltage regulator consists of directly connecting the output of the voltage regulator to the second input of the difference amplifier.
The junction of the current sense transistor and the reference current source is connected to the control terminal of a current limiting transistor that is connected in parallel with the transistor of the long-tailed pair that has its control terminal as the second input of the difference amplifier.
The invention further provides a method for improving current limiting in an integrated low Drop Out (LDO) linear voltage regulator, comprising the steps of.
providing a 2-input, 1-output difference voltage amplifier consisting of a
differential pair,
connecting a reference voltage source to a first input of the difference voltage
amplifier,
providing an arrangement to sense the output voltage of the voltage regulator
and coupling it to the second input of the difference amplifier in a manner that
provides negative feedback,
connecting a series pass transistor to the output of the difference voltage
amplifier,
coupling a current sense transistor to the series pass transistor using current
mirroring to monitor the current passing through it,
connecting a reference current source to the output of the current sense
transistor, and
coupling the junction of the current sense transistor and the reference current source to the difference voltage amplifier in a manner that increases the apparently sensed voltage as the current through the current sense transistor exceeds the reference current value.
The arrangement for sensing the output voltage of the voltage regulator consists of directly connecting the output of the voltage regulator to the second input of the difference amplifier.
Brief Description of the Drawings:
The invention will now be described with reference to the accompanying drawings.
Figure 1 shows a schematic block diagram of the prior art circuit for LDO.
Figure 2 shows a schematic circuit diagram of the LDO linear voltage regulator with
improved current limiting in accordance with the present invention.
Figure 3 shows waveforms defining the operation of the current limiter in a LDO linear
voltage regulator according to the present invention.
Detailed Description:
Figure 1 has already been described in the background to the invention.
Fig.-2 shows a preferred embodiment of the improved LDO linear voltage regulator according to this invention. This embodiment is merely illustrative and is not intended to be limiting in any manner. For instance, the embodiment shows a Complementary Metal Oxide Semiconductor (CMOS) implementation, however a Bipolar (BJT) implementation is equally possible. Similarly, the embodiment shows a unity gain configuration for the regulator, though non-unity gain configurations are equally feasible. Referring to figure 2, the improved LDO voltage regulator includes a differential amplifier 10 and an output stage incorporating current sensing and current limiting circuitry comprising two branches of pass transistors, each branch comprising a pair of complementary transistors M6, M7, and M8, M9. The pass transistor M6 which is in one branch and the corresponding current sense transistor M8 in the other branch have their control terminals (gates) connected together at vg, and their Source terminals connected together at the common supply terminal. Since both transistors are located on the same silicon die, are fabricated with the same process, are sized proportionately and are (preferably) located in close proximity to each other, this
arrangement enables current sense transistor M8 to mirror the current flowing through series pass transistor M6. The 2 transistors are sized in proportion appropriately based on the requirements of the design. For instance, the M6-M8 size ratio could be 27,000um/40um whereby M8 would carry a current 675 times smaller than the current flowing through M6 at any point of time during the operation of the regulator. The Drain terminal of the Series Pass Transistor M6 which is the output vo of the regulator is also connected to the vin input terminal of the differential amplifier to provide unity gain feedback. Transistors M5, M7 and M9 have their control (Gate) terminal connected together at Vb while their Source terminals are connected to the common supply terminal. This arrangement enables mirroring of currents in proportion to the relative sizes of these transistors. The common control terminal of these three transistors is connected to an external fixed bias current source to provide predefined currents in these transistors. Transistor M5 provides the tail current for the Differential Amplifier, transistor M7 is a biasing transistor connected in series with M6 to complete dc current path and ground any leakage currents, and transistor M9 provides a reference current limit.
The output terminal vo delivers an regulated voltage with respect to the output load current and input voltage vin. The output is fed to the non-inverting terminal of the differential amplifier to complete the feedback loop. The inverting input of differential amplifier is connected to the reference voltage vref.
The differential amplifier 10 acts as an error amplifier and amplifies any deviation of the output voltage with respect to the reference voltage to adjust the gate voltage of pass transistor M6. The differential amplifier is a double-input single-output active current mirror type differential amplifier. The pass transistors M3, Ml, M10 and M4, M2 form two parallel branches Bl and B2 respectively of the differential amplifier. The pass transistors M3 and M4 form an active current mirror with transistor Ml and M2 providing non-inverting and inverting terminal of the differential amplifier respectively. Reference voltage is applied to the control terminal (gate) of the pass transistor M2 and the negative feedback voltage is applied from vo to the control terminal of the pass transistor Ml.
The pass transistors M8, M9 and M10 together form the current sensing and limiting circuit. The transistors M8 and M9 have common drain connected to the gate of M10 as the current limiting feedback.
The circuit operation can be understood from figure 3. In general the output vo sits at the same voltage level as vref because of negative feedback and voltage follower configuration used. When higher current is drawn from the load at the output vo tends to decrease as shown in figure 3a. As vo is connected to the control terminal of the pass transistor Ml, the decrease in vo causes the gate overdrive voltage of Ml to decrease. This reduced overdrive voltage of Ml results in decrease of current through pass transistor Ml. According to differential amplifier characteristics, a decrease in current of branch Bl results in a corresponding increasing in current in branch B2 thus lowering of vg. The decrease in vg increases the gate overdrive voltage of pass transistor M6 enabling it to provide higher current without appreciable fall in vo.
The output voltage vo and corresponding current through transistor Ml is allowed to decrease on demand of the higher output current until the output current reaches a desired/critical pre-decided current value which is set by the reference current flowing through M9. The reference current value can be set by properly sizing transistors in the current sensing and limiting branch of circuit. The pass transistor M8 whose size is proportional to M6 gives a current proportional to the load current.. The current limit is determined by the empirical relation:
(Formula Removed)
This would mean that M9 should be set for a reference current of 900uA for a current limit of 600 mA.
If the current in the pass transistor M8 is less than reference current vs remains near zero. Thus during the normal operation of the regulator when the load current being drawn is less than the set current limit the transistor M10 would not be operational and the differential amplifier acts purely as an error amplifier. When the current in pass transistor M6 becomes
comparable to the reference curent the vs node voltage starts increasing as shown in Figure 3b
The rising vs would not cause the bypass transistor M10 to turn on at lower currents because the source of M10 would already be sitting at a higher voltage of
(Formula Removed)
However, when vs increases by an mount vt above vp i.e. gate overdrive voltage for the pass transistor M10 becomes positive, then transistor M10 will start to turn on.
Now for any increase in the load current as vo decreases the normal phenomenon of decrease in transistor Ml current would be compensated by increase in current through pass transistor M10 maintaining the total current flowing through branch Bl constant. Because of this, the voltage at node vg does not fall any further and is clamped to this level as shown in Figure 3c. Any further decrease in load impedance does not cause the gate voltage for driver transistor would to decrease as required and therefore the output voltage would start falling sharply. At the short circuit of output the regulator will provide the pre-determined short-circuit current.
Because the transistor M10 becomes a part of a high-gain differential amplifier, as evident from the figure 3d and figure 3e, this current limiting arrangement has the advantage of fast response without requiring the addition of extra stages resulting in a very simple and efficient implementation. The current limiting circuit does not interfere with the normal operation of the voltage regulator and comes into operation only when the current is approaches the set limit. Another advantage of the present invention is the implementation of Soft Start mechanism by the same circuit arrangement. When the regulator is switched on the load capacitor offers a virtual short circuit to ground. As large current would tend to flow under this condition, the current limiting circuit operates to limit the charging current at the pre-determined current limit. Thus the capacitor is charged slowly using the maximum current limit thereby providing a soft start to the regulator.

We claim: -
1. An integrated Low Dropout (LDO) linear voltage regulator providing improved
current limiting, comprising:
a 2-input, 1-output difference voltage amplifier (10) consisting of a differential
pair,
a reference voltage source connected to a first input of the difference voltage
amplifier,
an arrangement to sense the output voltage of the voltage regulator and couple
it to the second input of the difference amplifier in a manner that provides
negative feedback,
a series pass transistor (M6) connected to the output of the difference voltage
amplifier,
a current sense transistor (M8) coupled to the series pass transistor using
current mirroring to monitor the current passing through it,
a reference current source coupled to the output of the current sense transistor,
and
the junction of the current sense transistor (M8) and the reference current
source being connected to the difference voltage amplifier (10) in a manner
that increases the apparently sensed voltage as the current through the current
sense transistor (M8) exceeds the reference current value.
2. An integrated Low Dropout (LDO) linear voltage regulator as claimed in claim 1, wherein the difference voltage amplifier (10) is a long-tailed pair having a constant current source for providing the tail current.
3. An integrated Low Dropout (LDO) linear voltage regulator as claimed in claim 1, wherein the arrangement for sensing the output voltage of the voltage regulator consists of directly connecting the output of the voltage regulator to the second input of the difference amplifier (10).
4. An integrated Low Dropout (LDO) linear voltage regulator as claimed in claim 2, wherein the junction of the current sense transistor (M8) and the reference current source is connected to the control terminal of a current limiting transistor that is

connected in parallel with the transistor of the long-tailed pair that has its control terminal as the second input of the difference amplifier (10).
5. A method for improving current limiting in an integrated Low Drop Out (LDO) linear
voltage regulator, comprising the steps of:
providing a 2-input, 1-output difference voltage amplifier (10) consisting of a
differential pair,
connecting a reference voltage source to a first input of the difference voltage
amplifier (10),
providing an arrangement to sense the output voltage of the voltage regulator
and coupling it to the second input of the difference amplifier (10) in a manner
that provides negative feedback,
connecting a series pass transistor (M6) to the output of the difference voltage
amplifier,
coupling a current sense transistor (M8) to the series pass transistor (M6)
using current mirroring to monitor the current passing through it,
connecting a reference current source to the output of the current sense
transistor (M8), and
coupling the junction of the current sense transistor (M8) and the reference
current source to the difference voltage amplifier (10) in a manner that
increases the apparently sensed voltage as the current through the current
sense transistor (M8) exceeds the reference current value.
6. A method for improving current limiting in an integrated low Drop Out (LDO) linear voltage regulator as claimed in claim 5, wherein the arrangement for sensing the output voltage of the voltage regulator consists of directly connecting the output of the voltage regulator to the second input of the difference amplifier.
7. An integrated Low Dropout (LDO) linear voltage regulator providing improved current limiting substantially as herein described with reference to and as illustrated in Figure 2 and 3 of the accompanying drawings.

8. A method for improving current limiting in an integrated low Drop Out (LDO) linear voltage regulator substantially as herein described with reference to and as illustrated in Figure 2 and 3 of the accompanying drawings.