Claims:A package comprising:
a photonic integrated circuit (PIC);
a redistribution layer (RDL) electrically coupled with the PIC; and
an interconnect bridge coupled to a substrate, the interconnect bridge electrically coupled with the RDL, the RDL to extend electrical connections of the PIC outside an area peripheral to the PIC.
, Description:FIELD
[0003] Embodiments of the present disclosure generally relate to the field of semiconductor packaging, and in particular to packages that include a photonic integrated circuit (PIC).

BACKGROUND
[0004] Continued growth in virtual machines and cloud computing will continue to increase the demand for computing devices that include PICs.

BRIEF DESCRIPTION OF THE DRAWINGS
[0005] FIG. 1 illustrates a cross-section of an example integrated PIC and a processor IC package, in accordance with various embodiments.
[0006] FIG. 2 illustrates a cross-section of an example integrated PIC and processor IC package that includes a dummy die, in accordance with various embodiments.
[0007] FIG. 3 illustrates a cross-section of an example integrated PIC and processor IC package that includes a dummy die and an extended EMIB, in accordance with various embodiments.
[0008] FIG. 4 illustrates a cross-section of an example integrated PIC and processor IC package that includes an electrical integrated circuit (EIC) in discreet components, in accordance with various embodiments.
[0009] FIG. 5 illustrates a cross-section of an example integrated PIC and processor IC package that includes an electrical integrated circuit (EIC), in accordance with various embodiments.
[0010] FIG. 6 illustrates a perspective view of an example integrated PIC and processor IC package, in accordance with various embodiments.
[0011] FIG. 7 illustrates a zoomed in perspective view of an example integrated PIC and processor IC package, in accordance with various embodiments.
[0012] FIG. 8 illustrates a photo of an example integrated PIC and a processor IC package, in accordance with various embodiments.
[0013] FIG. 9 illustrates a photo of an example PIC coupled with a fan out redistribution layer (FORDL), in accordance with various embodiments.
[0014] FIG. 10 is an example process for constructing an integrated PIC and a processor IC package that includes a FORDL, in accordance with various embodiments.
[0015] FIG. 11 schematically illustrates a computer system, in accordance with embodiments.

DETAILED DESCRIPTION
[0016] Embodiments described herein include packages that include CPUs and PICs that are electrically coupled via an interconnect bridge, described herein in embodiments as an EMIB. In embodiments, the interconnect bridge may be a bridge die. In some embodiments, the bridge die may have overlying build-up or substrate layers. In some embodiments, the bridge die may not have overlapping build-up or substrate layers. In embodiments, the bridge die may be a EMIB. In embodiments, the interconnect bridge may be an open cavity bridge (OCB), where the OCB is disposed in a cavity at an upper surface of a package substrate. In embodiments, the OCB may not have overlying build-up layers. In embodiments, interconnect bridge may not be embedded into a substrate or other component. References herein that refer to an EMIB may also refer to any implementation of an interconnect bridge.
[0017] In embodiments, the PIC is electrically coupled with the EMIB using a FORDL to extend the reach of electrical connectors of the PICs. In other embodiments, EICs are electrically coupled between the PIC and the EMIB, to support operation of the PIC. In embodiments, the CPUs may be graphical processing units (GPUs), field programmable gate arrays (FPGAs), and the like. It should be noted that herein the term photonics IC and PIC may be used interchangeably.