Claims:1. There is an integrated circuit chip with a large number of components, each of which is connected to one another by one or more logic functions. The sending circuit of the chip is connected to a first logic function, and the receiving circuit is connected to a second logic function. The sending circuit is connected to the first logic function via an antenna, and this antenna transmits an electromagnetic signal to the receiving circuit on the chip.
2. a clock and a clock distribution circuit local to a part of the large integrated chip, according to claim 1 of the intra-chip communication system.
3. System of claim 1, wherein said electromagnetic signal is an antenna-radiated logic signal.
4. The intra-chip communication system of claim 1, wherein the electromagnetic signal is a high-frequency radio signal.
5. The intra-chip communication system of claim 4, where the high frequency exceeds three gigahertz.
, Description:Specifically, the current invention is concerned with communication between integrated circuits, and more specifically with inter-chip and intra-chip wireless communications for 6G networks.
DISCUSSION OF THE PRIOR ART:
The advancement in the development of semiconductor devices is continuing, with an increase in the density of circuits and an increase in their performance. In order to accomplish this, the size of the CMOS device, as well as the width and spacing of the interconnecting metallization, are being decreased. The operating speed and cut-off frequencies of CMOS devices are increasing, and it is expected that speeds greater than 100 GHz will be achieved in the near future (see figure). Copper wiring is used to maintain the resistance of interconnecting wiring, but the total length of wiring is increasing as more and more functions are integrated into semiconductor chips and the capacitance per unit length of wiring is increasing. Because of the reduction in size, the resistance of the contact and via is increasing, and the resistance is becoming a larger proportion of the total wire net resistance, where Rnet=Rwire+Rcontact+Rvia is calculated. As the resistance of the wiring increases, the interconnecting wiring transforms into RC transmission lines, with the RC delay constant equal to RwireCwire and the RC delay constant equal to RwireCwire. Additionally, as a result of decreasing line spacing, the capacitance between metal lines is increasing. As a result, the voltage drop across the wire increases, as does the time it takes for signals to travel from the driving circuit to the receiving circuit to arrive at their destination.
The authors of "Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters," published in the IEEE Journal of Solid State Circuits in May 2002, Vol. 37, No. 5, pp. 534-552, describe a wireless interconnect system that uses radio frequency (RF) to communicate across a semiconductor integrated circuit chip with transmitters and receivers that have integrated receivers. The research paper "Bit-error-rate performance of intra-chip wireless interconnect system," published in IEEE Communication Letters in January 2004, Vol. 8, No. 1, pp 39-41, is concerned with the evaluation of the bit-error-rate performance of a coherent phase shift interconnect system operating on an intra-chip wireless channel at 15 GHz, and is published in IEEE Communication Letters. The paper "Characteristics of integrated dipole antennas on bulk, SOI, and SOS substrates for wireless communications", by Kihong Kim and Kenneth K. O, published in IEEE IITC in 1998, pages 21-23, is concerned with integrated antennas on bulk, SOI, and SOS substrates.
An integrated dipole antenna with high transmission gain on silicon is described in "High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect," IEEE Electron Device Letters, Vol. 23, No.12, December 2002, pp. 732-733, by A. B. M. H. Rashid, S Watanabe, and T. Kikkawa. A high performance antenna on a proton-implanted silicon with 106 ohm centimeter resistivity is described in the paper "Integrated antennas on Si, proton-implanted Si, and silicon-on-quartz," published in the IEEE IEDM Technical Digest in 2001, pages 903-906. K. T. Chan, Albert Chin, Y. B. Chen, Y. D. Lin, T. S. Duh, and W. J. Lin, "Integrated antenna High-resistivity polysilicon wafers are used as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components, according to a study published in the Electronic Components and Technology Conference 2004 (pp. 1879-1884). The study is directed at high-resistivity polysilicon wafer technology that is used as low-loss substrates for three-dimensional integration of on-chip antennas and RF passive components.
In the article "Broadband micro-strip patch antenna on micro-machined silicon substrates," published in Electronics Letters, vol. 34, no. 1, pp. 3-4, January 1998, the authors describe the development of a micro-machined micro-strip patch antenna on high-resistivity silicon wafers using a micro-machined micro-strip patch antenna design. The paper "Design and tolerance analysis of a 21 GHz CPW-fed, slot-coupled, micro-strip antenna on etched silicon," published in the IEEE AP-S Digest in 2002, Vol. 1, pp. 402-405, is concerned with a rectangular patch antenna on high resistivity silicon. Mau-Chung In their paper "RF/wireless interconnect for inter- and intra-Chip communications," published in the Proceedings of the IEEE, vol. 89, no. 4, April 2001, pp 456-463, Frank Chang and colleagues describe a concept for future inter- and intra-ULSI communications using radio frequency wireless interconnects. In "High performance interconnects: An integration overview," by Robert H. Havemann and James A. Hutchby in Proceedings of the IEEE, vol. 89, no. 5, May 2001, pp 586-601, the authors discuss high performance interconnections that arise as a result of the scaling of chip wiring not keeping pace with other factors of semiconductor integrated circuits.
The use of wireless networks to transmit high data rates for multimedia applications allows for coverage of nearby applications. For example, wireless local area networks (WLAN) operate at 11 Mbps for 100 meters, wireless personal area networks (WPAN) operate at 100 meters for 10 meters, and wireless body area networks (WBAN) operate at 600 meters per second for one mile. Therefore, in situations where distances between functions on a large integrated circuit chip are measured in centimeters or less, and data rates are measured in gigabits per second, a CAN (micro-chip area network) network could be useful in providing communications between functions on separate chips located on a multi-chip module (gigabits per second).
SUMMARY OF THE PRESENT INVENTION:
Functionalities on a large semiconductor integrated circuit chip connect with one another using radio frequency (RF) signals in the current invention, which is described in detail below. RF signals are sent from a transmitting circuit to a receiving circuit that is connected to a similar antenna by means of an antenna. The antennas are made of chip metallization and feature a structure that resembles a dipole in appearance. There are many different forms for the arms of a dipole antenna, including straight lengths of wire and zigzag configurations, where the zigzag pattern might be in the form of a saw tooth or a square wave. The frequencies of the RF signals are in a range where the length of each arm of the dipole antennas is a significant amount of a quarter wavelength, which corresponds to the length of each arm of the dipole antennas.
A tiny satellite (micro-satellite) embedded inside a multi-chip package enables integrated circuit chips to connect with one another using radio frequency signals (RF signals). Signal is linked to a first antenna on a first integrated circuit chip, and an RF signal is transferred from the first antenna to a second antenna placed in the module package and connected to the satellite. It links the RF signal to a third antenna in the module package, which sends it to a fourth antenna on another integrated circuit chip, which is then coupled to a fourth antenna on another integrated circuit chip. The communications between the first chip and the second chip may take place in either way due to the bidirectional nature of the satellite.
Because integrated circuit chips are wire bonded in wire bond packages, the -satellite and its associated antennas are mounted on the module cap above the integrated circuit chips, with each antenna associated with the -satellite being located over one of each semiconductor chip mounted on the module. If the semiconductor chips on the module are bonded together using flip-chip technology, the -satellite and its associated antennas are located on the bonding surface of the module, with each antenna associated with the -satellite being located underneath one of the semiconductor chips mounted on the module. RF communications between a single integrated circuit chip and a satellite, which then retransmits the RF signal back to the single integrated circuit chip, is a subset of this architecture.
The use of wireless networks to transmit high data rates for multimedia applications allows for coverage of nearby applications. For example, wireless local area networks (WLAN) operate at 11 Mbps for 100 meters, wireless personal area networks (WPAN) operate at 100 meters for 10 meters, and wireless body area networks (WBAN) operate at 600 meters per second for one mile. Therefore, in situations where distances between functions on a large integrated circuit chip are measured in centimeters or less, and data rates are measured in gigabits per second, a CAN (micro-chip area network) network could be useful in providing communications between functions on separate chips located on a multi-chip module (gigabits per second).
BRIEF DESCRIPTION OF THE INVENTION:
Optimum geometrical parameters were determined for the plasmonic horn and plantenna designs at a working frequency of v = 474 THz (wavelength = 633 nm) and were optimised for this frequency. Plasmatic nanostructures, with thicknesses t1 = 45.0 nm, were thought to be made of gold and grown on a silicon dioxide (SiO2) dielectric substrate, with permittivity r = 2.28 and thickness h = 240.0 nm, and were deemed to be composed of gold.
As shown in Figure 1, the substrate was ended with a perfect electric conductor (PEC) boundary-condition in order to imitate a ground plane.
However, any form of modulation that can be modulated and demodulated reliably, such as pulse position modulation (PPM), is within the scope of the present invention. Wireless peripheral component interconnect express is the preferred mode for communicating digital signals between distant logical units of the present invention. The use of high-frequency radio electromagnetic signals to transmit and receive signals between a chip and a remote satellite is preferred; however, any form of radiated energy signal that allows for reliable ultra-wide band transmission and reception of signals, such as light, is within the scope of the present invention.
It will be understood by those skilled in the art that, while the invention has been particularly shown and described with reference to preferred embodiments thereof, it is possible to make various modifications to the form and details of the invention while still maintaining the spirit and scope of the invention.
However, those knowledgeable in the field will appreciate that the invention is not limited to the pictures of drawings or drawings described above and is not meant to depict the different scale components, as the invention is described herein by example utilizing embodiments and illustrative figures. In addition, for the sake of clarity, certain aspects of the invention may not be shown in particular representations. Omissions in this section do not affect any of the examples presented in any way. To be clear, the invention is not intended to be limited to the specific form described in the drawings and extensive descriptions. On the other hand, the narrative is to cover all possible modifications, equivalents, and alternatives to the invention as indicated by the attached claims. a common phrasing
"May" is used in a permissive sense rather than an obligatory one in this description, implying that there is the possibility for it (i.e., meaning must).
Unless otherwise specified, the terms "a" and "an" denote "at least one," while the word "plurality" denotes "one or more. " To further emphasizes this point, all of the vocabulary and phraseology used below is purely descriptive. They should not be interpreted as restricting in any way the scope of the project. Subject matter listed after that is not intended to be limited by the use of language such as "including," or variations thereof, such as "comprising," "having," "containing," or "involved," which is intended to be broad enough to include the subject matter listed after that as well as any other subject matter that is not specifically mentioned. For legal purposes, the phrase "comprising" is regarded to be interchangeable with the terms "including" or "including." The specification includes any references to prior art papers, materials, devices, or objects merely to set the stage for the current invention. It is not implied or stated that any or all of the above constitutes previous art or was generally known in the relevant area prior to the filing of the current application.
To avoid ambiguity, we will use the transitional phrase "comprising" to indicate that a component or group of components is also contemplated with the words "consisting of," "consisting of," or "selected from a group that includes," and vice versa, when reciting compositions, elements, or groups of elements.
According to the accompanying figures, the present invention is disclosed in different embodiments, wherein the reference numbers used therein correspond to the similar components in the description. However, this innovation may be implemented in a variety of ways. It is not intended to be restricted to the specific implementation described in this document. For the sake of completeness and clarity, a picture has been included in this disclosure to demonstrate the extent of the invention. Various parts of the specified implementations are given numerical numbers and ranges in the following in-depth discussion. The figures and ranges presented here are not meant to restrict the scope of the claims, but rather to serve as examples. A number of materials have been recognized as appropriate for different aspects of the projects. Rather, they should be seen as illustrative rather than restrictive to the invention's potential.