CLIAMS:We Claim:
1. A computer-implemented method comprising:
receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;
modifying, via one or more hardware processors, the design to include a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes; and
outputting the design to the PLD to program the PLD.

2. The method of claim 1, wherein:
the logic analyzer circuit is arranged to store signals from the selected nodes when the logic analyzer circuit is programmed into the PLD.

3. The method of claim 1, comprising:
modifying, via the one or more hardware processors, the design to include:
an external memory interface for connecting the logic analyzer circuit to an external memory; and
a trace memory enable register configured to alter a rate and format of data written to and read from the external memory.

4. The method of claim 3, wherein the external memory interface and the trace memory enable register may be disabled.

5. The method of claim 1, comprising:
modifying, via the one or more hardware processors, the design to include:
a plurality of selectable groups of trigger signals, wherein any one of the trigger signals can be connected to any one of the nodes; and
for each trigger signal, a trigger condition for the logic analyzer circuit.

6. The method of claim 5, wherein a trigger signal corresponds to a capture signal, such that when the trigger condition of the trigger signal is satisfied, the capture signal is stored in memory.

7. The method of claim 5, wherein a trigger signal corresponds to multiple capture signals.

8. A non-transitory, computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method, the method comprising:
receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;
modifying the design to include a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes; and
outputting the design to the PLD to program the PLD.

9. A system comprising:
one or more hardware processors; and
a memory storing instructions that, when executed by the one or more hardware processors, cause the one or more hardware processors to perform a method, the method comprising:
receiving a design for a programmable logic device (PLD), the design including a plurality of nodes;
modifying the design to include a logic analyzer circuit, the logic analyzer circuit including inputs for a plurality of selectable groups of capture signals for connecting to selected nodes of the plurality of nodes; and
outputting the design to the PLD to program the PLD.

10. The system of claim 9, wherein:
the logic analyzer circuit is arranged to store signals from the selected nodes when the logic analyzer circuit is programmed into the PLD.

11. The system of claim 9, wherein the method comprises:
modifying the design to include:
an external memory interface which connects the logic analyzer circuit to an external memory; and
a trace memory enable register configured to alter the rate and format of the data written to and read from the external memory.

12. The computer-readable medium of claim 11, wherein the external memory interface and the trace memory enable register may be disabled.

13. The system of claim 9, wherein the method comprises:
modifying the design to include:
a plurality of selectable groups of trigger signals, wherein any of the trigger signals can be connected to any one of the nodes; and
for each trigger signal, a trigger condition for the logic analyzer circuit.

14. The system of claim 13, wherein a trigger signal corresponds to a capture signal, such that when the trigger condition of the trigger signal is satisfied, the capture signal is stored in memory.

15. The system of claim 13, wherein a trigger signal corresponds to multiple capture signals.

16. A system comprising:
a user logic circuit programmed into a chip, and including a plurality of nodes;
a logic analyzer circuit programmed into the chip, and including:
a capture signal group selector configured to select a group of capture signals from a plurality of selectable groups of capture signals corresponding to the plurality of nodes, based on a capture signal group selection input; and
a trigger signal group selector configured to select a group of trigger signals from a plurality of selectable groups of trigger signals corresponding to the plurality of nodes, based on a capture trigger group selection input; and
a memory configured to store one of the selected group of capture signals responsive to a condition of a corresponding one of the selected group of trigger signals being met.

17. The system of claim 16, wherein the logic analyzer circuit comprises
a trace memory enable register configured to alter the rate and format of the data written to and read from the memory, wherein the memory is external to the chip.

18. The system of claim 17, wherein the trace memory enable register may be disabled.

Dated this 27th day of March, 2014
Madhusudan S.T.
Of K&S Partners
Attorney for the Applicant
,TagSPECI:TECHNICAL FIELD
The present invention relates to logic analyzer circuits, and more particularly, to logical analyzer circuits for programmable logic devices.