DESC:TECHNICAL FIELD
[0001] The present disclosure relates to the field of semiconductor device technology, and nanoelectronics. More precisely, the present disclosure focuses on a type of transistor design used in modern integrated circuits, and a Silicon-Controlled Rectifier (SCR) which is a type of semiconductor device used for switching and amplification.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present disclosure. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed disclosure, or that any publication specifically or implicitly referenced is prior art.
[0003] An ESD stress occurs when two bodies at different electrostatic potential come in contact leading to a massive flow of current between the bodies for a few hundreds of nano-seconds. At chip level it can be because a charged human touching a device modelled as Human Body Model (HBM) or a charged device being abruptly grounded modelled as Charged Device Model (CDM) or can be during assembly when a huge machinery which is accidently grounded by a chip categorized as Machine Model (MM). These three models are differentiated based on the ESD stress time and peak amplitude of current reached. Referring to FIG. 1, it illustrates a conventional Fin based SCR. An ESD event can result in catastrophic failure of the device by gate oxide breakdown or meltdown of device active area. They can also lead to time dependent degradation of the device. Hence it is critical to design efficient Fin based ESD protection elements for non-planar technology nodes.
[0004] Among various ESD protection elements SCRs are a must for low voltage – high-speed I/O, as well as, ESD protection of RF pads, due to least parasitic loading and smallest foot print offered by SCRs. The implementation of Fin based SCRs with the fundamental concepts borrowed from conventional planar SCR fails to reproduce SCR characteristics. FinFET technology replaced their planar counterparts, by offering an improved short channel performance to scale the conventional transistors. However, this also increases the capacitance loading of the components on the core circuit and I/O causing signal delays and degraded rf and switching performances. It becomes crucial to reduce the capacitance loading of the ESD protection to retain the core circuit performance.
[0005] Therefore, there is, a need to overcome all drawbacks and limitations of the existing SCRs.

OBJECTS OF THE PRESENT DISCLOSURE
[0006] Some of the objects of the present disclosure, that at least one embodiment herein satisfy are as listed herein below.
[0007] It is an object of the present disclosure to overcome the drawbacks and limitations of the existing systems for the method for High Threshold Voltage and High Breakdown Gate Stack in p-GaN Gate e-mode HEMTs.
[0008] It is an object of the present disclosure to Gan raise the threshold voltage of the p-GaN gate e-mode HEMTs as a higher threshold voltage is desirable in certain applications to control the turn-on behavior of the transistor and prevent unintentional conduction.
[0009] It is an object of the present disclosure to increase the breakdown voltage of the gate stack in the p-GaN HEMTs as a higher breakdown voltage indicates that the transistor can handle higher voltage levels without suffering from electrical breakdown, making it more suitable for high-power and high-voltage applications.
[0010] It is an object of the present disclosure to enhance the overall reliability and robustness of the p-GaN gate e-mode HEMTs by optimizing the gate stack design, to make the devices more resistant to electrical stress, thermal effects, and other environmental factors that can degrade their performance over time.
[0011] It is an object of the present disclosure to minimize leakage current, especially when the transistor is in the off-state, which is crucial for power efficiency and preventing unnecessary energy consumption.
[0012] It is an object of the present disclosure to develop a gate stack fabrication method that is compatible with existing semiconductor fabrication processes which would facilitate the integration of the improved gate stack into existing manufacturing workflows.
[0013] It is an object of the present disclosure to achieve improvements in a cost-effective manner involving optimizing material usage, processing steps, and equipment requirements to minimize production costs and achieve the desired performance enhancements.
[0014] It is an object of the present disclosure to contribute to the advancement of semiconductor device technology and transistor performance which involves novel materials, design concepts, or fabrication techniques that lead to breakthroughs in the field.

SUMMARY
[0015] Within the scope of this application, it is expressly envisaged that the various aspects, embodiments, examples and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.
[0016] In an aspect, the present disclosure relates to a semiconductor device including a Silicon Controlled Rectifier (SCR). The SCR includes a floating tap SCR device and an emitter shorted SCR device connected in series with the floating tap SCR device. The combination of the floating tap SCR device and the emitter shorted SCR device enables a reduction in capacitance for a predetermined isolation distance between the floating tap SCR device and the emitter shorted SCR device.
[0017] In an embodiment, the reduction in capacitance is achieved by the combination of the floating tap SCR device and the emitter shorted SCR device ranges between 5X to 5 orders of magnitude.
[0018] In an embodiment, the floating tap SCR device is configured such that a base resistance of associated NPN and PNP transistors tends towards infinity when the taps are floated enabling a low capacitance response to changes in terminal signals.
[0019] In an embodiment, the SCR includes a doped silicon substrate, a Fin Field Effect Transistor (FinFET) gate comprising polysilicon as the gate material, a source and a drain region, each doped with metal contacts and a gate region and an SCR region comprising anode and cathode regions with copper as the gate material.
[0020] In an embodiment, one or more dielectric isolation layers separate the floating tap SCR device and the emitter shorted SCR device.
[0021] In an embodiment, the one or more dielectric isolation layers are configured to optimize the capacitance reduction for the predetermined isolation distance.
[0022] In an embodiment, the dielectric material used in the one or more dielectric isolation layers has a lower relative permittivity to reduce capacitance in the device.
[0023] In an embodiment, the SCR device is implemented in a three-dimensional stacked configuration.
[0024] Various objects, features, aspects, and advantages of the inventive subject matter will become apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[0025] The specifications of the present disclosure are accompanied with drawings to aid in better understanding of the said disclosure. The drawings are in no way limitations of the present disclosure, rather are meant to illustrate the ideal embodiments of the said disclosure.
[0026] In the figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0027] FIG. 1 illustrates a conventional Fin based SCR.
[0028] FIGs. 2A and 2B illustrate a top view and a cross-sectional of a gated SCR device in SOI FinFET Technology.
[0029] FIG. 3 illustrates a top view of an SCR with N and P trigger taps for injecting a trigger current in planar SOI technology.
[0030] FIGs. 4A and 4B illustrate top and cross-sectional views of an SCR with N and P taps in a different scheme in order to control holding/trigger voltage in planar SOI technology.
[0031] FIGs. 5A and 5B illustrate cross sectional views and an isometric view of an SCR in FinFET technology.
[0032] FIGs. 6A-6D illustrate cross-sectional views and top-view of an SCR in FinFET technology.
[0033] FIGs. 7A-7C illustrate an SCR in bulk FinFET technology.
[0034] FIGs 8A and 8B illustrate a 3D and an isometric view of the proposed Dual Fin SCR device, in accordance with an embodiment of the present disclosure.
[0035] FIG. 9 illustrates a modified schematic to achieve low capacitance, in accordance with an embodiment of the present disclosure.
[0036] FIG. 10 illustrates a cross-sectional view of a Conventional Fin-based SCR CFSCR device in a modified schematic, in accordance with an embodiment of the present disclosure.
[0037] FIG. 11 illustrates a capacitance and a TLP I-V of CFSCR devices in the modified circuit scheme, with varying isolation distance between the emitter shorted and floating tap devices, in accordance with an embodiment of the present disclosure.
[0038] FIG. 12 illustrates a TCAD schematic of CFSCR and DTFSCR devices in modified Scheme, in accordance with an embodiment of the present disclosure.
[0039] FIG. 13 illustrates a capacitance of DTFSCR devices in modified scheme showing five orders of reduction in capacitance, based on the optimized Liso, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0040] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0041] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0042] If the specification states a component or feature “may”,”can”,”could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have that characteristic.
[0043] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0044] The present invention relates to the field of semiconductor device technology, and nanoelectronics. More precisely, the present invention focuses on a type of transistor design used in modern integrated circuits, and a Silicon-Controlled Rectifier (SCR) which is a type of semiconductor device used for switching and amplification.
[0045] FIGs. 2A and 2B illustrate a top view and a cross-sectional of a gated SCR device in SOI FinFET Technology.
[0046] Referring to FIGs. 2A and 2B, the device operates as a controllable rectifier, meaning it can switch between conducting and non-conducting states under the influence of an external signal. This technology finds application in various electronic circuits, particularly in scenarios where efficient switching and amplification are required, such as in digital logic circuits, analog circuits, and radio frequency (RF) systems. The integration of Low Capacitance FinFET technology with SCR functionality enhances the performance of semiconductor devices in terms of speed, power efficiency, and signal processing capabilities.
[0047] The distinguishing feature of the Low Capacitance FinFET SCR is its focus on minimizing the device's capacitance. Capacitance in a semiconductor device can lead to slower switching speeds and increased power consumption, particularly in high-frequency applications. By reducing capacitance, the device becomes better suited for high-speed operations, such as those encountered in digital circuits and RF systems. The integration of low capacitance with the FinFET SCR design makes it particularly well-suited for high-speed applications. These could include advanced digital logic circuits that require rapid switching between states, analog circuits demanding precise control over signal amplification, and radio frequency systems where efficient signal processing at high frequencies is critical.
[0048] The Low Capacitance FinFET SCR offers enhanced performance characteristics compared to traditional SCR devices or even standard FinFET transistors. Its combination of efficient switching, low leakage, and reduced capacitance contributes to improved power efficiency, reduced signal delays, and better overall system performance. This innovative device finds applications in a wide range of electronic circuits and systems. Examples include high-speed data communication systems, wireless communication devices, radar systems, and advanced sensor networks. Its ability to handle high frequencies while maintaining low capacitance makes it an attractive choice for cutting-edge technology.
[0049] FIG. 3 illustrates a top view of an SCR with N and P trigger taps for injecting a trigger current in planar SOI technology.
[0050] Referring to FIG. 3, a top view 300 of a Silicon-Controlled Rectifier (SCR) device implemented using planar Silicon-On-Insulator (SOI) technology is a type of semiconductor device commonly used in electronics for switching and amplification. In the context, the "N" and "P" trigger taps suggests that the SCR is designed with both N-type and P-type regions, which are the two basic types of semiconductor materials. The N-type region is typically the cathode or emitter of the SCR, and the P-type region is the anode or collector. The trigger taps are used to inject a trigger current, which is a small current applied to the gate of the SCR to turn it on. This allows to control the SCR's triggering and holding voltage characteristics. The planar SOI technology indicates that the device is built using a layered structure, with a layer of silicon (the active layer) on top of a layer of insulating material (the oxide layer). This helps reduce power consumption and improve device performance. In summary, the invention seems to be a planar SOI-based SCR device with N and P trigger taps for injecting a trigger current to control its triggering and holding voltage characteristics. This could have potential applications in power electronics and semiconductor devices.
[0051] FIGs. 4A and 4B illustrate top and cross-sectional views of an SCR with N and P taps in a different scheme in order to control holding/trigger voltage in planar SOI technology
[0052] Referring to FIGs. 4A and 4B, top and cross-sectional views 400 of an SCR with N and P taps are disclosed. The device has a central area with alternating N and P regions. The central region is where the SCR's main operation takes place. The outer regions are P-type material, acting as the anode or collector. The inner regions are N-type material, acting as the cathode or emitter. The N and P trigger taps are strategically placed near the SCR's gate area. These trigger taps allow the injection of trigger currents for controlling the device's trigger and holding voltages. In the cross-sectional view, the N-type silicon region forms the emitter of the SCR. The P-type silicon region acts as the gate or control region. The insulating layer (oxide) separates the active silicon layers from the substrate. The substrate is P-type silicon, serving as the collector or anode. The N and P trigger taps would be connected to the N-type and P-type regions in the gate area. This different scheme for controlling holding/trigger voltage could offer improved performance, reduced power consumption, or other advantages compared to traditional SCR designs.
[0053] FIGs. 5A and 5B illustrate cross sectional views and an isometric view 500 of an SCR in FinFET technology.
[0054] Referring to FIG. 5A, the gate of the SCR, often made of P or P+ polysilicon material, is positioned above the P-type region. An insulating layer (oxide) separates the gate from the underlying N+ region. The N+ region acts as the emitter of the SCR. Another insulating layer (oxide) separates the N+ region from the underlying P-type region, which acts as the collector. The P-well region, isolated by an insulating layer, is often used to control the trigger characteristics of the SCR. The N- region serves as a buffer layer between the P-well and the N+ emitter, aiding in voltage control and reducing leakage. The N+ and P+ regions are typically highly doped for efficient current flow and conductivity. The substrate is a P+ silicon layer, acting as the anode or collector terminal. In this SOI-based SCR design, the insulating layers between the active regions and the substrate help reduce parasitic effects and enhance the device's performance by minimizing unwanted leakage currents. The presence of the gate allows precise control of the device's triggering and holding characteristics.
[0055] Referring to FIG. 5B, the N-Fin serves as the emitter of the SCR and is formed from N-type silicon. The P-Fin, adjacent to the N-Fin, acts as the collector and is made of P-type silicon. A P-type gate is positioned above the N-Fin and separated by an insulating layer (oxide). The P-Well region is often used to control the triggering characteristics of the device, influencing the behavior of the SCR. The substrate serves as the anode or collector terminal of the SCR. In this FinFET-based SCR design, the gate provides electrostatic control over the N-Fin, allowing for precise control of the trigger and holding voltages. The insulating layer (oxide) beneath the gate helps reduce unwanted leakage currents and enhances device performance. The FinFET structure offers improved control over the flow of current and provides better immunity to parasitic effects. This FinFET-based SCR takes advantage of the unique characteristics of FinFET technology, such as better electrostatic control and reduced leakage, to create a compact and efficient SCR device for various applications.
[0056] FIGs. 6A-6D illustrate cross-sectional views and top-view of an SCR in FinFET technology.
[0057] Referring to FIG. 6A and 6B, cross-sectional and top-views 600 of an SCR in FinFET technology is disclosed. The SOI substrate consists of a layer of silicon (active layer) on top of a layer of insulating material (Buried Oxide or BOX layer). An N-well is formed by selectively doping the silicon layer with N-type dopants. This N-well creates a region with N-type conductivity within the silicon layer. Adjacent to the N-well, a P-well is formed by selectively doping the silicon layer with P-type dopants. This P-well creates a region with P-type conductivity within the silicon layer. The Buried Oxide (BOX) layer serves as an insulating barrier between the N-well, P-well, and the underlying substrate. It helps prevent unwanted interactions and leakage currents between different regions of the integrated circuit. The substrate, located beneath the Buried Oxide (BOX) layer, provides structural support and may have a specific conductivity type (N-type or P-type) depending on the design requirements. This structure allows for the creation of isolated regions with different conductivity types on a single chip. It is a fundamental design in modern integrated circuit fabrication, enabling the integration of various types of transistors and devices within a semiconductor chip while improving performance and reducing power consumption. The N-well and P-well regions play a crucial role in defining the characteristics and behavior of the devices fabricated on the SOI substrate.
[0058] FIGs. 7A-7C illustrate an SCR 700 in bulk FinFET technology.
[0059] FIG. 7A illustrates an SCR in a perspective view. It includes a semiconductor fin extending upwardly (e.g., in z-direction) from an upper surface of semiconductor substrate and extending in a first direction (e.g., in x-direction). Shallow trench isolation (STI) region, which is made of a dielectric material (e.g., silicon dioxide), has an upper surface that divides the semiconductor fin into an upper and a base portion. The STI region laterally surrounds the base fin portion, while the upper fin portion remains above the upper surface of the STI region. FIG. 7B is a thyristor-based semiconductor device having a fin adapted to inhibit short channel effects, according to an embodiment of the present invention. It shows various example implantation regions, including N+ source/drain and cathode implant region, P base implant region, N base implant region and P+ source/drain and anode implant region.
[0060] Referring to FIG. 7C, a perspective view of the B is SCR for bulk FinFET having three gate electrodes is disclosed. The central region consists of alternating N+ (N-type) and P (P-type) regions. This is where the main SCR operation takes place. The three gate electrodes (Gate 1, Gate 2, and the central Gate) are positioned over the N+ and P regions. The P-type regions serve as the anode or collector, while the N+ regions act as the emitter. The SCR can be triggered by applying suitable voltages to the gate electrodes, allowing control over its operation. The physical layout incorporates the fin-like structures characteristic of FinFET technology, enhancing control and reducing leakage. This perspective view provides a conceptual representation of the bulk FinFET SCR with three gate electrodes. In practice, the actual layout and design would involve more detailed considerations, doping profiles, and optimization to achieve the desired performance characteristics.
[0061] FIGs. 8A and 8B illustrate a 3D and an isometric view of the proposed Dual Fin SCR device, in accordance with an embodiment of the present disclosure.
[0062] Referring to FIGs. 8A and 8B, an illustration 800 of the 3D and isometric views of the proposed Dual Fin SCR device is disclosed. The representations are analogous and only represent different perspectives for viewing of the device. At the top layer are the metal contacts that provide connection points to the device. The anode contact is where the current enters the device. The n-tap contact is positioned strategically for optimal control and modulation and the gate terminal controls the SCR and FinFET components. On both sides of the device, there are two FinFET structures protruding from the substrate. Each FinFET structure consists of a fin-like channel and a gate electrode that wraps around the sides. The n-well region is located beneath the FinFET structures and helps modulate the FinFET characteristics. Below the FinFET region is the SCR region where the anode is situated, facilitating current flow. The n-Tap and n-Well regions provide additional control and modulation, enhancing device performance. The gate region is positioned between the anode and n-tap/n-well regions, the gate controls SCR conductivity. Dielectric isolation layers are used to separate different regions of the device, preventing unintended interactions. The silicon substrate also serves as the foundation of the device structure.
[0063] FIG. 9 illustrates a modified schematic to achieve low capacitance, in accordance with an embodiment of the present disclosure.
[0064] Referring to FIG. 9, a modified schematic 900 to achieve low capacitance is disclosed. It aims at reducing the overall capacitance of a Silicon-Controlled Rectifier (SCR) device by introducing an open tap structure in series with a standard SCR. The anode terminal of the standard SCR is where the current enters the device and the cathode terminal serves as the current exit point. The gate terminal controls the triggering and conductivity of the SCR. An open tap structure can be added in series with the standard SCR to reduce overall capacitance which includes an anode tap, a cathode taps, and a gate tap, each of which has minimal physical overlap with other device components. The open tap structure is designed for low capacitance and is optimized for high-speed operation. The dielectric isolation layers, such as silicon dioxide (SiO2), are strategically placed to ensure electrical separation between different components of the device. Metal interconnects are used to establish electrical connections between different parts of the device while minimizing parasitic capacitance. When a control signal is applied to the gate of the standard SCR component, it triggers the device's conductivity between the anode and cathode. The open tap structure, with its low capacitance design, minimizes the capacitive coupling between the standard SCR and the rest of the circuit. This reduction in capacitance allows for faster charging and discharging of the device, making it more suitable for high-speed applications.
[0065] FIG. 10 illustrates a cross-sectional view of a Conventional Fin-based SCR CFSCR device in a modified schematic, in accordance with an embodiment of the present disclosure.
[0066] Referring to FIG. 10, a cross-sectional view 1000 of the convention Fin-based SCR CFSCR device in a modified schematic is disclosed. The CFSCR device features a complex structure that integrates FinFET transistors and SCR functionality. The topmost layer consists of metal contacts, which serve as connection points to external circuitry. Beneath the contact layer is a dielectric material that provides electrical insulation between the metal contacts and the underlying semiconductor layers. Below the dielectric layer is the gate stack of the FinFET transistor. It consists of a gate dielectric (typically high-k dielectric) and a gate electrode (often made of polysilicon). The gate stack wraps around the sides of the fin-like semiconductor structure. The fin-like semiconductor structure serves as the channel region of the FinFET. It extends vertically between the source and drain regions. Doped regions on either side of the fin act as the source and drain terminals of the FinFET. Contacts are made to these regions to enable electrical connections. Below the FinFET structure, there are doped regions that function as the anode and cathode terminals of the SCR. These regions play a crucial role in the SCR's rectification and switching behavior. Situated between the anode and cathode regions, the gate region controls the SCR's conductivity. The gate is formed by a gate dielectric and a gate electrode. The isolation layers are often made of materials like silicon dioxide (SiO2), separate the different components and prevent unwanted electrical interactions and the bottommost layer is the silicon substrate, which is the foundation for the entire device structure.
[0067] FIG. 11 illustrates a capacitance and a TLP I-V of CFSCR devices in the modified circuit scheme, with varying isolation distance between the emitter shorted and floating tap devices, in accordance with an embodiment of the present disclosure.
[0068] Referring to FIG. 11, an illustration 1100 of the capacitance and a TLP I-V of the CFSCR devices is disclosed. According to a device operating principle, when taps of an SCR is floated, the base resistance associated with the NPN and PNP tends to infinity. This causes them to trigger even when a very small current, much below trigger current flows through them. As a result of this, they have very low capacitance, since they respond to any change in the terminal signal very fast as a result of very fast SCR action. This results in the very low capacitance that they have. However, due to the absence of any well pick-ups they have severe latch-up issues, and therefore, while providing low capacitance, they will be vulnerable to both static and dynamic latch up. To address the issue of latch-up an emitter shorted tapped device is put in series with a floating tap device. This increases the overall holding voltage of the device and provides significant dynamics and static latch-up immunity. The device in the modified configuration gives a reduction in capacitance between 5X to 5 orders depending on the baseline device used.
[0069] FIG. 12 illustrates a TCAD schematic of CFSCR and DTFSCR devices in modified schematic, in accordance with an embodiment of the present disclosure.
[0070] Referring to FIG. 12, a Technology Computer Aided design (TACD) schematic 1200 of the CFSCR and DTFSCR devices is disclosed. CFSCR could potentially involve the integration of Copper (Cu) materials into the FinFET and SCR device structure. There can be a silicon substrate with appropriate doping, a FinFET Gate with gate material of polysilicon and a dielectric nature. The source and drain are doped regions with contacts and the SCR region comprises anode and cathode regions which are doped regions with contacts with a gate material of copper with dielectric. There may be copper metal layers for interconnecting different parts of the device and dielectric isolation layers (e.g., SiO2) for separating different components. A DTFSCR would involve a FinFET-based SCR with dual triggering mechanisms and a silicon substrate with appropriate doping. Again, it will comprise a FinFET Gate, a source and drain, an SCR region with anode and cathode regions along with a gate region and dual triggering mechanisms and dielectric isolation layers.
[0071] FIG. 13 illustrates a capacitance of DTFSCR devices in modified scheme showing five orders of reduction in capacitance, based on the optimized Liso, in accordance with an embodiment of the present disclosure.
[0072] Referring to FIG. 13, an illustration 1300 of a capacitance of the DTFSCR devices is disclosed. A five-order reduction in capacitance is a significant improvement in semiconductor device design, indicating a substantial decrease in the capacitive effects that can impact the performance of electronic circuits. One common approach to reducing capacitance is to scale down the dimensions of the semiconductor device. Smaller dimensions generally lead to lower capacitance due to reduced overlap between different layers of the device. This could involve shrinking the gate length, width, or other dimensions of the device. The choice of dielectric material between different layers of the device can impact capacitance. Using materials with lower relative permittivity (dielectric constant) can reduce the capacitance between layers. Introducing spacers of controlled thickness between different layers can reduce the effective capacitance by increasing the physical separation between conducting elements. Applying mechanical strain to the semiconductor material can alter its properties, including capacitance.
[0073] In an embodiment, by carefully engineering strain, it may be possible to reduce capacitance effects. Stacking semiconductor layers in a three-dimensional configuration can reduce the lateral footprint of the device, potentially reducing capacitance. Improved isolation between different components of the device can minimize unwanted capacitive coupling. Modifying the gate insulator material and structure can influence the capacitance of the device. Lower capacitance allows for faster charging and discharging of the device, which is crucial for high-speed operations. Reduced capacitance means less energy is required to charge and discharge the device, contributing to lower power consumption. Lower capacitance helps in maintaining signal integrity, reducing signal degradation and improving overall device performance. Lower capacitance can also help reduce the susceptibility of the device to external noise and interference.
[0074] It is to be appreciated by a person skilled in the art that while various embodiments of the present disclosure have been elaborated for a low capacitance FinFET SCR. However, the teachings of the present disclosure are also applicable for other types of applications as well, and all such embodiments are well within the scope of the present disclosure. However, a low capacitance FinFET SCR, and all such embodiments are well within the scope of the present disclosure without any limitation.
[0075] Moreover, in interpreting the specification, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0076] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are comprised to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE PRESENT DISCLOSURE
[0077] The present disclosure provides a device for a low capacitance FinFET SCR.
[0078] The present disclosure provides a device for the lower capacitance in a Low Capacitance FinFET SCR reduces the charge storage and discharge times, leading to faster switching speeds.
[0079] The present disclosure provides a device with reduced capacitance, in which the gate-to-drain charge (Qgd) and gate-to-source charge (Qgs) are minimized.
[0080] The present disclosure provides a device with low capacitance FinFET SCRs are well-suited for high-frequency applications as the reduced capacitive load allows the device to operate efficiently at higher frequencies, making it suitable for RF amplification and high-speed signal processing.
[0081] The present disclosure provides a device in which lower capacitance reduces the vulnerability of the SCR to noise and parasitic effects which results in improved noise immunity and signal integrity, especially in environments with high electromagnetic interference (EMI) or radio frequency interference (RFI).
[0082] The present disclosure provides a device that allows for compact and densely packed circuit designs which is particularly beneficial for integrated circuits where space is limited and where multiple components need to be integrated on a single chip.
[0083] The present disclosure provides a device that reduces the capacitive coupling between neighboring devices, mitigating the risk of cross-talk and unwanted interactions between different parts of the circuit which leads to better isolation and improved overall circuit performance.

,CLAIMS:1. A semiconductor device (100) comprising:
a Silicon Controlled Rectifier (SCR) (102) comprising:
a floating tap SCR device (104); and
an emitter shorted SCR device (106) connected in series with the floating tap SCR device (104),
wherein the combination of the floating tap SCR device (104) and the emitter shorted SCR device (106) enables a reduction in capacitance for a predetermined isolation distance between the floating tap SCR device (104) and the emitter shorted SCR device (106).

2. The device (100) as claimed in claim 1, wherein the reduction in capacitance achieved by the combination of the floating tap SCR device (104) and the emitter shorted SCR device (106) ranges between 5X to 5 orders of magnitude.

3. The device (100) as claimed in claim 1, wherein the floating tap SCR device (104) is configured such that a base resistance of associated NPN and PNP transistors tends towards infinity when the taps are floated enabling a low capacitance response to changes in terminal signals.

4. The device (100) as claimed in claim 1, wherein the SCR (102) comprises:
a doped silicon substrate;
a Fin Field Effect Transistor (FinFET) gate comprising polysilicon as the gate material;
a source and a drain region, each doped with metal contacts; and
a gate region and an SCR region comprising anode and cathode regions with copper as the gate material.

5. The device (100) as claimed in claim 1, wherein one or more dielectric isolation layers separate the floating tap SCR device (104) and the emitter shorted SCR device (106).

6. The device (100) as claimed in claim 5, wherein the one or more dielectric isolation layers are configured to optimize the capacitance reduction for a predetermined isolation distance.

7. The device (100) as claimed in claim 1, wherein the emitter shorted SCR device (106) is configured to increase an overall holding voltage of the semiconductor device (100).

8. The device (100) as claimed in claim 1, wherein the dielectric material used in the one or more dielectric isolation layers has a lower relative permittivity to reduce capacitance in the device (100).

9. The device (100) as claimed in claim 1, wherein the SCR device (102) is implemented in a three-dimensional stacked configuration.