I/WE CLAIM:
1. An electronic processing system, comprising:
a processor;
memory communicatively coupled to the processor; and logic communicatively coupled to the processor to:
determine if a wake event corresponds to a wake from a zero-power state of an operating system (OS) of the electronic processing system,
determine if a run-time state is valid to wake the OS from the zero-power state, and
wake the OS from the zero-power state to the run-time state if the run-time state is determined to be valid.
2. The system of claim 1, wherein the logic is further to:
determine if a wake vector is available, the wake vector including
information related to a transition of the OS to the zero-power state; and
wake the OS from the zero-power state based on the wake vector, if the wake vector is determined to be available.
3. The system of claim 2, wherein the logic is further to:
replay an initialization sequence from the zero-power state, if the wake vector is determined to be available.
4. The system of claim 2, wherein the logic is further to:
determine if the memory includes a multi-level memory with at least one
level of non-volatile memory.
5. The system of claim 4, wherein the logic is further to:
receive an indication of a transition to a zero-power state; and
create the wake vector, if the memory is determined to include the multi¬level memory with at least one level of non-volatile memory.

6. The system of claim 5, wherein the logic is further to:
initiate a flush of volatile memory to the non-volatile of the multi-level
memory based on the received indication of the transition to the zero-power state.
7. The system of claim 4, wherein the nonvolatile memory comprises
phase change memory.
8. A semiconductor package apparatus, comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
determine if a wake event corresponds to a zero-power state of an operating system (OS),
determine if a run-time state is valid to wake from the zero-power state, and
wake the OS from the zero-power state to the run-time state if the run-time state is determined to be valid.
9. The apparatus of claim 8, wherein the logic is further to:
determine if a wake vector is available, the wake vector including
information related to a transition of the OS to the zero-power state; and
wake the OS from the zero-power state based on the wake vector, if the wake vector is determined to be available.
10. The apparatus of claim 9, wherein the logic is further to:
replay an initialization sequence from the zero-power state, if the wake
vector is determined to be available.
11. The apparatus of claim 9, wherein the logic is further to:

determine if a system memory includes a multi-level memory with at least one level of non-volatile memory.
12. The apparatus of claim 11, wherein the logic is further to:
receive an indication of a transition to a zero-power state; and
create the wake vector, if the system memory is determined to include the multi-level memory with at least one level of non-volatile memory.
13. The apparatus of claim 12, wherein the logic is further to:
initiate a flush of volatile memory to the non-volatile memory of the multi¬
level memory based on the received indication of the transition to the zero-power
state.
14. The apparatus of claim 11, wherein the non-volatile memory comprises phase change memory.
15. The apparatus of claim 8, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.
16. A method of waking an operating system, comprising:
determining if a wake event corresponds to a zero-power state of an
operating system (OS);
determining if a run-time state is valid to wake from the zero-power state, and
waking the OS from the zero-power state to the run-time state if the run¬time state is determined to be valid.
17. The method of claim 16, further comprising:
determining if a wake vector is available, the wake vector including
information related to a transition of the OS to the zero-power state; and

waking the OS from the zero-power state based on the wake vector, if the wake vector is determined to be available.
18. The method of claim 17, further comprising:
replaying an initialization sequence from the zero-power state, if the wake vector is determined to be available.
19. The method of claim 17, further comprising:
determining if a system memory includes a multi-level memory with at least one level of non-volatile memory.
20. The method of claim 19, further comprising:
receiving an indication of a transition to a zero-power state; and
creating the wake vector, if the system memory is determined to include
the multi-level memory with at least one level of non-volatile memory.
21. The method of claim 20, further comprising:
initiating a flush of volatile memory to the non-volatile memory of the multi-level memory based on the received indication of the transition to the zero-power state.
22. The method of claim 19, wherein the non-volatile memory
comprises phase change memory.