Sign In to Follow Application
View All Documents & Correspondence

Low Latency Digital Signature Processing With Side Channel Security

Abstract: A low-latency digital-signature with side-channel security is described. An example of an apparatus includes a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit, wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

Get Free WhatsApp Updates!
Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
24 August 2022
Publication Number
13/2023
Publication Type
INA
Invention Field
COMMUNICATION
Status
Email
Parent Application

Applicants

INTEL CORPORATION
2200 Mission College Boulevard, Santa Clara, California 95054, USA

Inventors

1. SANTOSH GHOSH
7638 NE Prefontaine St, Hillsboro, OR, USA, 97124
2. ANDREA BASSO
Flat 3, Holme House, Sulgrave Road, London, UK, W6 7QQ
3. MANOJ SASTRY
4006 NW Riggs Drive, Portland, OR, USA, 97229

Specification

Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/484,870 filed on 24 September 2021 and titled “LOW-LATENCY DIGITAL-SIGNATURE PROCESSING WITH SIDE-CHANNEL SECURITY” the entire disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD
[0002] Embodiments described herein generally relate to the field of electronic devices and, more particularly, low-latency digital signature processing with side-channel security.

BACKGROUND
[0003] Quantum computing is expected to enable attackers to solve problems that were previously impractical to attempt, including the solving of cryptographic mathematics. Attacks may utilize side channels to obtain signals from cryptographic computation, and apply quantum computing to determine secret values. As a result, any existing cryptographic methods may potentially be broken.
[0004] Dilithium (Crystals-Dilithium) is a lattice based post-quantum digital signature protocol that is a finalist in the National Institute of Standards and Technology (NIST) Post-Quantum Cryptography (PQC) standardization competition. Such technology is expected to provide greatly improved security in digital signature technology.
[0005] However, the Dilithium technology requires high levels of computations in polynomial multiplication, and thus will be challenging to implement efficiently for security applications, particularly in devices with limited resources.

BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Embodiments described here are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements.
[0007] FIG. 1 is an illustration of an system or apparatus to generate a digital signature, according to some embodiments;
[0008] FIG. 2 is an illustration of an NTT algorithm operation that may be utilized in digital signature operation, according to some embodiments;
[0009] FIG. 3 is an illustration of an apparatus to support polynomial multiplication in digital signature generation;
[0010] FIG. 4 is an illustration of an apparatus to support improved operation in polynomial multiplication for digital signature generation, according to some embodiments;
[0011] FIGS. 5A-5C illustrate algorithms for processing for polynomial multiplication in Dilithium digital signature generation, according to some embodiments;
[0012] FIG. 6 is an illustration of a process for digital signature operation, according to some embodiments; and
[0013] FIG. 7 illustrates an embodiment of an exemplary computing architecture for operations including low-latency digital signature processing with side-channel security, according to some embodiments.

DETAILED DESCRIPTION
[0014] Embodiments described herein are directed to a low-latency digital signature processing with side-channel security.
[0015] Public key cryptography, also referred to as asymmetric cryptography, is in general a cryptographic system that uses pairs of keys in encryption, the pairs including public keys that may be publicly known and private keys that are securely maintained and only known by the key owner. The key pairs are generated utilizing cryptographic algorithms that are based on difficult mathematical problems.
[0016] It is expected that classical public-key cryptography, such as Elliptic Curve Cryptography (ECC), Elliptic Curve Digital Signature Algorithm (ECDSA), Diffie-Hellman (DH), Rivest Shamir Adleman (RSA), Digital Signature Algorithm (DSA), will be broken by quantum computers, referring to computers that exploit properties of quantum states to perform computation. Further, adversaries may be currently mining data from cryptographic operations to implement when sufficient quantum computing technology is available.
[0017] For this reason, Post-Quantum Cryptography Standardization is a program and competition by the National Institute of Standards and Technology (NIST) to update their standards to include post-quantum cryptography. However, there is a pressing need to develop post quantum secure KEM solutions as soon as possible.
, Claims:1. An apparatus comprising:
a coefficient multiplier circuit to perform polynomial multiplication, the coefficient multiplier circuit providing Number Theoretic Transform (NTT) and INTT (Inverse NTT) processing; and
one or more accessory operation circuits coupled with the coefficient multiplier circuit, each of the one or more accessory operation circuits to perform a computation based at least in part on a result of an operation of the NTT/INTT coefficient multiplier circuit;
wherein the one or more accessory operation circuits are to receive results of operations of the NTT/INTT coefficient multiplier circuit prior to the results being stored in a memory.

Documents

Application Documents

# Name Date
1 202244048279-US 17484870-DASCODE-5465 [24-08-2022].pdf 2022-08-24
2 202244048279-FORM 1 [24-08-2022(online)].pdf 2022-08-24
3 202244048279-DRAWINGS [24-08-2022(online)].pdf 2022-08-24
4 202244048279-DECLARATION OF INVENTORSHIP (FORM 5) [24-08-2022(online)].pdf 2022-08-24
5 202244048279-COMPLETE SPECIFICATION [24-08-2022(online)].pdf 2022-08-24
6 202244048279-FORM-26 [24-11-2022(online)].pdf 2022-11-24
7 202244048279-FORM 3 [21-02-2023(online)].pdf 2023-02-21
8 202244048279-Proof of Right [20-04-2023(online)].pdf 2023-04-20
9 202244048279-FORM 3 [21-08-2023(online)].pdf 2023-08-21
10 202244048279-FORM 3 [21-02-2024(online)].pdf 2024-02-21
11 202244048279-FORM 18 [17-09-2025(online)].pdf 2025-09-17