LOW PHASE NOISE QUADRATURE OSCILLATORS CROSS-REFERENCES TO RELATED APPLICATIONS [0001] None FIELD OF THE INVENTION [0002] The disclosure relates generally to voltage control oscillator and in particular to noise reduction in quadrature LC voltage control oscillators. DESCRIPTION OF THE RELATED ART [0003] Quadrature (I/Q) carrier generators with low phase noise and small phase error are integral to modern high-performance direct conversion transceivers. Phase noise causes reciprocal mixing of undesired signals into the desired signal band. Quadrature phase error results in poor image rejection or degraded error vector magnitude (EVM) and adjacent channel power ratio (ACPR). Quadrature VCOs (QVCO) with coupling transistors in series with the switching transistors combine low phase noise with small phase error. But they nonetheless have higher 1/f3 phase noise than a single-phase VCO. [0004] The US patent application US20120249250A1 relate to circuits for quadrature signals generation in communication systems. The US patent US8963648B2 discloses a method of reducing phase noise in an oscillator having a resonant circuit. Another US patent US8044741B2 discloses a method of reducing flicker noise in an oscillator. A novel and useful oscillator topology that show improved phase noise performance is demonstrated in US9197221B2. "A Capacitive-Coupling Technique with Phase Noise and Phase Error Reduction for Multi-Phase Clock Generation," Zhao et al (2014) proposes capacitive coupling techniques that may improve the phase noise performance in multi-phase oscillators while maintain good phase accuracy over wide frequency range. Colpitts architecture based Quadrature VCO(QVCO) introduced in "A 0.6-V Quadrature VCO With Enhanced Swing and Optimized Capacitive Coupling for Phase Noise Reduction," Zhao et al (2012) has low phase noise, but has a limited tuning range and startup issue. The invention discloses a novel SQVCO with noise suppressing means that overcomes some of the disadvantages discussed above. SUMMARY OF THE INVENTION [0006] In various embodiments a quadrature oscillator configured to generate oscillating output voltage that characterized by suppressed noise levels is disclosed. The quadrature oscillator includes a first voltage controlled oscillator coupled to a second voltage controlled oscillator that may run in quadrature and is biased with either a current source or a voltage source. Each oscillator includes a pair of cross-coupled switching transistors, a tank circuit configured to control the frequency of the oscillating output voltage, at least one coupling circuit comprising a pair of coupling transistors connected in series with the respective switching transistor, at least one phase noise suppressing means connected to the drain of each of the switching transistor. [0007] In various embodiments the phase noise suppressing means is selected from one of at least one coupling capacitor connected to the drain of each of the switching transistor, at least one coupling capacitor differentially connected between the drain nodes of the switching transistors in the first oscillator and the second oscillator, one or more coupling capacitors connected as a ring between the drain nodes of the switching transistors of the first oscillator and the second oscillator, a coupling capacitor connected from the drain of the switching transistors to the output nodes or at least one coupling transistor connected in parallel to each of the coupling transistors of the first oscillator and the second oscillator wherein the gates of the coupling transistors are driven by 180° out of phase signals with respect to the gate signals of the coupling transistors of the first oscillator and the second oscillator. [0008] In some embodiments the switching transistors of the quadrature oscillator are semiconductor devices configured to exhibit negative transconductance to compensate for the tank losses. In various embodiments the coupling transistors of the quadrature oscillators are semiconductor devices that are configured to couple the first oscillator and the second oscillator. [0009] The value of the coupling capacitor that forms the noise suppressing means in various embodiments is in the range ^ — Q ~ Q where C is the single ended tank capacitance and Q is the quality factor. [0010] In some embodiments the switching transistors and the coupling transistors are identical. In some embodiments a tail tank resonator is connected to the quadrature oscillator to voltage bias the first oscillator and the second oscillator. In some embodiments a tail tank resonator is connected to the quadrature oscillator when the quadrature oscillator is current biased with low output impedance current source at RF due to parasitic drain capacitances. [0011] In various embodiments a method of reducing phase noise in a series-coupled quadrature voltage controlled oscillator that comprises a first voltage controlled oscillator coupled to a second voltage controlled oscillator to run in quadrature and biased with either a current source or a voltage source where each oscillator includes a pair of cross-coupled switching transistors connected to a tank circuit, at least one coupling circuit comprising a pair of coupling transistors connected in series with the respective switching transistor is disclosed. [0012] In various embodiments the method includes attaching at least one phase noise suppressing means to the drain of each of the switching transistors. This may enable injecting noise into the tank circuit twice in a cycle and obtaining a symmetric impulse sensitivity function (ISF) that may reduce the phase noise in the series-coupled quadrature voltage controlled oscillator. [0013] In various embodiments the phase noise suppressing means is selected from configuration A comprising at least one coupling capacitor connected to the drain of each of the switching transistors, configuration B comprising at least one coupling capacitor differentially connected between the drain nodes of the switching transistors in the first oscillator and the second oscillator, configuration C comprising one or more coupling capacitors connected as a ring between the drain nodes of the switching transistors of the first oscillator and the second oscillator, configuration D comprising a coupling capacitor connected from the drain of the switching transistors to the output nodes or configuration E comprising at least one coupling transistor connected in parallel to each of the coupling transistors of the first oscillator and the second oscillator. The gate signals of the first oscillator and the second oscillator are 180° out of phase with respect to the gate signals of the coupling transistors of the first oscillator and the second oscillator. [0014] In some embodiments when the oscillator is current-biased the phase noise is lower than -115 dBc/Hz at 100 kHz and -135 dBc/Hz at 1MHz and the figure of merit (FoM) is at least 190 dB at 100kHz or at 1MHz. [0015] In various embodiments when the oscillator is a voltage-biased series-coupled quadrature voltage controlled oscillator the phase noise is lower than -110 dBc/Hz at 100 kHz and -135 dBc/Hz at 1MHz and the figure of merit (FoM) is at least 190 dB at 100kHz and at 1MHz. [0016] In various embodiments an integrated circuit chip incorporating the method is disclosed. The integrated chip may produces an output signal that has low phase noise and low phase error. In some embodiments Quadrature carrier generators characterized by low phase noise and low phase error may be developed by incorporating the method. [0017] This and other aspects are disclosed herein. BRIEF DESCRIPTION OF THE DRAWINGS [0018] The invention has other advantages and features which will be more readily apparent from the following detailed description of the disclosure and the appended claims, when taken in conjunction with the accompanying drawings, in which: [0019] FIG. 1A illustrates series-coupled quadrature voltage controlled oscillator with coupling capacitor connected to the drain of each of the switching transistors. [0020] FIG. IB illustrates the series-coupled quadrature voltage controlled oscillator with differentially connected coupling capacitor. [0021] FIG. 1C illustrates the series-coupled quadrature voltage controlled oscillator with coupling capacitors connected as a ring between the drain nodes of switching transistors. [0022] FIG. ID shows the series coupled quadrature voltage controlled oscillator with coupling capacitors connected from the drain of the switching transistors to the output nodes [0023] FIG. IE illustrates the series-coupled quadrature voltage controlled oscillator with coupling transistors connected in parallel to each of the coupling transistors. [0024] FIG. IF shows the tail tank circuit attached during voltage bias or current biased with low output impedance current source. [0025] FIG. 2A illustrates the method of reducing phase noise in a series-coupled quadrature voltage controlled oscillator. [0026] FIG. 2B shows the gate voltages Vip and Vim of the series-coupled LC voltage controlled oscillator. [0027] FIG. 2C illustrates the drain current of switching transistor 120-2. [0028] FIG. 2D illustrates the current in the switching transistor 120-1.. [0029] FIG. 2E illustrates the current flowing through the coupling transistor 130-2. [0030] FIG. 2F illustrates the the gate voltages of the voltage controlled oscillator may be shifted by noise sources v„. [0031] FIG. 2G shows the drain current of switching transistor 120-2.. [0032] FIG. 2H illustrates the current in the switching transistor 120-1. [0033] FIG. 21 shows the two peaks of the error current that is injected into the tank. [0034] FIG. 3A shows the SQVCO with Cc connected at the drain of the switching transistor. [0035] FIG 3B illustrates the simulated waveforms and ISFs of low frequency version of SQVCO 1 [0036] 3C illustrates the simulated waveforms and phase noise comparison of low frequency version of SQVCO 1. [0037] FIG 4 shows the FoM at 100kHz Vs Ccfor low frequency SQVCO-1, SQVCO-2, SQVCO-3. [0038] FIG. 5A illustrates the ISF waveform of SQVC04.. [0039] FIG 5B shows FoM variation with Cc of SQVC03, SQVC04.. [0040] FIG. 5C illustrates the phase noise in SQVC03, SQVC04 at 2.4 GHz [0041] [0042] FIG. 6A shows SQVC05 having coupling transistors connected in parallel to the existing coupling transistors. [0043] FIG. 6B illustrates the ISF of SQVC05 at 2.4GHz. [0044] FIG.6C shows the phase noise and FoM of voltage biased SQVC05 at 2.4GHz. [0045] FIG. 7A illustrates the block diagram of Chip 1 [0046] FIG. 7B shows the phase noise comparison of SQVCO0 with SQVC03. [0047] FIG. 7C illustrates the phase noise in voltage-biased SQVC04. [0048] FIG. 7D shows the phase noise across tuning range 2.35 to 2.6 GHz. [0049] FIG. 7E illustrates the phase error across 5 chips DETAILED DESCRIPTION [0050] While the invention has been disclosed with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from its scope. [0051] Throughout the specification and claims, the following terms take the meanings explicitly associated herein unless the context clearly dictates otherwise. The meaning of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on." Referring to the drawings, like numbers indicate like parts throughout the views. Additionally, a reference to the singular includes a reference to the plural unless otherwise stated or inconsistent with the disclosure herein. [0052] The invention in its various embodiments proposes a method of reducing phase noise in a series-coupled quadrature voltage controlled oscillator. [0053] In various embodiments a series-connected voltage controlled quadrature oscillator 100 (SQVCO) configured to generate oscillating output voltage that is characterized by suppressed noise levels is disclosed. The SQVCO 100 as shown in FIG. 1A includes a first voltage controlled oscillator (VCO) 110-1 coupled to a second voltage controlled oscillator 110-2 to run in quadrature. The first voltage controlled oscillator 110-1 and the second voltage controlled oscillator 110-2 are biased with either a current source 112-1, 112-2 or a voltage source. Each voltage controlled oscillator 110-1, 110-2 includes a pair of cross-coupled switching transistors 120-1, 120-2, 120-3, 120-4 driven by voltages Vim, Vip, VQm, VQP respectively, a tank circuit 115-1, 115-2, at least one coupling circuit that includes a pair of coupling transistors 130-1, 130-2 and 130-3, 130-4 connected in series with the respective switching transistors 120-1, 120-2 and 120-3, 120-4 and at least one phase noise suppressing means that is connected to the drain of each of the switching transistors 120-1, 120-2 and 120-3, 120-4. In some embodiments the tank circuit 115-1, 115-2 includes LC components and is configured to control the frequency of the oscillating output voltage. [0054] In various embodiments the phase noise suppressing means is selected from one of configuration A, configuration B configuration C configuration D or configuration E. Each configuration includes one or more coupling capacitors connected to the drain of each switching transistor. In various embodiments the noise suppressing means prevent the switching transistor to enter into the triode region during one of the zero crossings of the oscillating waveforms. This enables the switching transistors to inject noise vn, twice into the tank circuit in each cycle to get a symmetric impulse sensitive function(ISF). In various embodiments the net phase shift due to the correlated 1/f noise is zero over the VCO period. [0055] In various embodiments configuration A includes at least one coupling capacitor 140-1, 140-2, 140-3, 140-4 connected to the drain of each of the switching transistors 120-1, 120-2, 120-3, 120-4 as shown in FIG. 1A. In various embodiments the drain current of the switching transistor 120-2 finds a path through the coupling capacitor 140-2 at zero crossing of the signals in the switching transistors 120-1 and 120-2. This may prevent the switching transistor 120-2 from collapsing into deep triode region. In various embodiments the switching transistor 120-2 injects noise twice into the tank 115-1. In some embodiments the injection of the noise twice into the tank circuit makes the ISF from vn symmetric. This suppresses the 1/f3 phase noise. [0056] In various embodiments configuration B includes at least one coupling capacitor 240-1, 240-2 differentially connected as shown in FIG. IB between the drain nodes of the switching transistors 220-1, 220-2 of the first oscillator 210-1 and between the drain nodes of the switching transistors 220-3, 220-4 of the second oscillator 210-2.In various embodiments the current through the switching transistor 220-1 passes through the coupling capacitor 240-1 and the coupling transistor 230-2. The current through the coupling transistor 230-2 in some embodiment delays the pulse width that may result in injecting noise twice in a cycle to obtain a symmetric ISF. [0057] In some embodiments configuration C includes one or more coupling capacitors 340-1, 340-2, 340-3, 340-4 connected as a ring as shown in FIG. 1C between the drain nodes of the switching transistors 320-1, 320-2, 320-3, 320-4 of the first oscillator 310-1 and the second oscillator 310-2. [0058] In various embodiments configuration D includes coupling capacitors 440-1, 440-2, 440-3, 440-4 connected from the drain of the switching transistors 420-1, 420-2, 420-3, 420-4 to the output nodes as shown in FIG. ID. The effect of transistor parasitics Cgs 451, 452, 453, 454 during high frequency operations is compensated by the capacitors 440-1, 440-2, 440-3, 440-4. In various embodiments the tail tank 460 is connected differentially between the first voltage controlled oscillator 410-1 and the second voltage controlled oscillator 410-2 to improve the common-mode impedance. [0059] In various embodiments configuration E may include at least one coupling transistor 540-1, 540-2, 540-3, 540-4 connected in parallel as shown in FIG. IE to each of the coupling transistors 530-1, 530-2, 530-3, 530-4 of the first oscillator 510-1 and the second oscillator 510-2. In some embodiments the gates of the coupling transistors 540-1, 540-2, 540-3, 540-4 are driven by 180° out of phase signals with respect to the gate signals of the coupling transistors 530-1, 530-2, 530-3, 530-4 of the first oscillator and the second oscillator. In various embodiments the coupling transistors 540-1, 540-2, 540-3, 540-4 are at least 7 times smaller than the coupling transistors 530-1, 530-2, 530-3, 530-4. In various embodiment the coupling transistors 540-1, 540-2, 540-3, 540-4 may suppress the flicker noise upconversion from switching transistors in the SQVCO. The coupling transistor 540-2 provides a low impedance path from drain of switching transistor 520-2 during the first zero crossing and the coupling transistor 540-2 is off. This again avoids the drain of switching transistor 520-2 from collapsing to zero during the zero crossing, thereby maintaining the waveform symmetry. Because of this, the switching transistor 520-2 again injects noise twice every cycle there by maintaining the ISF symmetry and reducing the 1/f noise upconversion. [0060] The switching transistors in various embodiments are semiconductor devices that are used as negative transconductors that may compensate for the tank losses. The switching transistors may include semiconductor devices including MOSFETs that are identical. In various embodiments the coupling transistors are semiconductor devices including MOSFETS that are configured to couple the first oscillator and the second oscillator. The coupling transistors in various embodiments are identical. [0061] In various embodiments the coupling capacitor that forms the suppressing means may have a value that may prevent the switching transistors from collapsing into deep triode region with zero current when the two input waves cross. The value of the coupling capacitor is in the range ^