Claims:1. An electrostatic discharge (ESD) protection circuit electrically connected to a scan line and a data line of a Large Area Electronics, the ESD protection circuit comprising:
a first set of at least two back-to-back MISIS Thin-Film-Transistor (TFT) devices with one end of the at least two MISIS TFT devices of the first set connected to the scan line between two resistors R1 and R2 and the other end connected to at least one ESD bus;
a second set of least two back-to-back MISIS TFT devices with one end of the at least two MISIS TFT devices of the second set connected to the data line after a single resistor R1 in the data line and the other end connected to at least one ESD bus.

2. The ESD protection circuit as claimed in claim 1, wherein the at least back-to-back MISIS TFTs are connected to each of the scan lines and the data lines of the Large Area Electronics.

3. The ESD protection circuit as claimed in claim 1, wherein the circuit further comprises a third set of at least two back-to-back MISIS TFT devices with their one end connected to VDD power line and their other end connected to VSS power line.

4. The ESD protection circuit as claimed in claim 3, wherein the MISIS TFTs has a structure of Metal gate – Insulator – thin Semiconductor layer – Insulator – Semiconductor channel MISIS with a carrier injection terminal in the thin semiconductor layer close to gate terminal, wherein the carrier injection terminal works as a secondary source contact.

5. The ESD protection circuit as claimed in claim 4, wherein during an ESD event the MISIS TFTs work as diode connected TFTs and thereby sinks large currents due to their low on resistance.

6. The ESD protection circuit as claimed in claim 3, wherein the first set, the second set and the third set of the at least two back-to-back MISIS TFT devices in the scan line, the data line and the power lines respectively comprise at least one MISIS TFT device for positive ESD stress and at least one MISIS TFT device for negative ESD stress.

7. The ESD protection circuit as claimed in claim 3, wherein MISIS TFTs are configured in the circuit in any of gate coupled mode or in grounded gate mode.

8. The ESD protection circuit as claimed in claim 1, wherein R1 is adapted to reduce ESD stress on the MISIS TFT devices of the protection circuit in the scan lines and the data lines, and wherein R1 has value in range of few k ohms.

9. The ESD protection circuit as claimed in claim 1, wherein R2 is adapted to reduce ESD stress on TFTs of the LAE in the scan lines, and wherein R2 has value in range of few M ohms.

10. The ESD protection circuit as claimed in claim 4, wherein the MISIS TFTs incorporate a secondary drain contact along with a secondary source contact in the thin semiconductor layer close to the gate terminal, and wherein the thin intermediate layer acts as a TFT channel.

11. The ESD protection circuit as claimed in claim 4, wherein the MISIS TFTs include lightly doped Source and Drain extensions, wherein the Source and Drain extensions work to improve breakdown voltage of the MISIS TFTs.

12. The ESD protection circuit as claimed in claim 4, wherein the MISIS TFTs are two-terminal devices in any of gate-coupled mode or in grounded-gate mode.

13. The ESD protection circuit as claimed in claim 12, wherein the two terminal MISIS TFTs in gate-coupled mode is realized by shorting the Gate and Drain contacts and the Source and secondary Source contacts; and the two terminal MISIS TFTs in grounded gate mode is realized by shorting the Source- Secondary Source-Gate contacts.

14. The ESD protection circuit as claimed in claim 4, wherein the carrier injection terminal of the MISIS TFTs surrounds the gate, and wherein the carrier injection terminal surrounding the gate enables accumulation of significant amount of charge carriers under the gate in less time for effective screening of gate electric field.
, Description:TECHNICAL FIELD
The present disclosure relates generally to the field of electrostatic discharge (ESD) protection circuit. In particular, the present disclosure pertains to an active dielectric based low power ESD protection device and circuit.

BACKGROUND
Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
A chip of integrated circuit can be divided into a core circuit and an Input/Output (I/O) circuit. The core circuit and the I/O circuit are respectively driven by different power sources with different voltages. In order to receive input from external power sources the chip of the integrated circuit has core power pad and I/O power pad disposed thereon supplying power to the core circuit and the I/O circuit respectively.
However, during processes such as manufacturing, testing, packaging and delivering etc., the pads easily transfer electrostatic charges - a phenomenon which is commonly known as electrostatic discharge (ESD). ESD is a critical problem for any kind of integrated circuits. ESD is a very short duration current pulse which discharges between the two bodies of unequal charge or potential. This discharge can produce significant amount of heat inside the electronic device leading to a thermal breakdown and hence the failure of the system. Thus it reduces the production yield significantly. Therefore, concept of on-chip or on-panel ESD protection is very important which refers to the ESD protection devices and circuits integrated with the main functional circuit.
For Large Area Electronics (LAE) such as those used in a display or scanner or image sensor, ESD protection is required for all i/o pads through which core circuit interacts with outside world as ESD event can occur between any of the i/o pads (in scan line/ data line) and ground. ESD can also attack between two different supply lines (e.g. VDD & VSS).
In LAEs key requirements are: 1) low temperature fabrication processes to enable the system design on a glass, plastic or polymer (PDMS) substrate; 2) low cost fabrication processes to reduce cost per unit area; and 3) uniformity of semiconductor material over a large area. Crystalline silicon technology is not suitable for the application as it cannot address any of these requirements of LAE. Therefore, Thin film Transistors (TFT) are used in these devices as elementary building blocks where the semiconductor material is deposited as films over a large substrate at a relatively low temperature with an excellent uniformity over large areas. However, due to absence of any snapback action or BJT kind of operation in the TFTs these devices cannot shunt high ESD current while clamping a low voltage stress across it. Moreover, high on resistance of amorphous material in channel and poor thermal conductivities of glass substrate, gate insulator and channel material cause enormous heat generation during the ESD stress which leads to thermal breakdown of the device.
State of art in respect of ESD protection devices and circuits for Thin Film Transistors (TFT) based large-area electronics provides various solutions. However, these solutions mostly use grounded-gate TFTs (ggTFTs) or gate-drain coupled TFTs (gcTFTs) i.e. diode connected TFTs as ESD protection device in scan line/data line as well as in power line. There are different kinds of topological arrangements of TFTs but all of them use conventional TFTs i.e. with MIS (Metal-Insulator-Semiconductor) structure as the base. Power clamp is also used in power lines. But all these solutions suffer from drawback of large normal mode leakage current.
FIG. 1A and FIG. 1B illustrate typical circuit diagrams for Grounded gate TFT and Diode connected TFT respectively. These are topologically similar to those used in crystalline-Si based MOS technology. However, due to absence of any snapback action or Bipolar Junction Transistor (BJT) kind of operation in the TFTs, these devices cannot shunt high ESD current while clamping a low voltage stress across it. Moreover, high on resistance of amorphous material in channel and poor thermal conductivity of the glass substrate, gate insulator and channel material causes enormous heat generation during the ESD stress which leads to thermal breakdown of the device. This problem can be minimized by increasing the device width (W). On the other hand, they also offer a very high normal mode leakage current, which increases with the increase in W. Thus enhancing the ESD robustness of the circuit causes an increase in normal mode leakage current and hence a substantial battery power consumption.
FIG. 2 illustrates an ESD protection circuit with three connected TFTs both for positive and negative ESD stress as discussed in the United States Patent US7019796B2. Such circuits increase reliability as it still works if one of the devices gets damaged, and it has lower power consumption. However, it offers high turn-on voltage due to series connected TFTs and hence large voltage will develop during the ESD event, which could degrade the inner circuit-TFTs. Moreover, it consumes large layout area.
FIG. 3 illustrates a conventional power clamp used to protect a circuit from ESD event in a power line. In the circuit, the turn-on voltage of the ESD protection device can be controlled by changing the values of resistor R and capacitor C. However, it needs many additional components. Also it cannot reduce normal mode leakage current significantly.
Thus it can be seen that ESD protection devices and circuits in LAE domain are mostly based on conventional ESD protection concepts used in crystalline-Si technology. But all these conventional device structures offer a very high normal mode leakage current and hence they offer a very narrow margin for trade-off between normal mode leakage current and ESD robustness.
In view of above, there exists a dire need to provide an ESD protection scheme that solves the issue of handling ESD robustness in power lines as well as in scan and data lines efficiently thereby reducing battery power consumption.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term “about.” Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Markush groups used in the appended claims.

OBJECTS OF THE INVENTION
A general object of the present disclosure is to provide an ESD protection circuit for Large Area Electronics.
An object of the present disclosure is to provide an ESD protection circuit that reduces battery power consumption significantly while meeting the ESD robustness requirement
An object of the present disclosure is to provide an ESD protection circuit that provides similar kind of ESD robustness as that of a conventional TFT structure, but with a significantly lower normal mode leakage current.
Another object of the present disclosure is to provide an ESD protection circuit that allows increase in width of the ESD device to enhance ESD robustness keeping the leakage current at a very low value.
Yet another object of the present disclosure is to provide an ESD protection scheme that has potential to replace conventional protection for scan line, data line and power lines with similar kind of ESD robustness but with much lesser normal mode leakage current.
Yet another object of the present disclosure is to provide an ESD protection circuit with Metal gate – Insulator – thin Semiconductor layer – Insulator – Semiconductor channel (MISIS) TFT.
Still another object of the present disclosure is to provide an ESD protection circuit with MISIS TFT that requires use of less number of components and thereby occupying much lesser area.
Still another object of the present disclosure is to provide a structure for MISIS TFT that enables improvement in charging time of thin semiconductor layer for a faster gate field screening during low frequency normal mode operation in scan/data line overcoming limitation of optical lithography constraint during fabrication of the MISIS TFT.

SUMMARY
Aspects of the present disclosure relate to an active dielectric based low power Electrostatic Discharge (ESD) protection circuit. In an aspect, the disclosed low power ESD protection circuit incorporates TFT device having a structure of Metal gate – Insulator – thin Semiconductor layer – Insulator – Semiconductor channel (MISIS) with a carrier injection terminal in the thin semiconductor layer closest to the gate terminal working as a secondary source contact (also referred to as Source1 or S1).
In an aspect, carrier injection terminal in MISIS TFT device injects charge at low frequency or the steady state condition and screens most of the gate electric field coupling to the channel thereby significantly reducing normal mode leakage current through the protection device to a very small value. At the same time the device acts as a diode connected TFT and sinks large currents due to its low on resistance during an ESD event which is a very high frequency event. Thus, during an ESD event the disclosed ESD protection circuit is adapted to shunt a large amount of ESD current while clamping a low voltage across it.
In an aspect, the ESD protection circuit can include at least two back-to-back MISIS TFT devices with their one end connected between two resistors R1 and R2 in scan lines, and at least two back-to-back MISIS TFT devices with their one end connected after a single resistor R1 in data lines. Other end of the at least two back-to-back thin-film-transistor (TFT) devices can be connected to at least one ESD bus.
In an aspect, the present disclosure also provides an ESD protection circuit for power lines in a LAE. The ESD protection circuit for power lines can include at least two back-to-back MISIS TFT devices with their one end connected to VDD power line and their other end connected to VSS power line.
In one embodiment, said at least two back-to-back TFT devices, in the scan lines, the data lines and the power lines respectively include one TFT device from said at least two back-to-back TFT devices for the positive ESD stress and the other TFT device from said at least two back-to-back TFT devices for the negative ESD stress.
In an aspect, resistors R1 and R2 used in scan lines and R1 in data lines increase robustness of the ESD protection scheme, such that, R1 reduces ESD stress on the ESD protection device while R2 protects the inner circuit node from a large voltage stress. The data lines do not require R2 as the gate insulator of internal circuit TFT are not stressed in data lines.
In an aspect, two back-to-back TFT devices can be used in gate-coupled mode (gcTFT) or in grounded-gate mode (ggTFT).
In an aspect, MISIS TFT devices used in the disclosed circuit can additionally have a secondary drain contact (also referred to as Drain 1 or D1) along with a secondary source contact (Source1) in the thin semiconductor layer closest to the gate terminal, with the thin intermediate layer acting as a TFT channel. The configuration provides two bias control knobs at the Source1 and Drain 1 contacts which can provide better charge injection and charge extraction control inside the thin semiconductor layer.
In an aspect, MISIS TFT devices used in the disclosed ESD protection circuit can include lightly doped Source and Drain extensions to lower breakdown voltage of the MISIS TFT. This can relax space charges created at junctions and hence improve the breakdown voltage. In an aspect, it increases ESD robustness in terms of the thermal breakdown at the junctions.
In an aspect, the present disclosure provides a two terminal MISIS TFT device with a carrier injection terminal wherein a two terminal configuration is achieved by shorting the Gate-Drain contacts and the Source-Source1 contacts in case of gate-coupled (gcTFT) configuration or by shorting the Source-Source1-Gate contacts in case of grounded-gate (ggTFT) configuration during fabrication of the device. In an aspect a two terminal MISIS TFT device either in gate-coupled (gcTFT) configuration or in grounded-gate (ggTFT) configuration, can result in simplifying layout and reduction in the area.
In an aspect, the present disclosure provides a modified MISIS TFT device having carrier injection terminal that enables effective screening down the gate electric field in much less time. This is achieved by configuring carrier injection terminal to surround gate so that much less time is required for the accumulation of significant amount of charge carriers under the gate which can effectively screen down the gate electric field. In another aspect, the proposed structure of the carrier injection terminal surrounded by the gate does away with requirement of need to keep distance D between the carrier injection terminal and the gate to a significantly low figure that is restricted by optical lithography constraint during fabrication of the MISIS TFT device
Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
FIG. 1A and FIG. 1B illustrate typical circuit diagrams for ESD protection using grounded gate TFT and diode connected TFT respectively.
FIG. 2 illustrates an ESD protection circuit with three connected TFTs both for positive and negative ESD stress as disclosed in the United States Patent number US7019796B2.
FIG. 3 illustrates a conventional power clamp used to protect circuits from ESD event in a power line.
FIG. 4 illustrates a MISIS TFT device as disclosed in the United States Patent number US8053818B2.
FIG. 5A illustrates an exemplary ESD protection circuit using MISIS TFT for scan lines and data lines in a large area electronics in accordance with an embodiment of the present disclosure.
FIG. 5B illustrates an exemplary ESD protection circuit for power lines using MISIS TFT for large area electronics in accordance with an embodiment of the present disclosure.
FIG. 6 illustrates an exemplary schematic arrangement in a MISIS TFT incorporating a secondary drain (D1) in addition to a secondary source (S1) in accordance with embodiments of the present disclosure.
FIG. 7 illustrates an exemplary schematic arrangement in a MISIS TFT with lightly doped source and drain extension in accordance with embodiments of the present disclosure.
FIG. 8 illustrates an exemplary schematic arrangement in a 2-terminal MISIS TFT for Gate-coupled configuration in accordance with embodiments of the present disclosure.
FIG. 9 illustrates an exemplary schematic arrangement in a 2-terminal MISIS TFT for grounded Gate configuration in accordance with embodiments of the present disclosure.
FIG. 10 illustrates an exemplary representation of secondary Source (S1) surrounding gate in three directions in a MISIS TFT in accordance with an embodiment of the present disclosure.
FIG. 11 illustrates an exemplary ESD protection circuit with MISIS TFT used in grounded Gate configuration in accordance with embodiments of the present disclosure.
FIG. 12 illustrates an exemplary simulation setup for 2kV HBM signal stress on scan line in accordance with embodiments of the present disclosure.
FIG. 13 illustrates an exemplary graph showing ESD drain current in accordance with an embodiment of the present disclosure.
FIG. 14 illustrates an exemplary graph showing maximum device temperature in accordance with an embodiment of the present disclosure.
FIG. 15 illustrates an exemplary graph showing ESD voltage stress on gate-drain and ESD field stress inside the dielectric in accordance with an embodiment of the present disclosure.
FIG. 16 illustrates exemplary graphs showing effect of width of MISIS TFT device on maximum device temperature in accordance with an embodiment of the present disclosure.
FIG. 17 illustrates exemplary graphs showing effect of width of MISIS TFT device on ESD stress on gate/ drain (robustness) in accordance with an embodiment of the present disclosure.
FIG. 18 illustrates an exemplary ESD protection circuit for scan lines with MISIS TFT in Gate-coupled configuration and with a resistor R2 between the MISIS TFT and internal TFT in accordance with an embodiment of the present disclosure
FIG. 19 illustrates an exemplary ESD protection circuit for scan lines with MISIS TFT in Gate-coupled configuration and a resistor R2 between the MISIS TFT and the internal TFT and a resistor R1 between input pad and protection device in accordance with an embodiment of the present disclosure.
FIG. 20 illustrates an exemplary ESD protection circuit in data line in accordance with embodiments of the present disclosure.
FIG. 21 illustrates exemplary graphs showing comparison of normal-mode leakage current (transient-state) of MISIS & MIS TFT in accordance with embodiments of the present disclosure.
FIG. 22 illustrates exemplary graphs showing reduction of normal-mode leakage current (transient-state) with a MISIS TFT having secondary Source (S1) contact surrounding gate in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
Embodiments explained herein relate to on-chip or on-panel (for display) ESD protection for Large Area Electronics (LAE) which use TFTs as their elementary building blocks. Due to absence of any snapback action or BJT kind of operation in the TFTs, these devices cannot shunt high ESD current while clamping a low voltage stress across it. The problem is more severe due to materials used. For example, poor thermal conductivities of glass substrate, gate insulator and channel material causes enormous heat generation during the ESD stress which leads to the thermal breakdown of the device. By far in the LAE domain the ESD protection devices and circuits are mostly based on conventional ESD protection concepts used in crystalline-Si technology. But all these conventional device structures offer a very high normal mode leakage current and hence they offer a very narrow margin for trade-off between normal mode leakage current and ESD robustness.
The present disclosure provides an ESD protection scheme which solves the above mentioned problems by offering similar kind of ESD robustness but with a very low normal mode leakage current thereby reducing power consumption without affecting level of ESD protection.
It is to be appreciated that though various embodiments of the present disclosure are explained with respect to electrostatic discharge (ESD) protection circuit being used as a circuit to shunt a large amount of ESD current while clamping a low voltage across it, it is possible to use the disclosed circuit with variations in terms of circuitry arrangement and/or device arrangement that would be evident to those skilled in the art for other purposes and all such variations are well within the scope of the present disclosure without any limitation.
In an embodiment, the disclosed low power ESD protection circuit incorporates TFT device disclosed in United States Patent US8053818B2 and having a structure of Metal gate – Insulator – thin Semiconductor layer – Insulator – Semiconductor channel (MISIS) with a carrier injection terminal in the thin semiconductor layer closest to the gate terminal working as a secondary source contact (Source1/ S1).
FIG. 4 illustrates a MISIS TFT device 400 as disclosed in the United States Patent number US8053818B2. The MISIS TFT device 400 includes source 402 and drain 404 separated by a gap forming a channel 406. The MISIS device 400 further includes a top insulator layer 408 and a bottom insulator layer 414 sandwiching a thin semiconductor layer 410 having a secondary source contact S1 412. The bottom insulator layer 414 includes a gate 416 separated from S1 412 by a distance D. The bottom insulator layer 414 is supported on a glass substrate 418.
In an embodiment, MISIS TFT device 400 in the disclosed ESD protection circuit works as a diode connected TFT during an ESD event thereby sinking large currents due to its low ON resistance. At the same time, the device 400 in the disclosed circuit has an ability to shield the gate field at low frequency and hence reduces normal mode leakage current through the ESD protection circuit to a very small value.
In an embodiment, the ESD protection circuit can include at least two back-to-back MISIS TFT devices such as device 400 or any of its modified versions disclosed in different embodiments of the present disclosure, either in gate-coupled mode (gcTFT) or in grounded-gate mode (ggTFT), with their one end connected between two resistors R1 and R2 in scan lines, and at least two back-to-back MISIS TFT devices such as device 400, with their one end connected after a single resistor R1 in data lines. Other end of the at least two back-to-back thin-film-transistor (TFT) devices can be connected to at least one ESD bus. Further, inclusion of resistors R1 and R2 in the circuit increases robustness of the ESD protection scheme as R1 reduces ESD stress on the ESD protection device while R2 protects inner circuit node from a large voltage stress.
Further, it is to be appreciated that in device 400 or any of its modified version disclosed in this patent, any reference to any of Source/ Drain/ Source1/ Drain1 implies any electrode that makes a good contact (ohmic) with semiconductor implementing whatever fabrication steps needed such as high doping near the metal electrode as shown by n+ regions in different FIGs.
In an aspect, the present disclosure also provides an ESD protection circuit for power lines in a LAE. The ESD protection circuit for power lines can include at least two back-to-back MISIS TFT devices with their one end connected to VDD power line and their other end connected to VSS power line.
FIG. 5A illustrates an ESD protection circuit 500 for scan lines and data lines in large area electronics in accordance with embodiments of the present disclosure. In one embodiment, the ESD protection circuit according to the present disclosure includes MISIS TFT devices such as MISIS TFT of FIG. 4 or any other variant disclosed in the present disclosure, with two resistors in the scan lines and with a single resistor in the data lines.
It is to be noted that though various circuits have been explained in the present disclosure with reference to MISIS TFT device 400 of FIG 4, however reference to MISIS TFT 400 should not be construed to limit the scope to the already patented MISIS TFT device, and the MISIS TFT device referred to here can be either the already patented device structure of FIG 4 or any of its improved version (keeping ESD application in mind) disclosed in various embodiments of the present disclosure. In particular, it can be a MISIS TFT device with the secondary source S1 surrounding gate structure as disclosed in FIG. 10.
In one embodiment shown in FIG. 5A, the ESD protection circuit 500 includes at least two back-to-back MISIS TFT devices 506 and 508 with their one end connected to a scan line 502 between two resistors R1 510 and R2 512 and other end connected to ESD bus 520. In an aspect, at least one of the at least two back-to-back MISIS TFT devices 506 and 508 provide for positive ESD stress in the scan line 502, and at least one of the at least two back-to-back MISIS TFT devices 506 and 508 provide for negative ESD stress in the scan line 502
In an embodiment, the disclosed circuit can further include at least two MISIS TFT devices 514 and 516 with their one end connected to a data line 504 after a single resistor R1 518. In an aspect, at least one of the at least two back-to-back MISIS TFT devices 514 and 516 provide for positive ESD stress in the data line 504, and at least one of the at least two back-to-back MISIS TFT devices 514 and 516 provide for negative ESD stress in the scan line 504.In an embodiment, two back-to-back TFTs such as 506 and 508 can be connected to each of the scan lines such as 502 and likewise two back-to-back TFTs such as 514 and 516 can be connected to each of the data lines such as 504 in LAE; one for positive ESD stress and the other one for negative ESD stress.
In an aspect, the present disclosure also provides an ESD protection circuit for power lines in a LAE. FIG. 5B illustrates an exemplary ESD protection circuit for power lines using MISIS TFT for large area electronics in accordance with an embodiment of the present disclosure. As shown the ESD protection circuit for power lines can include at least two back-to-back MISIS TFT devices with their one end connected to VDD power line and their other end connected to VSS power line. The proposed ESD protection for power lines can replace conventional power clamp such as shown in FIG. 3.
It is to be appreciated that while embodiments illustrated in FIG. 5A and 5B show MISIS TFT devices 506, 508, 514 and 516 arranged in gate coupled mode, this is not a limitation on the disclosed circuit and they can as well be arranged in grounded gate mode. FIG. 11 illustrates an exemplary ESD protection circuit with MISIS TFT 400 used in grounded Gate configuration in accordance with embodiments of the present disclosure. A similar configuration of MISIS TFT 400 in grounded gate mode is possible for ESD protection in power lines.
In an embodiment, MISIS TFT device 400 can be made using any semiconductor material for thin non-crystalline semiconductor layer. In a preferred embodiment, poly-crystalline silicon has been used being widely used material in the AMOLED or LCD displays.
In one embodiment of the present disclosure, MISIS TFT device 400 shown in FIG. 4 can be fabricated with different architectures (shown in FIG. 6 to FIG. 9) for different application requirements. Though the basic device operation is same for all the architectures but they can provide different benefits.
FIG. 6 illustrates an exemplary schematic arrangement of a MISIS TFT 600 incorporating a secondary drain (Drain 1 or D1) in addition to a secondary source (S1) in accordance with embodiments of the present disclosure. The secondary drain (D1) 602 is built on the thin semiconductor layer 410. Thus, the intermediate layer/ thin semiconductor layer 410 also acts as a TFT channel.
In one embodiment, though MISIS TFT 600 is a five terminals device, it can give two bias control knobs at the S1 and D1 contacts which can provide better charge injection and charge extraction control inside the thin semiconductor layer 410.
In one embodiment, breakdown voltage of MISIS TFT 400 can be lowered by using lightly doped source and drain extensions. FIG. 7 illustrates an exemplary schematic arrangement of MISIS TFT 700 that incorporates lightly doped source extension 702 and lightly doped drain extension 704 in accordance with embodiments of the present disclosure. In one implementation, the MISIS TFT 700 can include same internal structures/components as discussed in FIG. 4 or FIG. 6 (or in FIG. 8 and 9 below which disclose two terminal configuration of the device of FIG. 4) above except having the lightly doped source and drain extensions. In an aspect, the lightly doped source extension 702 and lightly doped drain extension 704 can relax space charges created at the junctions and hence can improve the breakdown voltage thereby increasing ESD robustness in terms of thermal breakdown at the junctions.
In one embodiment, though MISIS TFT 400 and its variant MISIS TFT 700 have more than two terminals, they can be fabricated as two terminal devices. FIG. 8 and FIG. 9 illustrate exemplary schematic arrangement in a 2-terminal MISIS TFTs 800 and 900 with Gate-coupled configuration and grounded Gate configuration respectively. As shown, two terminal configurations can be achieved either by shorting the Gate-Drain contacts and the Source-Source1 contacts as shown in FIG. 8 for a gate-coupled (gcTFT) configuration, or by shorting the Source-Source1-Gate contacts as shown in FIG. 9 for a grounded-gate (ggTFT) configuration.
In one implementation, MISIS TFTs 800 and 900 include same internal structures/components as discussed in FIG. 4 or FIG 7 above except for shorting of Gate-Drain contacts and the Source-Source1 contacts (in case of gate-coupled/gcTFT configuration) as shown in FIG. 8 or shorting of Source-Source1-Gate contacts (in case of grounded-gate/ggTFT configuration) as shown in FIG. 9.
In an embodiment, the present disclosure provides a modified MISIS TFT device having carrier injection terminal that enables effective screening down the gate electric field in much less time. This is achieved by configuring the carrier injection terminal to surround the gate so that much less time is required for the accumulation of significant amount of charge carriers under the gate which can effectively screen down the gate electric field. In another aspect, the proposed structure of the carrier injection terminal surrounding the gate does away with requirement of need to keep distance D between the carrier injection terminal and the gate to a significantly low figure that is restricted by optical lithography constraint during fabrication of the MISIS TFT device. FIG. 10 illustrates an exemplary representation of secondary Source (S1) surrounding gate in three directions in a MISIS TFT in accordance with an embodiment of the present disclosure.
In one embodiment, the proposed ESD protection circuit has been validated for its performance using MISIS TFT device 400 of FIG. 4 in gate-coupled (i.e. gate-drain shorted) configuration as depicted in FIG. 5A. In one embodiment, during the validation, channel length L (refer FIG. 4) of the MISIS TFT device 400 was optimized to a value 7 microns to get a high ESD peak current as well as a low normal mode leakage current. Keeping L very low can improve ESD current carry capability but on the other hand a low channel length L shall increase the normal mode leakage current. Moreover, there could be short channel effect and higher stress on drain side if L is kept on being decreased. Offset D (refer FIG. 4) of the Source1 412 from edge of Gate 416 has to be decided based on the ESD event time (typically ~ 0.5 to 500 ns) and the normal mode operation frequency (typically ~ hundreds of Hz) of the circuit which is to be protected from the ESD. First, capacitance between the gate 416 and thin semiconductor layer 410 can be calculated and then based on required RC time constant we need to calculate resistance value. This RC time should be such that it is larger than the ESD event time and smaller than the regular mode operation time period of the internal circuit to be protected. Then corresponding to this resistance value offset D needs to be optimized. It is to be noted that bringing the Source1 412 closer to edge of the gate 416 increases stresses on bottom nitride layer. For demonstration purpose offset D is maintained as 1 micron.
In one embodiment, an ATLAS (SILVACO) TCAD device simulator was used during validation exercise to demonstrate that objective of obtaining required ESD robustness while keeping the normal mode leakage current very low is achieved by the disclosed circuit.
In one embodiment, performance of the disclosed circuit 500 using MISIS TFT 400 was compared with that of a circuit with conventional TFT (Metal-Insulator-Semiconductor, MIS structure), both devices configured in gate-coupled mode in the respective circuits, under a 2 kV Human-Body-Model (HBM) signal stress. Both the devices had silicon nitride as gate insulator and poly-Si as semiconductor material. Both the devices had same effective oxide thickness (EOT) as 123.76 nm and same aspect ratio, W/L = 500 microns/ 7 microns. FIG. 12 shows the standard 2kV HBM setup with ESD protection device MISIS in the scan line; Cint is the internal capacitance (pixel TFT capacitance + Load capacitance).
In one embodiment, performance validation has shown that with similar dimensions and material properties along with the same configurations in the ESD protection circuit, the circuit 500 with MISIS TFT 400 can offer almost 106 times less leakage current at steady state due to screening effect that happens in the thin-semiconductor layer as compared to ESD protection circuit having conventional TFT and therefore can significantly reduce power consumption. Further, MISIS TFT 400 also offers a lot of room to increase width of the device to enhance ESD robustness without much worry about normal mode leakage current. Table below shows a comparison of Normal mode leakage current for MIS and MISIS structure:

TFT Normal mode leakage current @ Vgs=Vds=10V
MIS 2.98 mA
MISIS 3.74 nA

Table 1: Comparison of Normal mode leakage current for MIS and MISIS structure
FIG. 13 illustrates an exemplary graph showing ESD Drain current in respect of the two protection circuits that are based on conventional TFT device having MIS structure and MISIS structure respectively in accordance with embodiments of the present disclosure. As can be seen curve 1302 pertaining to ESD protection circuit based on conventional TFT device and curve 1304 pertaining to ESD protection circuit based on MISIS TFT follow almost same profile indicating similar ESD robustness.
FIG. 14 illustrates an exemplary graph showing maximum device temperature for conventional MIS structure (curve 1402) and the MISIS structure (curve 1404) in accordance with embodiments of the present disclosure.
FIG. 13 and FIG. 14 show that ESD current shunting capability and maximum device temperature developed inside the protection device during the ESD event are almost same for ESD circuits that are based on conventional MIS TFT device and the MISIS TFT device in accordance with the present disclosure. Maximum device temperature in both cases is well below melting point of poly-crystalline Si. Thus from thermal breakdown point of view, the disclosed protection circuit is robust to 2 kV HBM ESD stress.FIG. 15 illustrates an exemplary graph showing ESD voltage stress on gate-drain and ESD field stress inside dielectric in accordance with embodiments of the present disclosure. The ESD voltage stress on gate-drain in respect of ESD protection circuit using conventional MIS TFT device and MISIS TFT device is depicted by curves 1502 and 1504 respectively. While curves 1506 and 1508 show ESD field stress inside dielectric in respect of ESD protection circuit using conventional MIS TFT device and MISIS TFT device respectively. As can be seen, the curve 1508 represent a significantly high electric field stress inside insulator at the Source-Gate overlap region (for MISIS, it is the bottom nitride layer) during an ESD event, which is very close to the breakdown field of the nitride insulator. It also stresses the internal TFT at its gate node to a very high voltage, which is very severe because it can damage gate insulator of internal circuit. Because of advantage of very low normal mode leakage current in the proposed ESD protection scheme, width W of the device can be increased to reduce the stress without significantly increasing the normal mode leakage current.
In an embodiment, effect of width W of MISIS TFT was also examined during the validation experiment. FIG. 16 and FIG. 17 illustrate exemplary graphs showing effect of width of MISIS TFT device on maximum device temperature and ESD stress on gate/ drain respectively. In FIG. 16 plots 1602, 1604 and 1606 show temperature of the device against transient time for 1500, 1000 and 500 micron width of the device respectively. Likewise, plots 1702, 1704 and 1706 in FIG. 17 show ESD stress against transient time for 1500, 1000 and 500 micron width of the device respectively. As can be seen both maximum temperature and maximum ESD stress experienced by the device decreases with increasing width indicating improvement of ESD robustness in terms of reducing max device temperature and ESD stress as W increases. Thus it is possible to achieve a desired robustness of the protection device by selecting a suitable value for the width.
FIG. 18 illustrates an exemplary ESD protection circuit with MISIS TFT 400 in Gate-coupled configuration and with a resistor R2 between the MISIS TFT and internal TFT in accordance with an embodiment of the present disclosure. Shown herein is another way to protect the internal circuit TFT by using its low frequency operation property. In this case, a resistance R2 is introduced between the MISIS TFT device and internal circuit node in such way that “R2*Cint” time constant is larger than HBM signal time constant but smaller than internal circuit operation time period.
In one implementation, 1 M ohm resistance was introduced and from the simulations it was identified that drain voltage, current and device temperature remained almost the same but voltage stress across internal circuit capacitance reduced to a great extent. Also during the normal mode operation this will not create any problem as its RC time constant is 1 microsecond and the operating frequency of a typical pixel circuit is in the order of few hundred Hz. However, with the design as shown in FIG. 18, the internal circuit gets protected, but the MISIS TFT device still faces a high voltage stress and hence a high field stress in the bottom nitride layer. To protect the MISIS TFT device another resistor R1 can be incorporated between input pad and the MISIS device.
FIG. 19 illustrates a Gate-coupled ESD protection circuit with a resistor R2 between the MISIS TFT and the internal TFT and a resistor R1 between the input pad and the protection device in accordance with an embodiment of the present disclosure. The resistor R1 having typical value of ~ few k ohms, can have some voltage drop across it during an ESD event and hence the MISIS TFT of the protection circuit and the protected TFT device will experience less voltage stress. Again it is not going to disturb the normal mode low frequency operation as discussed earlier.
While protection circuit of FIG. 19 can protect scan lines in LAE from ESD, for the data lines the challenges are a little bit different. In data line under normal operating mode, channel resistance is in hundreds of ohms which restricts use of a high series resistance R1 as it can slow down pixel charging process. However, as the data line frequency is in hundreds of HZ a low resistance value (say ~ few k ohms) can be used to help reduce the stress across MISIS TFT to some extent. FIG. 20 illustrates scheme for ESD protection in data line in accordance with above embodiment. As in case of data lines the ESD stress does not appear across the gate insulator of the internal TFT, there is no need to use the second resistor R2 to reduce the voltage stress. This design can also be good for the data signal which has a higher frequency than the scan signal.
As is known in the art that, an ESD event has a time constant of t~ 0.5 ns – 500 ns and response of MISIS TFT shall be dependent on carrier mobility, density of localized states, channel length L and offset D between secondary source S1 412 and edge of gate 416. R2 should be chosen so that
?t_HBM<(R?_2*C_int)