Claims:1. An apparatus comprising:
a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a rising edge of the first clock;
a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a rising edge of a second clock; and
a circuitry coupled to the first and second flip-flops, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan enable is active.

2. The apparatus of claim 1, wherein the circuitry is to skew the first clock by substantially 180 degrees.

3. The apparatus of claim 1, wherein the rising edge of the second clock substantially aligns with a falling edge of the first clock.

4. The apparatus of claim 1, wherein the circuitry comprises:
a multiplexer to select one of the first clock or a skewed version of the first clock;
a sequential circuit to receive the first clock and the scan enable via an OR gate, wherein the sequential circuit is to provide a sampled output; and
an AND gate coupled to an input of the multiplexer, wherein the AND gate is controllable by the first clock and the sampled output.

5. The apparatus of claim 4, wherein the OR gate is to receive the scan enable and a scan capture enable.

6. The apparatus of claim 5, wherein an output of the OR gate is received by the sequential circuit to clear the sampled output.

7. The apparatus of claim 5, wherein the AND gate is a first AND gate, and wherein the circuitry comprises a second AND gate to generate a control for the multiplexer, wherein the second AND gate is to receive the output of the OR gate and a skew circuit enable.

8. The apparatus of claim 7, wherein the skew circuit enable is to enable or disable the circuitry.

9. A system comprising:
a memory;
a processor coupled to the memory; and
a wireless interface to allow the processor to communicate with another device, wherein the processor includes a scan chain which is partitioned into at least a first partition and a second partition,
wherein the first partition includes a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a first edge of the first clock,
wherein the second partition includes a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a second edge of a second clock, and
wherein the processor includes a circuitry coupled to the first and second flip-flops, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan enable is active.

10. The system of claim 9 comprises an input to receive a test pattern for the scan chain.

11. The system of claim 9, wherein the circuitry is to skew the first clock by substantially 180 degrees.

12. The system of claim 9, wherein the second edge of the second clock substantially aligns with the first edge of the first clock, wherein second edge is phase shifted relative to the first edge by substantially 180 degrees.

13. The system of claim 9, wherein the circuitry is operable to provide the first clock as output when the circuitry is disabled.

14. The system of claim 9, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when scan capture is enabled.

15. A machine-readable storage media having machine-readable instructions that when executed cause one or more processors to perform a method comprising:
identifying a portion of a chip having higher temperature or power consumption compared to another portion of the chip;
dividing the portion into a first partition and a second partition;
adding a clock skew circuit to the first partition and the second partition;
operating a first scan chain of the first partition using a positive edge of a first clock;
skewing the first clock by the clock skew circuit to generate a second clock which is skewed version of the first clock; and
operating a second scan chain of the second partition using an edge of the second clock.

16. The machine-readable storage media of claim 15 having machine-readable instructions that when executed cause the one or more processors to perform the method comprising:
determining power for the first partition and the second partition.

17. The machine-readable storage media of claim 16, wherein the portion is a first portion, wherein machine-readable storage media has machine-readable instructions that when executed cause the one or more processors to perform the method comprising:
comparing the power against a threshold, and performing, if the power is greater than the threshold, operations comprising:
dividing the second portion into a first partition and a second partition;
adding a second clock skew circuit to the first partition and the second partition of the second portion;
operating a first scan chain of the second partition using a positive edge of the first clock;
skewing the first clock by the second clock skew circuit to generate a third clock which is skewed version of the first clock; and
operating the second scan chain of the second partition using an edge of the third clock.

18. The machine-readable storage media of claim 17 having machine-readable instructions that when executed cause the one or more processors to perform the method comprising: performing layout of the first and second partitions of the first portion and the second portion if the power is less than the threshold.

19. The machine-readable storage media of claim 16, wherein the clock skew circuit is to skew the first clock by substantially 180 degrees.

20. The machine-readable storage media of claim 15, wherein a rising edge of the second clock substantially aligns with a falling edge of the first clock.
, Description:BACKGROUND
[0001] Scan chains are typically used for testing of an integrated chip such as a processor. Scan test patterns generated by automatic test pattern generation (ATPG) tools cause high switching activity (signal toggle ratio) in the processor compared to functional mode of the processor. The processor may undesirably exceed its maximum limit of power budget (either average or instantaneous) when the test pattern is executed on the processor, resulting in false failures or yield loss during manufacturing test.
[0002] Excessive electric power dissipation during scan test can result in excessive voltage variations, reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure. Invalid tests result in yield loss during manufacturing/production testing causing revenue loss. This also impacts test quality resulting in high Defective Parts Per Million (DPPM) count and customer returns impacting goodwill with customers. Issues caused due to high peak power are generally not visible in simulation and are challenging to model, thus they go through prolonged debug cycle during post-silicon validation phase.

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0004] Fig. 1 illustrates two scan chains that toggle using a same scan clock, resulting in high instantaneous and average power consumption when enabled.
[0005] Fig. 2 illustrates a plot showing high instantaneous and average power consumption upon rising edge of the scan clock.
[0006] Fig. 3 illustrates two scan chains that toggle using different scan clocks using a clock skew circuit, resulting in lower instantaneous and average power consumption when enabled, in accordance with some embodiments.
[0007] Fig. 4 illustrates a plot showing lower instantaneous and average power consumption compared to the plot of Fig. 2, in accordance with some embodiments.
[0008] Fig. 5 illustrates a pin diagram of the clock skew circuit, in accordance with some embodiments.
[0009] Fig. 6 illustrates a schematic of the clock skew circuit, in accordance with some embodiments.
[0010] Fig. 7 illustrates a flowchart of a method of inserting clock skew circuits in the scan clock network for the scan chains, in accordance with some embodiments.
[0011] Fig. 8 illustrates a processor with partitioned scan chains to lower instantaneous and average power consumption, in accordance with some embodiments.
[0012] Fig. 9 illustrates a simplified computer system for executing the flowchart of Fig. 7, in accordance with some embodiments.
[0013] Fig. 10 illustrates a smart device or a computer system or an SoC (System-on-Chip) with low power scan apparatus of various embodiments.

DETAILED DESCRIPTION
[0014] Fig. 1 illustrates an apparatus 100 having two scan chains (1011, 1012, 1013, and 1014) that toggle using a same scan clock, resulting in high instantaneous and average power consumption when enabled. Here, the first scan chain comprises scan cell 1 1011, and scan cell 2 1012 coupled via combinational logic (C.L.) 1021. The second scan chain comprises scan cell 3 1013, and scan cell 4 1014 coupled via C.L. 1022. Each scan cell includes an edge triggered latch or flip-flop, and receives input data (D), scan input Si, clock (Clk), and scan enable (SE), and provides at least one output Q. A person skilled in the art would appreciate that a scan cell may include a multiplexer to select between the regular data path or the scan input path. The output of the first scan chain is Scan Output 1. The output of the second scan chain is Scan Output 2.
[0015] The inputs to Scan Cell 1 1011 are Functional Input 1 (received by data pin D), Scan Input 1 (received by scan input pin Si), Scan Clock (received by clock pin Clk), and Scan Enable (received by enable input SE). The inputs to Scan Cell 2 1012 are output of C.L. 1021 (received by data pin D), output of Scan Cell 1 (received by scan input pin Si), Scan Clock (received by clock pin Clk), and Scan Enable (received by enable input SE). The inputs to Scan Cell 3 1013 are Functional Input 2 (received by data pin D), Scan Input 2 (received by scan input pin Si), Scan Clock (received by clock pin Clk), and Scan Enable (received by enable input SE). The inputs to Scan Cell 4 1014 are output of C.L. 1022 (received by data pin D), output of Scan Cell 3 (received by scan input pin Si), Scan Clock (received by clock pin Clk), and Scan Enable (received by enable input SE). Here, node/pin names and signal names are interchangeably used. For example, Si may refer to pin/node or scan input signal depending on the context of the sentence.
[0016] Fig. 2 illustrates plot 200 showing high instantaneous and average power consumption upon rising edge of the scan clock. Upon enabling the Scan Enable, whenever Scan Clock is pulsed, all the four flip-flops 1011-4 toggle and combinational logic 1021 and 1022 between the flip-flops also toggles. First shaded region 201 shows dynamic power of sequential logic (scan flops 1011-4) while second shaded region 202 shows dynamic power of combinational logic 1021-2. For rising edge-based scan flops, the dynamic power is higher at the rising edge of Scan Clock than the falling edge of the Scan Clock. Plot 200 shows maximum power limit Pmax for a processor. During scan mode, the dynamic power from the scan flops may cross the Pmax. In this example, the power is P1 upon rising edge of Scan Clock.
[0017] In some embodiments, apparatus is provided that uses both clock edges of Scan Clock during scan shift phase (e.g., for different the scan flops 1011-4). In that case, the Scan Clock I used to toggle different parts of the design (e.g., different scan chains) at different intervals of time. This brings down the dynamic power consumption drastically reducing the peak power of the chip. In one example, in scan-shift mode, the same clock reaches all the flip-flops in the design and Scan Enable bit for all the flip-flops is set to ‘1’, so the value at Scan Input (Si pin) is stored in the flip-flop. Some embodiments describe a methodology to insert clock skew circuits that enable scan data propagation using clock edges of Scan Clock during scan shift phase. The methodology minimizes peak power dissipation during scan operation. The methodology and apparatus can be used for minimizing peak/instantaneous power during scan shift and scan capture or either of them independently (e.g., via register programmability).
[0018] In some embodiments, an apparatus is provided which comprises: a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a rising edge of the first clock; and a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a rising edge of a second clock. The apparatus further comprises a circuitry coupled to the first and second flip-flops, wherein the circuitry receives the first clock and skew the first clock to generate the second clock when the scan enable is active. In some embodiments, the circuitry skews the first clock by substantially 180 degrees. In some embodiments, the rising edge of the second clock substantially aligns with a falling edge of the first clock. In some embodiments, the circuitry comprises: a multiplexer to select one of the first clock or a skewed version of the first clock; a sequential circuit to receive the first clock and the scan enable via an OR gate, wherein the sequential circuit provides a sampled output; and an AND gate coupled to an input of the multiplexer, wherein the AND gate is controllable by the first clock and the sampled output. In some embodiments, the OR gate receives the scan enable and a scan capture enable. In some embodiments, an output of the OR gate is received by the sequential circuit to clear the sampled output. In some embodiments, the AND gate is a first AND gate, and wherein the circuitry comprises a second AND gate to generate a control for the multiplexer, wherein the second AND gate receives the output of the OR gate and a skew circuit enable. In some embodiments, the skew circuit enable is to enable or disable the circuitry.
[0019] There are several technical effects of various embodiments. For example, the approach of various embodiments can help to reduce peak power close to 50% during scan operations. The methodology is transparent to existing design-for-test (DFT) electronic design automation (EDA) tools and works seamlessly with existing flows irrespective of the vendors such as Mentor Graphics®, Synopsys®, Cadence®, Siemens®. For example, the same set of test vectors can be applied with or without the addition of the clock skew circuit. As such, the methodology and apparatus of various embodiments improves quality of results (QoR) in terms of peak power profile agnostic to any EDA vendor used, resulting in yield improvement. In one example, the methodology and apparatus reduce peak scan power by 50%, and has direct impact on preserving reliability in wafer test floor. Other technical effects are evident from the various figures and embodiments.
[0020] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.
[0021] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.
[0022] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.
[0023] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
[0024] The term “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).
[0025] The term "circuit" or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.
[0026] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."
[0027] The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and may be subsequently being reduced in layout area. In some cases, scaling also refers to upsizing a design from one process technology to another process technology and may be subsequently increasing layout area. The term “scaling” generally also refers to downsizing or upsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up – i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/- 10% of a target value.
[0028] Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
[0029] For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0030] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.
[0031] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described but are not limited to such.
[0032] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.
[0033] Fig. 3 illustrates apparatus 300 showing two scan chains that toggle using different scan clocks using a clock skew circuit, resulting in lower instantaneous and average power consumption when enabled, in accordance with some embodiments. Compared to apparatus 100, here clock skew circuit 301 is added to separate the scan clocks for the two sets of scan chains. Clock-skew circuit 301 is used at sub-partition level to control positive and negative clock edges of the scan clock. Using both clock edges during scan shift phase (for different scan flops) toggle different parts of the design at different intervals of time. This brings down the dynamic power consumption drastically reducing the peak power of the chip.
[0034] Fig. 4 illustrates plot 400 showing lower instantaneous and average power consumption compared to the plot of Fig. 2, in accordance with some embodiments. Peak power (when clock toggles from 0 to 1) = power of flip-flops (1011 and 1012) plus power of the C.L. 1021. Peak power (when clock toggles from 1 to 0) = power of flip-flops (1013 and 1014) plus power of the C.L. 1022. Table 1 summarizes the impact of test time and quality of existing methodologies compared with the embodiments.
Table 1
Methodology Type Test Coverage Test Time Test Quality

Low Power ATPG patterns Up to 10% coverage loss observed for low power ATPG patterns We will not be able to achieve peak coverage. Up to 2x-3x increase due to large number of low power ATPG patterns Quality worsens due to coverage drop.

Scan Shift Frequency Reduction

NA Up to 3x-4x increase depending on magnitude of reduction across different PTV (process, temperature, voltage) conditions. Increase in test time results in higher test cost leading to profit/revenue (dollar) loss to Intel.

Masking failing flops/Region
Yes, depending on magnitude of masking needed. Need to deploy additional tests during manufacturing to recover coverage drop. May not recover all coverage loss across various fault types.
ATPG Patterns on Higher Voltage during production test
NA
NA Severe impact on quality as there will be test escapes causing DPPM (defective parts per million) hit.
Embodiment of Fig. 3 No test coverage loss No test time increase No impact on test quality

[0035] Compared to plot 200, power from toggling flip-flops 1011-4 is reduced by 50%, which assists in reducing associated combo logic toggles. In this example, dynamic power from flip-flops 1011-4 is illustrated by pattern 401 and dynamic power in C.L 1021-2 is illustrated by pattern 402. Clearly, peak power (P2) from both patterns (or first and second shaded regions) 401 and 402 are lower than peak power (P1) from patterns (or first and second shaded regions) 201 and 202.
[0036] Fig. 5 illustrates pin diagram 500 of clock skew circuit 301, in accordance with some embodiments. Pin diagram 500 shows the basic inputs and output of clock skew circuit 301. This pin diagram can be used as interface in hardware translation language (RTL) and in actual schematics. The main inputs include Scan Clock and Scan Enable while Skewed Scan Clock is the output. Other enable signals can be used for more programmability. In this example, the other inputs are input clock skew circuit enable (CLOCK_SKEW_CIRCUIT_ENABLE) and skew during capture enable (SKEW_DURING_CAPTURE_ENABLE).
[0037] Fig. 6 illustrates schematic 600 of the clock skew circuit 301, in accordance with some embodiments. Clock skew circuit 301 comprises OR gate 601, non-scan sequential logic (e.g., flip-flop) 602, inverter 603, AND gates 604 and 605, and multiplexer 606 coupled as shown. A person skilled in the art would appreciate that OR and AND gates can be replaced using other logic gates such as a NOR and NAND gates by applying De Morgan Theorem. When Clock_Skew_Circuit_enable is 0, circuit 301 is disabled and scan clock is passed through multiplexer 606 as the skewed scan clock. When Clock_Skew_Circuit_enable is 1, then output of AND gate 604 is used to provide as output to node skewed scan clock. The output of AND gate 604 depends on the polarity of scan clock and output of non-scan flip-flop 602. In some embodiments, non-scan flip-flop 602 has the effect of skewing the Scan clock so that skewed scan clock is phase shifted (e.g., by 180 degrees) from scan clock. As such, one partition or scan chain set toggles upon rising edge of Scan Clock while the other partition or scan chain set toggles upon falling edge of Scan Clock.
[0038] Table 2 illustrates the truth table of the clock skew circuit 600 or 301.
Table 2
clock_skew_circuit_enable skew_during_capture_enable Scan Enable Skewed Scan Clock (output) Comments
0 X X No Skew Circuit Disabled
1 0 1 Skewed Skew enabled during ATPG shift
1 0 0 No skew Skew disabled during ATPG capture
1 1 X Skewed Skew enabled during both ATPG Shift/Capture

[0039] Fig. 7 illustrates flowchart 700 of a method of inserting clock skew circuits in the scan clock network for the scan chains, in accordance with some embodiments. While the blocks are shown in a particular order, the order can be modified. For example, some blocks can be performed in parallel to other blocks. The process can be performed by software and/or hardware. In some embodiments, the process is performed by an EDA tool which intelligently inserts clock skew circuits 301 at various clock nodes in a clock distribution network. The process described here may be an iterative process that continues until power level is reduced below a maximum power threshold for a chip.
[0040] At block 701, an area or floor plan of a chip is selected and partitioned. This area may be a hot spot area, for example, where dynamic power of the chip is higher than a threshold. The area is partitioned into two sub-partitions based on a power criterion. For instance, a power virus is run on the chip and hot areas are identified. The hot areas are areas that consume power more than the specified maximum power Pmax. In some embodiments, hot spot areas include areas where traditional scan chains (e.g., as shown in Fig. 1) consume high dynamic power because the scan chain flip-flops toggle together on the same scan clock. Fig. 8 illustrates a processor 800 with partitioned scan chains to lower instantaneous and average power consumption, in accordance with some embodiments. For the sake of simplicity, components of processor 800 are not shown. Here, region 801 is the core and uncore logic region which is analyzed for placement of clock skew circuits 301. In this example, the floor plan of the chip is marked with hot spot regions and partitioned in the areas for skewed sequential 802 (e.g., flip-flops that receive skewed clock output of clock skew circuits 301) and unskewed sequential 803 (e.g., flip-flops that do not receive the skewed output from clock output of clock skew circuits 301).
[0041] Referring back to Fig. 7, at block 702, clock skew circuits 301 are added to the divided partitions. For instance, both the two sub-partitions are provided clock skew circuits 301 for their respective scan clock nodes. The clock skew circuits 301 are stitched with other nodes as shown in Figs. 5-6. For example, Scan Enable, Skew_During_Capture_enable, and Clock_Skew_Circuit_enable. If these signals are not available, they are routed to the locations of clock skew circuits 301.
[0042] At block 703, the clock skew circuit 301 is enabled for one of the two sub-partitions. This is done to analyze the cost and benefit of clock skew circuit 301. At block 704, scan chain is built (if not already there) for both sub-partitions such that one of the sub-partition shifts data on a positive edge of the scan clock (e.g., by passing the clock skew circuit 301 or as shown in Fig. 3) while the other sub-partition shifts the data on negative edge of the clock skew circuit. For example, with reference to Fig. 3, scan cells 1011, 1012, and C.L 1021 are part of one sub-partition and scan cells 1013, 1014, and C.L 1022 are part of a second sub-partition, and where scan cells 1011, 1012 operate on rising edge of the scan clock while scan cells 1013, 1014 operate using skew circuit clock from clock skew circuit 301. In various embodiments, lockup latch is inserted wherever the scan chain crosses a clock domain. For example, when the scan chain passes from one sub-partition to another sub-partition, a lockup latch is placed between the sub-partitions to avoid hold timing violations.
[0043] At block 705, the power virus is run again on the processor and the scan shift power is determined for both sub-partitions. At block 706, a determination is made about the power level relative to a threshold (e.g., Pmax). If the power from a sub-partition is higher than Pmax, then the process proceeds to block 701 where the abstraction level of the partition is refined and the sub-partition is further sub-divided into two sub-partitions and the process proceeds again. As such, more clock skew circuits 301 are added till power level falls below the Pmax threshold. Once power falls below the Pmax threshold, the process proceeds with layout of the scan chain in the various sub-partitions as indicated by block 707.
[0044] Fig. 9 illustrates a simplified computer system 900 for executing the flowchart of Fig. 7, in accordance with some embodiments. Elements of embodiments are also provided as a machine-readable medium (e.g., memory) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein) also referred to as machine-executable instructions. In some embodiments, the computing platform 900 comprises memory 901, processor 902, machine-readable storage media 903 (also referred to as tangible machine readable medium), communication interface 904 (e.g., wireless or wired interface), and network bus 905 coupled together as shown.
[0045] In some embodiments, processor 902 is a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a general-purpose Central Processing Unit (CPU), or a low power logic implementing a simple finite state machine to perform the method of various embodiments, etc.
[0046] In some embodiments, the various logic blocks of the system are coupled together via network bus 905. Any suitable protocol may be used to implement network bus 905. In some embodiments, machine-readable storage medium 903 includes Instructions (also referred to as the program software code/instructions) for calculating or measuring distance and relative orientation of a device with reference to another device as described with reference to various embodiments and flowchart.
[0047] Program software code/instructions associated with the methods and executed to implement embodiments of the disclosed subject matter may be implemented as part of an operating system or a specific application, component, program, object, module, routine, or other sequence of instructions or organization of sequences of instructions referred to as "program software code/instructions," "operating system program software code/instructions," "application program software code/instructions," or simply "software" or firmware embedded in processor. In some embodiments, the program software code/instructions associated with various embodiments are executed by the computing system.
[0048] In some embodiments, the program software code/instructions associated with various flowcharts are stored in a computer executable storage medium and executed by processor 902. Here, computer executable storage medium 903 is a tangible machine-readable medium that can be used to store program software code/instructions and data that, when executed by a computing device, causes one or more processors (e.g., processor 902) to perform a method(s) as may be recited in one or more accompanying claims directed to the disclosed subject matter.
[0049] In some embodiments, the program software code/instructions when executed cause one or more processors (e.g., processor 902) to perform a method comprising: identifying a portion of a chip having higher temperature or power consumption compared to another portion of the chip. This portion can be a hot spot. The method further comprises dividing the portion into a first partition and a second partition. The first and second partitions can operate on different clocks thereby reducing overall power. The method further comprises adding a clock skew circuit to the first partition and the second partition; operating a first scan chain of the first partition using a positive edge of a first clock. The method further comprises skewing the first clock by the clock skew circuit to generate a second clock which is skewed version of the first clock; and operating a second scan chain of the second partition using an edge of the second clock.
[0050] In some embodiments, the method comprises determining power for the first partition and the second partition. The method further comprises comparing the power relative to a threshold, wherein the portion is a first portion, and performing the following if the power is greater than the threshold: dividing the second portion into a first partition and a second partition; adding a second clock skew circuit to the first partition and the second partition of the second portion; operating a first scan chain of the second partition using a positive edge of the first clock; skewing the first clock by the second clock skew circuit to generate a third clock which is skewed version of the first clock; and operating the second scan chain of the second partition using an edge of the third clock. In some embodiments, the method comprises performing layout of the first and second partitions of the first portion and the second portion if the power is less than the threshold. In some embodiments, the clock skew circuit is to skew the first clock by substantially 180 degrees. In some embodiments, the rising edge of the second clock substantially aligns with a falling edge of the first clock.
[0051] Tangible machine-readable medium 903 may include storage of the executable software program code/instructions and data in various tangible locations, including for example ROM, volatile RAM, non-volatile memory and/or cache and/or other tangible memory as referenced in the present application. Portions of this program software code/instructions and/or data may be stored in any one of these storage and memory devices. Further, the program software code/instructions can be obtained from other storage, including, e.g., through centralized servers or peer-to-peer networks and the like, including the Internet. Different portions of the software program code/instructions and data can be obtained at different times and in different communication sessions or in the same communication session.
[0052] The software program code/instructions and data can be obtained in their entirety prior to the execution of a respective software program or application by the computing device. Alternatively, portions of the software program code/instructions and data can be obtained dynamically, e.g., just in time, when needed for execution. Alternatively, some combination of these ways of obtaining the software program code/instructions and data may occur, e.g., for different applications, components, programs, objects, modules, routines or other sequences of instructions or organization of sequences of instructions, by way of example. Thus, it is not required that the data and instructions be on a tangible machine-readable medium in entirety at a particular instance of time.
[0053] Examples of tangible computer-readable media 903 include but are not limited to recordable and non-recordable type media such as volatile and non-volatile memory devices, read only memory (ROM), random access memory (RAM), flash memory devices, floppy and other removable disks, magnetic storage media, optical storage media (e.g., Compact Disk Read-Only Memory (CD ROMS), Digital Versatile Disks (DVDs), etc.), among others. The software program code/instructions may be temporarily stored in digital tangible communication links while implementing electrical, optical, acoustical or other forms of propagating signals, such as carrier waves, infrared signals, digital signals, etc. through such tangible communication links.
[0054] In general, tangible machine readable medium 903 includes any tangible mechanism that provides (i.e., stores and/or transmits in digital form, e.g., data packets) information in a form accessible by a machine (i.e., a computing device), which may be included, e.g., in a communication device, a computing device, a network device, a personal digital assistant, a manufacturing tool, a mobile communication device, whether or not it is able to download and run applications and subsidized applications from the communication network, such as the Internet, e.g., an iPhone®, Galaxy®, Blackberry® Droid®, or the like, or any other device including a computing device. In one embodiment, processor-based system is in a form of or included within a PDA (personal digital assistant), a cellular phone, a notebook computer, a tablet, a game console, a set top box, an embedded system, a TV (television), a personal desktop computer, etc. Alternatively, the traditional communication applications and subsidized application(s) may be used in some embodiments of the disclosed subject matter.
[0055] Fig. 10 illustrates a smart device or a computer system or an SoC (System-on-Chip) with low power scan apparatus of various embodiments. In some embodiments, device 2400 represents an appropriate computing device, such as a computing tablet, a mobile phone or smart-phone, a laptop, a desktop, an Internet-of-Things (IOT) device, a server, a wearable device, a set-top box, a wireless-enabled e-reader, or the like. It will be understood that certain components are shown generally, and not all components of such a device are shown in device 2400. Any component of device 2400 can include the low power scan apparatus of various embodiments.
[0056] In an example, the device 2400 comprises an SoC (System-on-Chip) 2401. An example boundary of the SoC 2401 is illustrated using dotted lines in Fig. 10, with some example components being illustrated to be included within SoC 2401 – however, SoC 2401 may include any appropriate components of device 2400. In some embodiments, the processor or SoC 2401 includes a scan chain which is partitioned in to at least a first partition and a second partition, wherein the first partition includes a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a first edge of the first clock. In some embodiments, the second partition includes a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a second edge of a second clock. In some embodiments, the processor includes a circuitry coupled to the first and second flip-flops, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan enable is active. In some embodiments, SoC 2401 includes an input (e.g., a pin) to receive a test pattern for the scan chain. In some embodiments, the circuitry is to skew the first clock by substantially 180 degrees. In some embodiments, the second edge of the second clock substantially aligns with the first edge of the first clock, wherein second edge is phase shifted relative to the first edge by substantially 180 degrees. In some embodiments, the circuitry is operable to provide the first clock as output when the circuitry is disabled. In some embodiments, the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan capture is enabled.
[0057] In some embodiments, device 2400 includes processor 2404. Processor 2404 can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, processing cores, or other processing means. The processing operations performed by processor 2404 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, operations related to connecting computing device 2400 to another device, and/or the like. The processing operations may also include operations related to audio I/O and/or display I/O.
[0058] In some embodiments, processor 2404 includes multiple processing cores (also referred to as cores) 2408a, 2408b, 2408c. Although merely three cores 2408a, 2408b, 2408c are illustrated in Fig. 10, processor 2404 may include any other appropriate number of processing cores, e.g., tens, or even hundreds of processing cores. Processor cores 2408a, 2408b, 2408c may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches, buses or interconnections, graphics and/or memory controllers, or other components.
[0059] In some embodiments, processor 2404 includes cache 2406. In an example, sections of cache 2406 may be dedicated to individual cores 2408 (e.g., a first section of cache 2406 dedicated to core 2408a, a second section of cache 2406 dedicated to core 2408b, and so on). In an example, one or more sections of cache 2406 may be shared among two or more of cores 2408. Cache 2406 may be split in different levels, e.g., level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache, etc.
[0060] In some embodiments, processor core 2404 may include a fetch unit to fetch instructions (including instructions with conditional branches) for execution by the core 2404. The instructions may be fetched from any storage devices such as the memory 2430. Processor core 2404 may also include a decode unit to decode the fetched instruction. For example, the decode unit may decode the fetched instruction into a plurality of micro-operations. Processor core 2404 may include a schedule unit to perform various operations associated with storing decoded instructions. For example, the schedule unit may hold data from the decode unit until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit may schedule and/or issue (or dispatch) decoded instructions to an execution unit for execution.
[0061] The execution unit may execute the dispatched instructions after they are decoded (e.g., by the decode unit) and dispatched (e.g., by the schedule unit). In an embodiment, the execution unit may include more than one execution unit (such as an imaging computational unit, a graphics computational unit, a general-purpose computational unit, etc.). The execution unit may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit.
[0062] Further, execution unit may execute instructions out-of-order. Hence, processor core 2404 may be an out-of-order processor core in one embodiment. Processor core 2404 may also include a retirement unit. The retirement unit may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc. Processor core 2404 may also include a bus unit to enable communication between components of processor core 2404 and other components via one or more buses. Processor core 2404 may also include one or more registers to store data accessed by various components of the core 2404 (such as values related to assigned app priorities and/or sub-system states (modes) association.
[0063] In some embodiments, device 2400 comprises connectivity circuitries 2431. For example, connectivity circuitries 2431 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and/or software components (e.g., drivers, protocol stacks), e.g., to enable device 2400 to communicate with external devices. Device 2400 may be separate from the external devices, such as other computing devices, wireless access points or base stations, etc.
[0064] In an example, connectivity circuitries 2431 may include multiple different types of connectivity. To generalize, the connectivity circuitries 2431 may include cellular connectivity circuitries, wireless connectivity circuitries, etc. Cellular connectivity circuitries of connectivity circuitries 2431 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, 3rd Generation Partnership Project (3GPP) Universal Mobile Telecommunications Systems (UMTS) system or variations or derivatives, 3GPP Long-Term Evolution (LTE) system or variations or derivatives, 3GPP LTE-Advanced (LTE-A) system or variations or derivatives, Fifth Generation (5G) wireless system or variations or derivatives, 5G mobile networks system or variations or derivatives, 5G New Radio (NR) system or variations or derivatives, or other cellular service standards. Wireless connectivity circuitries (or wireless interface) of the connectivity circuitries 2431 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), and/or other wireless communication. In an example, connectivity circuitries 2431 may include a network interface, such as a wired or wireless interface, e.g., so that a system embodiment may be incorporated into a wireless device, for example, a cell phone or personal digital assistant.
[0065] In some embodiments, device 2400 comprises control hub 2432, which represents hardware devices and/or software components related to interaction with one or more I/O devices. For example, processor 2404 may communicate with one or more of display 2422, one or more peripheral devices 2424, storage devices 2428, one or more other external devices 2429, etc., via control hub 2432. Control hub 2432 may be a chipset, a Platform Control Hub (PCH), and/or the like.
[0066] For example, control hub 2432 illustrates one or more connection points for additional devices that connect to device 2400, e.g., through which a user might interact with the system. For example, devices (e.g., devices 2429) that can be attached to device 2400 include microphone devices, speaker or stereo systems, audio devices, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.
[0067] As mentioned above, control hub 2432 can interact with audio devices, display 2422, etc. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of device 2400. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display 2422 includes a touch screen, display 2422 also acts as an input device, which can be at least partially managed by control hub 2432. There can also be additional buttons or switches on computing device 2400 to provide I/O functions managed by control hub 2432. In one embodiment, control hub 2432 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in device 2400. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).
[0068] In some embodiments, control hub 2432 may couple to various devices using any appropriate communication protocol, e.g., PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), Thunderbolt, High Definition Multimedia Interface (HDMI), Firewire, etc.
[0069] In some embodiments, display 2422 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with device 2400. Display 2422 may include a display interface, a display screen, and/or hardware device used to provide a display to a user. In some embodiments, display 2422 includes a touch screen (or touch pad) device that provides both output and input to a user. In an example, display 2422 may communicate directly with the processor 2404. Display 2422 can be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment display 2422 can be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.
[0070] In some embodiments, and although not illustrated in the figure, in addition to (or instead of) processor 2404, device 2400 may include Graphics Processing Unit (GPU) comprising one or more graphics processing cores, which may control one or more aspects of displaying contents on display 2422.
[0071] Control hub 2432 (or platform controller hub) may include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections, e.g., to peripheral devices 2424.
[0072] It will be understood that device 2400 could both be a peripheral device to other computing devices, as well as have peripheral devices connected to it. Device 2400 may have a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device 2400. Additionally, a docking connector can allow device 2400 to connect to certain peripherals that allow computing device 2400 to control content output, for example, to audiovisual or other systems.
[0073] In addition to a proprietary docking connector or other proprietary connection hardware, device 2400 can make peripheral connections via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.
[0074] In some embodiments, connectivity circuitries 2431 may be coupled to control hub 2432, e.g., in addition to, or instead of, being coupled directly to the processor 2404. In some embodiments, display 2422 may be coupled to control hub 2432, e.g., in addition to, or instead of, being coupled directly to processor 2404.
[0075] In some embodiments, device 2400 comprises memory 2430 coupled to processor 2404 via memory interface 2434. Memory 2430 includes memory devices for storing information in device 2400.
[0076] In some embodiments, memory 2430 includes apparatus to maintain stable clocking as described with reference to various embodiments. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory device 2430 can be a dynamic random-access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, memory 2430 can operate as system memory for device 2400, to store data and instructions for use when the one or more processors 2404 executes an application or process. Memory 2430 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of device 2400.
[0077] Elements of various embodiments and examples are also provided as a machine-readable medium (e.g., memory 2430) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 2430) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).
[0078] In some embodiments, device 2400 comprises temperature measurement circuitries 2440, e.g., for measuring temperature of various components of device 2400. In an example, temperature measurement circuitries 2440 may be embedded, or coupled or attached to various components, whose temperature are to be measured and monitored. For example, temperature measurement circuitries 2440 may measure temperature of (or within) one or more of cores 2408a, 2408b, 2408c, voltage regulator 2414, memory 2430, a mother-board of SOC 2401, and/or any appropriate component of device 2400.
[0079] In some embodiments, device 2400 comprises power measurement circuitries 2442, e.g., for measuring power consumed by one or more components of the device 2400. In an example, in addition to, or instead of, measuring power, the power measurement circuitries 2442 may measure voltage and/or current. In an example, the power measurement circuitries 2442 may be embedded, or coupled or attached to various components, whose power, voltage, and/or current consumption are to be measured and monitored. For example, power measurement circuitries 2442 may measure power, current and/or voltage supplied by one or more voltage regulators 2414, power supplied to SOC 2401, power supplied to device 2400, power consumed by processor 2404 (or any other component) of device 2400, etc.
[0080] In some embodiments, device 2400 comprises one or more voltage regulator circuitries, generally referred to as voltage regulator (VR) 2414. VR 2414 generates signals at appropriate voltage levels, which may be supplied to operate any appropriate components of the device 2400. Merely as an example, VR 2414 is illustrated to be supplying signals to processor 2404 of device 2400. In some embodiments, VR 2414 receives one or more Voltage Identification (VID) signals, and generates the voltage signal at an appropriate level, based on the VID signals. Various type of VRs may be utilized for the VR 2414. For example, VR 2414 may include a “buck” VR, “boost” VR, a combination of buck and boost VRs, low dropout (LDO) regulators, switching DC-DC regulators, constant-on-time controller based DC-DC regulator, etc. Buck VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is smaller than unity. Boost VR is generally used in power delivery applications in which an input voltage needs to be transformed to an output voltage in a ratio that is larger than unity. In some embodiments, each processor core has its own VR, which is controlled by PCU 2410a/b and/or PMIC 2412. In some embodiments, each core has a network of distributed LDOs to provide efficient control for power management. The LDOs can be digital, analog, or a combination of digital or analog LDOs. In some embodiments, VR 2414 includes current tracking apparatus to measure current through power supply rail(s).
[0081] In some embodiments, device 2400 comprises one or more clock generator circuitries, generally referred to as clock generator 2416. Clock generator 2416 generates clock signals at appropriate frequency levels, which may be supplied to any appropriate components of device 2400. Merely as an example, clock generator 2416 is illustrated to be supplying clock signals to processor 2404 of device 2400. In some embodiments, clock generator 2416 receives one or more Frequency Identification (FID) signals, and generates the clock signals at an appropriate frequency, based on the FID signals.
[0082] In some embodiments, device 2400 comprises battery 2418 supplying power to various components of device 2400. Merely as an example, battery 2418 is illustrated to be supplying power to processor 2404. Although not illustrated in the figures, device 2400 may comprise a charging circuitry, e.g., to recharge the battery, based on Alternating Current (AC) power supply received from an AC adapter.
[0083] In some embodiments, device 2400 comprises Power Control Unit (PCU) 2410 (also referred to as Power Management Unit (PMU), Power Controller, etc.). In an example, some sections of PCU 2410 may be implemented by one or more processing cores 2408, and these sections of PCU 2410 are symbolically illustrated using a dotted box and labelled PCU 2410a. In an example, some other sections of PCU 2410 may be implemented outside the processing cores 2408, and these sections of PCU 2410 are symbolically illustrated using a dotted box and labelled as PCU 2410b. PCU 2410 may implement various power management operations for device 2400. PCU 2410 may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device 2400.
[0084] In some embodiments, device 2400 comprises Power Management Integrated Circuit (PMIC) 2412, e.g., to implement various power management operations for device 2400. In some embodiments, PMIC 2412 is a Reconfigurable Power Management ICs (RPMICs) and/or an IMVP (Intel® Mobile Voltage Positioning). In an example, the PMIC is within an IC chip separate from processor 2404. The may implement various power management operations for device 2400. PMIC 2412 may include hardware interfaces, hardware circuitries, connectors, registers, etc., as well as software components (e.g., drivers, protocol stacks), to implement various power management operations for device 2400.
[0085] In an example, device 2400 comprises one or both PCU 2410 or PMIC 2412. In an example, any one of PCU 2410 or PMIC 2412 may be absent in device 2400, and hence, these components are illustrated using dotted lines.
[0086] Various power management operations of device 2400 may be performed by PCU 2410, by PMIC 2412, or by a combination of PCU 2410 and PMIC 2412. For example, PCU 2410 and/or PMIC 2412 may select a power state (e.g., P-state) for various components of device 2400. For example, PCU 2410 and/or PMIC 2412 may select a power state (e.g., in accordance with the ACPI (Advanced Configuration and Power Interface) specification) for various components of device 2400. Merely as an example, PCU 2410 and/or PMIC 2412 may cause various components of the device 2400 to transition to a sleep state, to an active state, to an appropriate C state (e.g., C0 state, or another appropriate C state, in accordance with the ACPI specification), etc. In an example, PCU 2410 and/or PMIC 2412 may control a voltage output by VR 2414 and/or a frequency of a clock signal output by the clock generator, e.g., by outputting the VID signal and/or the FID signal, respectively. In an example, PCU 2410 and/or PMIC 2412 may control battery power usage, charging of battery 2418, and features related to power saving operation.
[0087] The clock generator 2416 can comprise a phase locked loop (PLL), frequency locked loop (FLL), or any suitable clock source. In some embodiments, each core of processor 2404 has its own clock source. As such, each core can operate at a frequency independent of the frequency of operation of the other core. In some embodiments, PCU 2410 and/or PMIC 2412 performs adaptive or dynamic frequency scaling or adjustment. For example, clock frequency of a processor core can be increased if the core is not operating at its maximum power consumption threshold or limit. In some embodiments, PCU 2410 and/or PMIC 2412 determines the operating condition of each core of a processor, and opportunistically adjusts frequency and/or power supply voltage of that core without the core clocking source (e.g., PLL of that core) losing lock when the PCU 2410 and/or PMIC 2412 determines that the core is operating below a target performance level. For example, if a core is drawing current from a power supply rail less than a total current allocated for that core or processor 2404, then PCU 2410 and/or PMIC 2412 can temporality increase the power draw for that core or processor 2404 (e.g., by increasing clock frequency and/or power supply voltage level) so that the core or processor 2404 can perform at higher performance level. As such, voltage and/or frequency can be increased temporality for processor 2404 without violating product reliability.
[0088] In an example, PCU 2410 and/or PMIC 2412 may perform power management operations, e.g., based at least in part on receiving measurements from power measurement circuitries 2442, temperature measurement circuitries 2440, charge level of battery 2418, and/or any other appropriate information that may be used for power management. To that end, PMIC 2412 is communicatively coupled to one or more sensors to sense/detect various values/variations in one or more factors having an effect on power/thermal behavior of the system/platform. Examples of the one or more factors include electrical current, voltage droop, temperature, operating frequency, operating voltage, power consumption, inter-core communication activity, etc. One or more of these sensors may be provided in physical proximity (and/or thermal contact/coupling) with one or more components or logic/IP blocks of a computing system. Additionally, sensor(s) may be directly coupled to PCU 2410 and/or PMIC 2412 in at least one embodiment to allow PCU 2410 and/or PMIC 2412 to manage processor core energy at least in part based on value(s) detected by one or more of the sensors.
[0089] Also illustrated is an example software stack of device 2400 (although not all elements of the software stack are illustrated). Merely as an example, processors 2404 may execute application programs 2450, Operating System (OS) 2452, one or more Power Management (PM) specific application programs (e.g., generically referred to as PM applications 2458), and/or the like. PM applications 2458 may also be executed by the PCU 2410 and/or PMIC 2412. OS 2452 may also include one or more PM applications 2456a, 2456b, 2456c. The OS 2452 may also include various drivers 2454a, 2454b, 2454c, etc., some of which may be specific for power management purposes. In some embodiments, device 2400 may further comprise a Basic Input/Output System (BIOS) 2420. BIOS 2420 may communicate with OS 2452 (e.g., via one or more drivers 2454), communicate with processors 2404, etc.
[0090] For example, one or more of PM applications 2458, 2456, drivers 2454, BIOS 2420, etc. may be used to implement power management specific tasks, e.g., to control voltage and/or frequency of various components of device 2400, to control wake-up state, sleep state, and/or any other appropriate power state of various components of device 2400, control battery power usage, charging of the battery 2418, features related to power saving operation, etc.
[0091] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.
[0092] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.
[0093] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.
[0094] In addition, well-known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.
[0095] Various embodiments described herein are illustrated as examples. The features of these examples can be combined with one another in any suitable way. These examples include:
[0096] Example 1: An apparatus comprising: a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a rising edge of the first clock; a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a rising edge of a second clock; and a circuitry coupled to the first and second flip-flops, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan enable is active.
[0097] Example 2: The apparatus of example 1, wherein the circuitry is to skew the first clock by substantially 180 degrees.
[0098] Example 3: The apparatus of example 1, wherein the rising edge of the second clock substantially aligns with a falling edge of the first clock.
[0099] Example 4: The apparatus of example 1, wherein the circuitry comprises: a multiplexer to select one of the first clock or a skewed version of the first clock; a sequential circuit to receive the first clock and the scan enable via an OR gate, wherein the sequential circuit is to provide a sampled output; and an AND gate coupled to an input of the multiplexer, wherein the AND gate is controllable by the first clock and the sampled output.
[00100] Example 5: The apparatus of example 4, wherein the OR gate is to receive the scan enable and a scan capture enable.
[00101] Example 6: The apparatus of example 5, wherein an output of the OR gate is received by the sequential circuit to clear the sampled output.
[00102] Example 7: The apparatus of example 5, wherein the AND gate is a first AND gate, and wherein the circuitry comprises a second AND gate to generate a control for the multiplexer, wherein the second AND gate is to receive the output of the OR gate and a skew circuit enable.
[00103] Example 8: The apparatus of example 7, wherein the skew circuit enable is to enable or disable the circuitry.
[00104] Example 9: A system comprising: a memory; a processor coupled to the memory; and a wireless interface to allow the processor to communicate with another device, wherein the processor includes a scan chain which is partitioned into at least a first partition and a second partition, wherein the first partition includes a first flip-flop to receive a first data input, a first scan input, a scan enable, and a first clock, wherein the first flip-flop is to sample one of the first data input or the first scan input at a first edge of the first clock, wherein the second partition includes a second flip-flop to receive a second data input, a second scan input, and the scan enable, wherein the second flip-flop is to sample one of the second data input or the second scan input at a second edge of a second clock, wherein the processor includes a circuitry coupled to the first and second flip-flops, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when the scan enable is active.
[00105] Example 10: The system of example 9 comprises an input to receive a test pattern for the scan chain.
[00106] Example 11: The system of example 9, wherein the circuitry is to skew the first clock by substantially 180 degrees.
[00107] Example 12: The system of example 9, wherein the second edge of the second clock substantially aligns with the first edge of the first clock, wherein second edge is phase shifted relative to the first edge by substantially 180 degrees.
[00108] Example 13: The system of example 9, wherein the circuitry is operable to provide the first clock as output when the circuitry is disabled.
[00109] Example 14: The system of example 9, wherein the circuitry is to receive the first clock and skew the first clock to generate the second clock when scan capture is enabled.
[00110] Example 15: A machine-readable storage media having machine-readable instructions that when executed cause one or more processors to perform a method comprising: identifying a portion of a chip having higher temperature or power consumption compared to another portion of the chip; dividing the portion into a first partition and a second partition; adding a clock skew circuit to the first partition and the second partition; operating a first scan chain of the first partition using a positive edge of a first clock; skewing the first clock by the clock skew circuit to generate a second clock which is skewed version of the first clock; and operating a second scan chain of the second partition using an edge of the second clock.
[00111] Example 16: The machine-readable storage media of example 15 having machine-readable instructions that when executed cause one or more processors to perform the method comprising: determining power for the first partition and the second partition.
[00112] Example 17: The machine-readable storage media of example 16 having machine-readable instructions that when executed cause one or more processors to perform the method comprising: comparing the power against a threshold, wherein the portion is a first portion, and performing, if the power is greater than the threshold, operations comprising: dividing the second portion into a first partition and a second partition; adding a second clock skew circuit to the first partition and the second partition of the second portion; operating a first scan chain of the second partition using a positive edge of the first clock; skewing the first clock by the second clock skew circuit to generate a third clock which is skewed version of the first clock; and operating the second scan chain of the second partition using an edge of the third clock.
[00113] Example 18: The machine-readable storage media of example 17 having machine-readable instructions that when executed cause one or more processors to perform the method comprising: performing layout of the first and second partitions of the first portion and the second portion if the power is less than the threshold.
[00114] Example 19: The machine-readable storage media of example 16, wherein the clock skew circuit is to skew the first clock by substantially 180 degrees.
[00115] Example 20: The machine-readable storage media of example 15, wherein a rising edge of the second clock substantially aligns with a falling edge of the first clock.
[00116] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.