DESC:TECHNICAL FIELD

The present subject matter described herein, in general relates to a communication technique in circuit breaker or switchgears, and more particularly, to achieving lower power consumption communication by changing the duty cycle of data line.

BACKGROUND

Circuit breaker is basically an instrument which is used to clear electrical faults if and when they occur. Nowadays we have Micro controller based circuit breaker. Many a times these controller based cards are also referred to as Smart Card or any other synonym name. The current generation of Circuit breakers (CBs) not only clear the fault but they also log down large amount of data. They share this data with other breakers in the system. One such standard communication protocol is deployed for communication between the modules that may include but not limited to Serial Peripheral Interface (SPI), serial communications interface (SCI), controller area network (CAN), MODBUS, Process Field Bus (Profibus), and the like.

In general a communicating system has a transmitter and receiver. They have data line for making exchange of information between them possible. The exchange of information takes place by changing the voltages on these lines. This basic concept of change of voltage levels on the data lines is common to all the communication system that includes but not limited to Universal asynchronous receiver/transmitter (UART), Serial Peripheral Interface (SPI), SCI, CAN, etc) but the number of Data lines may vary. For e.g., UART has two data line for exchanging data namely Rx and Tx. The data lines are kept at a particular voltage suitable to their idle conditions by using pull up or pull down resistors as shown in figure 2.

Further, most of the controllers have internal pull up or pull down resistors. The figure 3 shows the internal port diagram of the controller on Rx or Tx pins. In figure 3, when the pull up is enabled i.e. given high voltage level (1), the gate of the Pmos gets a low voltage signals which causes it to turn on and the In/Out signal line(Data line) is pulled up to a voltage level equal to EVdd (VCC). Also when we declare the pin as output pin (Control pin = 0) the voltage on the data line completely depends on the data that is being sent. When Data sent is 1 the output of NAND gate is 1 and that of NOR gate is 0. Thus Pmos is turned on and Nmos is turned off and the voltage on the Data line is same as that in Idle condition. However when the data that is sent is 0, it causes the NAND output to be high and turning off the pmos, while the output of NOR is high which turns on the Nmos. The data line is pulled to Evss (ground voltage) due to this and the voltage on the line is 0 (ground voltage). Also there is complete path now from EVdd to ground for current to flow causing current consumption. The flow of current will continue till the time the data is 0. Usually the data is kept 0 for entire duty cycle of the clock.

Hence it is evident that with the pull-up configuration sending logic ‘1’ i.e. output HIGH does not consume much power. Sending Logic ‘0’ i.e. output LOW sinks in current at the port pin pulling the line LOW. Therefore as per the invention, the communication of Bit with Logic ‘0’ has a duty cycle setting with which it can achieve very low power consumption.

In case of a battery operated systems even a small amount of power consumption is very critical.

SUMMARY

This summary is provided to introduce concepts related to a low power serial communication with modified duty cycle of the data line. This summary is not intended to identify essential features of the subject matter nor is it intended for use in determining or limiting the scope of the subject matter.

In one implementation, the present invention relates to achieving lower power consumption communication by changing the duty cycle of data line.

In one implementation, the present invention relates to a method and system to be implemented in such serial communication protocols to make the system power efficient.

In one implementation, the present invention discloses a technique for reduced power consumption in serial communication is achieved by varying the duty cycle of data line.

In one implementation, the present invention offers two settings i.e., the baud rate and duty cycle. The baud rate settings will be according to the base serial protocol with which the invention is implemented. According to the duty cycle settings which is user configured, the sampling rate is changed to sense the data reliably which is derived from the synchronized clock of both the transmitter and receiver.

Accordingly in one implementation, a serial communication system for power consumption reduction comprising one or more master(s) having one or more transmitter(s) and one or more slave(s) having one or more receiver(s), wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s) is disclosed. The system is CHARACTERIZED to detect one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmit said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

In one implementation, a method for power consumption reduction in a serial communication system having one or more transmitter(s) and one or more receiver(s), communicating over a serial data link using one or more protocol(s) is disclosed. The method CHARACTERIZED IN THAT COMPRISING detecting one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmitting said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

In one implementation, a method for reading data using one or more slave(s) having one or more receiver(s), in a serial communication system with one or more master(s) having one or more transmitter(s) and said slave(s) having said receiver(s), wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s) is disclosed. The method CHARACTERIZED IN THAT COMPRISING:

· configuring one or more analog to digital converter(s) and one or more timer(s);
· scrutinize a set duty cycle and a specific baud of said serial communication system, thereby
· configuring sample rate to sense data which is received from one or more clock frequencies;
· checking falling edge of clocks;
· sampling received data, wherein the data is received in signal(s);
· storing said data sampled in one or more buffer, and reading said stored data for processing.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to refer like features and components.

Figure 1 illustrates a serial peripheral interface (SPI) (available in prior-art), is shown.

Figure 2 illustrates pull up resistors being used externally (available in prior-art), is shown.

Figure 3 illustrates internal port diagram of the controller on receiver or transmitter pins (available in prior-art), is shown.

Figure 4 illustrates a comparison of the traditional data transmission method with the data transmission according to the present invention with the setting of 30% duty cycle is shown, in accordance with an embodiment of the present subject matter.

Figure 5 illustrates a flow chart of a receiver method to receive the data is shown, in accordance with an embodiment of the present subject matter.

DETAILED DESCRIPTION OF THE PRESENT INVNENTION

Preferred embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the present disclosure in unnecessary detail.

The terms and words used in the following description are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention.

It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise.

By the term “substantially” it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

Accordingly in one implementation, a circuit breaker communication system for transmission of data messages through a data bus between two or more user microprocessors coupled to said data bus, said user microprocessors having an interface port of the types: a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, said user microprocessors being coupled to said data bus by a bus interface integrated circuit is disclosed. The circuit breaker communication system comprises of at least one Master out Slave in (MOSI) signal wire; at least one Master In Slave Out (MISO) signal wire; at least one Serial Clock (SCLK or SCK) signal wire; and at least one Slave Select (SS) signal wire to at least one Chip Select (CS) signal wire.

In one implementation, said Serial Clock (SCLK or SCK) signal wire carries a signal is generated to synchronize data transfer between said two or more user microprocessors; and said Slave Select (SS) signal wire and said Chip Select (CS) signal wire carries an active low signal.

In one implementation, the circuit breaker communication system comprises of at least one master device and at least one slave device coupled using said data bus,. The said system comprises of a Master Out Slave In (MOSI) port configured to transmit at least one MOSI signal generated by said master device, whose recipient is said slave device; a Master In Slave Out (MISO) port configured to transmit at least one MISO signals generated by said slave device, whose recipient is said master device; a Serial Clock (SCLK or SCK) port configured to transmit at least one SCLK signal generated by said master device to synchronize a data transfer between said master and said slave; and a Slave Select (SS) port configured to carry SS signal generated by said master to select said slave device, whose recipient is Chip Select (CS) port on said slave device, wherein said SS signal carries an active low signal.

In one implementation, said MOSI wire and said MISO wire send and receive data serially.

In one implementation, a power consumption of said two or more user microprocessors, and said at least one master device and said at least one slave device changes based on an internal configuration, wherein said internal configuration comprises a pulled-up configuration and a pulled-down configuration.

In one implementation, a communication method used in a circuit breaker communication system for transmission of data messages through a data bus between two or more user microprocessors coupled to said data bus, said user microprocessors having an interface port of the types: a serial communications interface (SCI) port or a serial peripheral interface (SPI) port along with a clock port and an input/output port, said user microprocessors being coupled to said data bus by a bus interface integrated circuit is disclosed. The communication method comprises of sending said data messages with a set duty cycle, wherein said data messages are transmitted in bits; and varying said set duty cycle based on capacities and clock frequencies of two or more user microprocessors in said circuit breaker communication system.

In one implementation, the present invention relates to achieving lower power consumption communication by changing the duty cycle of data line.

In one implementation, the present invention may be implemented using any of the serial protocols like MODBUS, CAN, SPI, I2C, etc. This patent describes the invention along with SPI protocol (Serial Peripheral Interface) which is a synchronized serial communication protocol.

The Serial Peripheral Interface or SPI is a synchronous serial data link that operates in full-duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave-select lines. Sometimes SPI is called a four–wired serial bus, contrasting with three-, two- and one-wire serial buses. SPI is often referred to as SSI (Synchronous Serial Interface).

In an exemplary embodiment of the present invention, figure 1 shows the topology of SPI system with one master and one slave device connected. An SPI protocol specifies 4 signal wires as follows:
· Master out Slave in (MOSI), a MOSI signal is generated by master, recipient is the slave,
· Master In Slave Out (MISO) - Slaves generate MISO signals and recipient is the master,
· Serial Clock (SCLK or SCK) - SCLK signal is generated by the master to synchronize data transfer between the master and the slave, and
· Slave Select (SS) from master to Chip Select (CS) of slave - SS signal is generated by Master to select individual slave/peripheral devices. The SS/CS is an active low signal.

On MOSI and MISO lines devices send and receive data serially. Data consists of 1’s and 0’s. Now depending on the internal configurations of these lines (pulled-up or pulled-down) and power consumption varies. For e.g., if say MOSI line is pulled-up internally with pull-up resistors, it consumes negligible current and hence power, while sending logic ‘1’. However while sending logic ‘0’ the line is pulled down by switching on an internal solid state switch which causes a current sink-in consuming considerable amount of power. Similarly if pull down resistors are used then in contrast with the previous case it consumes power while sending logic ‘1’ instead of logic ‘0’.

The present invention describes a novel communication method with devices with internal pull-up resistors.

The present invention offers various settings to the user to enhance the operation of the system. Following table shows the settings offered to the user.

Duty Cycle Settings ( %) Power Consumption Band Sampling Rate
100 Normal Standard(As per the baud rate)
90 Low
80
70
60
50 Very Low Standard x 2
40
30
25 Ultra Low Standard x 4
20
15

In one implementation, duty cycles 100% indicates the normal operation where the output LOW is transmitted for full bit time period i.e. 100%.

In one implementation, duty Cycles from 90% to 60% indicate ‘LOW’ power consumption band which use the same standard sampling rate same as the Normal operation of 100% duty cycle.

In one implementation, duty cycles from 50% upto 30% indicate ‘VERY LOW’ power consumption band which requires sampling rate which is 2 times the standard sampling rate.

In one implementation, duty cycles from 25% upto 15% indicate ‘ULTRA LOW’ power consumption band which requires sampling rate which is 4 times the standard sampling rate.

As shown above 15% Duty Cycle Setting offers the lowest power consumption of 85% compared to normal operation.

Referring now to figure 4 illustrates a comparison of the traditional data transmission method with the data transmission according to the present invention with the setting of 30% duty cycle is shown, in accordance with an embodiment of the present subject matter. An example of data serially being sent with both the traditional and this novel scheme is shown.
Since sending logic ‘1’ does not consume current it is transmitted normally as HIGH for full bit-time period. But logic ‘0’ which is normally transmitted as LOW for full bit time, the invention says, it is transmitted with a set duty cycle for e.g. less than 50%. Here it’s shown as 30% duty cycle. The value could be varied as per the requirements of current consumption and data being transmitted. However the receiver is also required to sense this transition timing to indentify the data-bit. Hence according to the capacities and clock frequencies on which both the devices work the duty cycle can be varied.

In the present invention, with 30% duty cycle, there is a reduced current consumption during 70% of bit time period. Hence a lot of power is saved. Especially in cases where there are large number of logic ‘0’ to be transmitted, this method saves power which can be really useful in power critical application like battery operated devices.

Referring now to figure 5 a flow chart of a receiver method to receive the data is shown, in accordance with an embodiment of the present subject matter. In one implementation the flow of the receiver software to receive the data is shown in figure. The steps involved in the receiver method to receive the data comprises of:

1. At the power up controller configures the ADC and timer peripherals. ADC is required to sense the data bit voltage level to decide whether it’s a ‘1’ or a ‘0’. Timer is required for internal operation of counting of receiving clock edges to synchronize start and stop of transmission.

2. Read the settings of Duty Cycle and Baud rate of the communication.

3. According to the above two settings, controller configures the sampling rate of sensing the data referring to the look up table provided.

4. Now the receiver is ready to receive the clock from the transmitter to start sampling the incoming the data bits of the set duty cycle at the Rx pin.

5. When transmitter starts transmitting, receiver will start sampling the incoming data bits and putting them into the receive buffer. After the transmitter is finished with sending the data, it will stop the clock which indicates the receiver that the transmission is over.

6. The receiver sends the received data in the buffer ahead for processing.

In one implementation, the present invention enables reducing power consumption by modifying the duty cycle of the data line as explained above, reducing effective power consumption of the communication system. This helps in increasing the battery life of the system and thus can play an important role in power critical applications.

In one implementation, it may be understood by the person skilled in that art that any particular communication protocol may be used which is capable of sending data on a serial line, those may include but not limited to CAN, MODBUS, SPI, SCI, and the like.

Accordingly in one implementation, a serial communication system for power consumption reduction comprising one or more master(s) having one or more transmitter(s) and one or more slave(s) having one or more receiver(s), wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s) is disclosed. The system is CHARACTERIZED to detect one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmit said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

In one implementation, a method for power consumption reduction in a serial communication system having one or more transmitter(s) and one or more receiver(s), communicating over a serial data link using one or more protocol(s) is disclosed. The method CHARACTERIZED IN THAT COMPRISING detecting one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmitting said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

In one implementation, a method for reading data using one or more slave(s) having one or more receiver(s), in a serial communication system with one or more master(s) having one or more transmitter(s) and said slave(s) having said receiver(s), wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s) is disclosed. The method CHARACTERIZED IN THAT COMPRISING:
· configuring one or more analog to digital converter(s) and one or more timer(s);
· scrutinize a set duty cycle and a specific baud of said serial communication system, thereby
· configuring sample rate to sense data which is received from one or more clock frequencies;
· checking falling edge of clocks;
· sampling received data, wherein the data is received in signal(s);
· storing said data sampled in one or more buffer, and reading said stored data for processing.

In one implementation, said set duty cycle is selected from a range varying from 15 % to 50 %, depending on requirements of power consumption and data being transmitted.

In one implementation, said master(s) and said slave(s) have internal pull-up resistors and internal pull-down resistors.

In one implementation, said set duty cycle is varied based on a capacity and one or more clock frequencies of said transmitter(s) and said receiver(s). In one example, based on the duty cycle set by the programmer (or may be automatically set), the receiver configures its sampling rate based on the table provided earlier to sense the data bit reliably. In one implementnantion, the capacity may be a capacity of receiver and/or transmitter (micro controllers) to reliably detect the signals. This detection of signals depends on sampling rate which subsequently depends on the clock frequency i.e., the processing speed of controller.

In one implementation, said receiver(s) is configured to set a sampling rate to sense said bit(s) transmitted. As, the transmitter and receiver are in synchronization in terms of the ’Duty cycle’ and ‘Baud rate’ settings, the receiver sets the sampling rate accordingly to sense the data bit reliably. In one implementation, a transition time may be sensed by the receiver. The transition time may be the time taken to change the state i.e., from 0 to 1 or the converse.

In one implementation, said specific baud rate is based on said one or more protocol(s) used in said serial communication system. It may be understood that the baud rate depend on the protocol that is selected. Each of them may have their own range.

In one implementation, said set duty cycle enables a change in sampling rate to sense data which is derived from one or more clock frequencies of said transmitter(s) and said receiver(s).

Exemplary embodiments discussed above may provide certain advantages. Though not required to practice aspects of the disclosure, these advantages may include those provided by the following features:

One features of the invention is that, the propose invention provides Reduced Power consumption in serial communication is achieved by varying the duty cycle of data line for e.g., by keeping the duty cycle 30% we save the power during remaining 70% of the duty cycle time.

Another feature of the invention is that, the present invention is useful in power critical applications like battery operated systems as it helps in saving power consumption.

Another feature of the invention is that, the present invention can be implemented with other serial communication protocols as MODBUS, CAN, I2C, etc.

Yet another feature of the invention is that, a battery operated product can go on for longer time in system where the above described method is adopted as compared to any normal communication system.

Apart from above mentioned features, the present invention has some unique features, few of them are mentioned below:

· A scheme of serial communication in which a bit which consumes more power e.g., Logic ‘0’ in case of pull-up configuration, is transmitted with 30% duty cycle which is well understood by the receiver in the communication system is present. This significantly reduces power consumption during communication. and
· A scheme for serial communication which reduces power consumption significantly whereas the patent filed by Atmel Corporation is about a bus circuitry for 2-wire communication with ‘active pull-ups’ for improved data throughput and reduced noise is present.

Although a low power serial communication with modified duty cycle of the data line has been described in language specific to structural features and/or methods, it is to be understood that the embodiments disclosed in the above section are not necessarily limited to the specific features or methods or devices described. Rather, the specific features are disclosed as examples of a low power serial communication with modified duty cycle of the data line.
,CLAIMS:1. A serial communication system for power consumption reduction comprising one or more master(s) having one or more transmitter(s)and one or more slave(s) having one or more receiver(s),wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s), CHARACTERIZED to detect one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmit said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

2. The serial communication system as claimed in claim 1, wherein said set duty cycle is selected from a range varying from 15 % to 50 %, depending on a requirements of power consumption and data being transmitted.

3. The serial communication system as claimed in claims 1 and 2, wherein said master(s) and said slave(s) have internal pull-up resistors and internal pull-down resistors.

4. The serial communication system as claimed in claims 1 to 3, wherein said set duty cycle is varied based on a capacity and one or more clock frequencies of said transmitter(s) and said receiver(s).

5. The serial communication system as claimed in claims 1 to 4, wherein said receiver(s) is configured to set a sampling rate to sense said bit(s) transmitted.

6. The serial communication system as claimed in claims 1 to 5, wherein said specific baud rate is based on said one or more protocol(s) used in said serial communication system.
7. The serial communication system as claimed in claims 1 to 5, wherein said set duty cycle enables a change in sampling rate to sense data which is derived from one or more clock frequencies of said transmitter(s) and said receiver(s).

8. A method for power consumption reduction in a serial communication system having one or more transmitter(s) and one or more receiver(s), communicating over a serial data link using one or more protocol(s), said method CHARACTERIZED IN THAT COMPRISING: detecting one or more bit(s), during said serial communication, transmitted with high power, thereby automatically transmitting said bit(s) detected with a set duty cycle and a specific baud rate to reduce power consumption in said serial communication.

9. The method as claimed in claim 8, wherein said set duty cycle is selected from a range varying from15 % to 50 %, depending on a requirements of power consumption and data being transmitted.

10. The method as claimed in claims8 and 9 wherein said set duty cycle is varied based on a capacity and one or more clock frequencies of said transmitter(s) and said receiver(s).

11. The method as claimed in claims 8 to 10, wherein said receiver(s) is configured to sense a transition timing to indentify said bit(s) transmitted.

12. The method as claimed in claims 8 to 11, wherein said specific baud rate is based on said one or more protocol(s) used in said serial communication system.

13. The method as claimed in claims 8 to 12, wherein said set duty cycle enables a change in sampling rate to sense data which is derived from one or more clock frequencies of said transmitter(s) and said receiver(s).

14. A method for reading data using one or more slave(s) having one or more receiver(s), in a serial communication system with one or more master(s) having one or more transmitter(s) and said slave(s) having said receiver(s),wherein said transmitter and said receiver are configured to communicate over a serial data link using one or more protocol(s),said method CHARACTERIZED IN THAT COMPRISING:configuring one or more analog to digital converter(s) and one or more timer(s);scrutinize a set duty cycle and a specific baud of said serial communication system, thereby configuring sample rate to sense data which is received from one or more clock frequencies; checking falling edge of clocks; sampling received data, wherein the data is received in signal(s);storing said data sampled in one or more buffer, and reading said stored data for processing.