FIELD OF THE INVENTION
This invention relates to Measurement of High Frequency Signals Through FPGA for
use in Flight Data Acquisition System (DAS) and, more particularly, for receiving, conditioning &
measurement of Frequency Signals and conversion in digital form to record the data in Flight
Data Recorder (FDR).
BACKGROUND OF THE INVENTION
The development of solid state memory devices, such as electrically erasable read-only
memory, has led to the design of all solid state flight data recorders. The solid state flight data
recorders commonly employ a data acquisition system (DAS) which receives and processes the
various aircraft input signals to be monitored and stored under the control of a central
processing unit (CPU). The analog signals are converted to digital signals by the DAS and,
under CPU control, are passed over a data bus to the solid state memory devices.
Programming within the CPU controls the processing of input airplane signals to corresponding
digital signals through the DAS and the subsequent transference of these digital signals to
controlled locations in the solid state memory.
The signals representative of monitored aircraft parameters are typically either discrete
level signals or analog signals. Discrete signals are typically switch positions and produce either
a high or a level output depending upon the status of the particular switch.
Further, it is desirable to conform the flight data recorder such that it is capable of being
conveniently modified to operate in any one of several different types of aircraft. To this end, the
DAS is preferably configured such that its inputs may be assigned by the CPU to handle any
analog, Frequency (Engine Parameter) or discrete input signal. Further, the levels of the various
signals at the inputs of the DAS must often be sealed for proper processing within the DAS.
Frequency Signals are generally tapped from tacho amplifier/generator. Input to the tacho
generator is rpm signal of engine of aircraft. Further tapped frequency signals are required to
measure for health of the engines during flight. This is critical parameter for health analysis of
the Aircraft.
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to Measurement of High frequency through
FPGA for use in a Flight data acquisition system of FDR.
An aspect of the present invention is the ability of the data acquisition system to process
a set of frequency parameter sense signals in response to a single CPU request and measure
the frequency signal.
A further aspect of the invention is the universal application of the frequency
measurement with present data acquisition system. Frequency input signals are grouped as two
high frequency and one low frequency signals. Each group consists of two frequency input
signals.
The required signal conditioning logic for the frequency inputs is provided using
operational amplifiers. After signal conditioning the inputs are fed to the FPGA where the signal
selection logic is implemented and then signals are passed to the central processing module of
the DAS. The signals are interfaced to counters of the processor of DAS.
Four identical, 16-bit, general-purpose timers of processor are configured to use as timer
counters for counting the Frequency input pulses.
High frequency signals are fed to 16 bit counter of the processor. Frequency signals are
fed to 32 bit counter (cascade of two 16bit counters) of the processor.
For testability, 1 MHz and 1 KHz reference signals are provided for High frequency
signals respectively.
Each high frequency signal will be measured for number of pulses in 200 msec duration
and the accumulated pulses count will be converted as frequency value of the input signal.
The time period will be measured by using 1 MHz clock signal. Upon detection of
rising/falling edge of actual frequency signal, 1MHz clock signal will be fed to 32 bit counter of
the processor. The accumulated number of pulses until the detection of next rising/falling edge
will be converted as frequency value of the input signal. If the rising/falling edge does not come
within 250msec, timeout bit will be set in frequency status register.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention will become more apparent and
descriptive in the description when considered together with figures/f charts presented:
Figure 1: is a Block Diagram of Measurement of High Frequency through FPGA
Figure 2: is a Block Diagram of Frequency Condition Circuits
Figure 3: is a Block Diagram of Frequency measurement through FPGA
DETAILED DESCRIPTION
The Hardware Architecture of each module of the Measurement of High Frequency
Signals through FPGA is described in following sections:
FREQUENCY CONDITIONING CIRCUIT:
The required signal conditioning circuit for the frequency inputs is provided using
operational amplifier devices. After spike & voltage suppression circuits the inputs are fed to the
Multiplexer which selects various frequency inputs based on its address select lines, which are
obtained from the hex latch. Then each selected frequency signals are passed through the
Schmitt trigger to convert into TTL pulse. These pulses are interfaced to FPGA where the
signal selection logic is implemented and then signals are passed to the central processing
module of the DAS. The signals are interfaced to counters of the processor of DAS. Frequency
conditioning circuits is attached at Figure: 2.
The output of the de-multiplexer is used to clock the data lines into hex latch. The
Multiplexer selects various frequency inputs based on its address select lines, which are
obtained from the hex latch. The Operational amplifiers form an instrumentation amplifier with
high common mode rejection, which converts the selected differential signal into a single ended
signal and converts it into TTL logic levels using Schmitt trigger. Further TTL pulse of each
conditioned frequency signals are fed to the FPGA for measurement of frequency channels.
FPGA BLOCK:
The FPGA device is Xilinx series family provides high-density programmable logic
solutions. This device provides Control and the Decoding logic for frequency selection,
measurement and gating logic for the module.
Frequency block addresses the interface of all frequency input signals. The signals are
interfaced to counters of the processor through some selection logic.
All frequency input signals are grouped as two high frequency and one frequency
signals. Each group consists of two frequency input signals.
Measurement of High Frequency
This Signal FOUT is assigned either FIN1, FIN2 or Reference signal (1KHz)
depending up on the frequency channel selection signal (FreqChSel) and Reference signal
selection (Ref sel).
If FreqChSel is '0' and Ref Sel is '0' FIN1 is assigned,
if FreqChSel is '1' and Ref Sel is '0' FIN2 is assigned
and FreqChSel is '0' or '1' and Ref Sel is '1' Reference signal of 1KHz is assigned this
signal are assigned for a duration of 200ms.
Ch Sel = ‘0’ NF1/NG1/NR will be selected to respective frequency inputs
Ch Sel = ‘1’ NF2/NG2/Fuel Qty will be selected to respective frequency inputs
FREQUENCY MEASUREMENT:
Four identical, 16-bit, general-purpose timers of CPU are configured to use as timer
counters for counting the Frequency input pulses. High frequency signals are fed to 16 bit
counter of the processor.
For testability, 1KHz reference clock is measured for 200msec for high frequency
channels
Each high frequency signal will be measured for number of pulses in 200 msec duration
and the accumulated pulses count will be converted as frequency value of the input signal.
The time period will be measured by using 4 MHz clock signal. Upon detection of
rising/falling edge of actual frequency signal, 4MHz clock signal will be fed to 32 bit counter of
the processor. The accumulated number of pulses until the detection of next rising/falling edge
will be converted as frequency value of the input signal. If accumulated value is T(micro sec)
then 1/T is the actual frequency. If the rising/falling edge does not come within 250msec,
timeout bit will be set in frequency status register.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Measurement of High frequency through FPGA is used for recording the actual sensed values of frequency parameters from a plurality of aircraft engine sensors at different modes of the aircraft flight profile, comprising:
Frequency Conditioning means for providing the spike free and over voltage protected signals to back end module of the device;
frequency selection means, Selection of more than one signal with frequency select logic generated by processor and glue logic generated by FPGA;
said conversion of edge triggered pulse (TTL Pulse) means conversion of analog signals to digital signals for detection of edge for measurement of frequency;
said measurement of frequency means, selected frequency is used for measurement through FPGA program and the frequency output from FPGA is measured by counter of processor.

2. The module of claim 1 wherein the conditioning circuit includes the operational amplifiers form an instrumentation amplifier with high common mode rejection, which converts the selected differential signal into a single ended signal and converts it into TTL logic levels using Schmitt trigger.

3. The module of claim 1 wherein said spike & overvoltage means frequency signal is passed to the spike & overvoltage protected signals which added due to engine sensor.

4. The module as claimed in any of the preceding claims wherein each high frequency signal is measured for number of pulses in 200 msec duration and the accumulated pulses count is converted as frequency value of the input signal.

5. The module as claimed in any of the preceding claims wherein each frequency signal, the frequency value is obtained by measuring the time period either between rising edge to rising edge or between falling edges to falling edge.

6. The module of claim 3 & 4 wherein the time period will be measured by using 4 MHz clock signal. Upon detection of rising/falling edge of actual frequency signal, 4MHz clock signal will be fed to 32 bit counter of the processor.

7. The module of claim 1 wherein FPGA device provides high-density programmable logic solutions. This device provides Control and the Decoding logic for frequency selection, measurement and gating logic for the module

8. The module as claimed in any of the preceding claims wherein frequency block addresses the interface of all frequency input signals. The signals are interfaced to counters of the processor through some selection logic. ,TagSPECI:As per Annexure-II