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Measuring Bit Error Rate During Runtime Of A Receiver Circuit

Abstract: In one embodiment a receiver includes: a data path having a first slicer to receive and sample an incoming analog signal and to determine a bit level for the incoming analog signal the first slicer to provide a bit decision to a consuming logic; an analysis path having a second slicer to receive and sample the incoming analog signal and to determine a second bit level for the incoming analog signal; and a controller coupled to receive an output of the first slicer and an output of the second slicer to determine a bit error rate for the data path based on the first and second slicer outputs. Other embodiments are described and claimed.

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Notices, Deadlines & Correspondence

Patent Information

Application #
Filing Date
21 February 2017
Publication Number
14/2017
Publication Type
INA
Invention Field
COMMUNICATION
Status
Email
Parent Application
Patent Number
Legal Status
Grant Date
2024-02-26
Renewal Date

Applicants

INTEL CORPORATION
2200 Mission College Boulevard Santa Clara California 95054.

Inventors

1. HERNANDEZ SOSA, Gaudencio
Periférico Sur 7980 Edif. 4E, Santa María Tequepexpan, Tlaquepaque, Guadalajara, OU, 45600.
2. KOLLIA, Varvara
3600 Juliette Ln., Santa Clara, California 95054.

Specification

the plurality of phases, iteratively adjust the second reference level and estimate the BER according to the second reference level, until a linear trend regarding the BER is determined, and thereafter extrapolate the linear trend to determine the BER for the corresponding phase.
23. The system of claim 19, wherein the receiver is to communicate the BER to the transmitter, and wherein the transmitter is to reduce an amplitude of the analog signal based on comparison of the BER to a threshold, the reduced amplitude to reduce power consumption of the transmitter.
24. The system of claim 19, wherein the receiver comprises one or more gain control circuits to receive and amplify the analog signal, an equalizer coupled to the one or more gain control circuits to equalize the amplified analog signal and to provide the equalized amplified analog signal to the first comparator and the second comparator,
25. The system of claim of 24, further comprising a control logic to control at least one of the one or more gain control circuits or the equalizer based at least in part on the BER.

Documents

Application Documents

# Name Date
1 Priority Document [21-02-2017(online)].pdf 2017-02-21
2 Form 5 [21-02-2017(online)].pdf 2017-02-21
3 Drawing [21-02-2017(online)].pdf 2017-02-21
4 Description(Complete) [21-02-2017(online)].pdf_186.pdf 2017-02-21
5 Description(Complete) [21-02-2017(online)].pdf 2017-02-21
6 201747006134.pdf 2017-02-22
7 Form 18 [23-02-2017(online)].pdf 2017-02-23
8 Form5_After Filing_06-03-2017.pdf 2017-03-06
9 Other Patent Document [15-03-2017(online)].pdf 2017-03-15
10 Form 26 [20-03-2017(online)].pdf 2017-03-20
11 Correspondence By Agent_Proof Of Right_20-03-2017.pdf 2017-03-20
12 Correspondence by Agent_Power Of Attorney_24-03-2017.pdf 2017-03-24
13 Form 3 [28-03-2017(online)].pdf 2017-03-28
14 201747006134-FER.pdf 2020-01-28
15 201747006134-Information under section 8(2) [27-07-2020(online)].pdf 2020-07-27
16 201747006134-FORM 3 [27-07-2020(online)].pdf 2020-07-27
17 201747006134-OTHERS [28-07-2020(online)].pdf 2020-07-28
18 201747006134-FER_SER_REPLY [28-07-2020(online)].pdf 2020-07-28
19 201747006134-CLAIMS [28-07-2020(online)].pdf 2020-07-28
20 201747006134-US(14)-HearingNotice-(HearingDate-02-11-2023).pdf 2023-10-10
21 201747006134-Correspondence to notify the Controller [10-10-2023(online)].pdf 2023-10-10
22 201747006134-Correspondence to notify the Controller [31-10-2023(online)].pdf 2023-10-31
23 201747006134-PatentCertificate26-02-2024.pdf 2024-02-26
24 201747006134-IntimationOfGrant26-02-2024.pdf 2024-02-26

Search Strategy

1 search_07-01-2020.pdf

ERegister / Renewals