WE CLAIM:
1. A memory array comprising:
a plurality of first wires;
at least one second wire crossing the first wires; and
a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the memory elements being formed on a substrate,
either the first electrode or the second electrode being connected to one of the first wires,
at least one of the memory elements having an applied layer in an area between the first electrode and the second electrode,
the memory elements including two kinds of memory elements different from each other in electrical characteristics between the first electrode and the second electrode by the applied layer,
information to be recorded being determined by arrangement with any combination of the two kinds of memory elements.
2. The memory array according to claim 1, wherein
the applied layer is a semiconductor layer formed of a semiconductor material applied to the area between the first electrode and the second electrode,
out of the two kinds of memory elements, one kind of

memory element is a memory element having the semiconductor layer, whereas another kind of memory element is a memory element not having the semiconductor layer, and
the one kind of memory element and the other kind of memory element record respective pieces of information different from each other by presence or absence of the semiconductor layer.
3. The memory array according to claim 1, wherein
the applied layer is formed of a semiconductor
material applied to the area between the first electrode and the second electrode and is a first semiconductor layer or a second semiconductor layer, the first and the second semiconductor layers being different from each other in electrical characteristics,
out of the two kinds of memory elements, one kind of memory element is a memory element having the first semiconductor layer, whereas another kind of memory element is a memory element having the second semiconductor layer, and
the one kind of memory element and the other kind of memory element record respective pieces of information different from each other by a difference in electrical characteristics between the first semiconductor layer and the second semiconductor layer.
4. The memory array according to claim 3, wherein the second semiconductor layer contains a semiconductor material different from that of the first semiconductor layer.
5. The memory array according to claim 3 or 4, wherein a film thickness of the second semiconductor layer is larger

than a film thickness of the first semiconductor layer.
6. The memory array according to claim 4 or 5, wherein
the first semiconductor layer and the second semiconductor
layer each contain one or more selected from the group
consisting of carbon nanotubes, graphene, fullerenes, and
organic semiconductors as the semiconductor material.
7. The memory array according to claim 3, wherein
the first semiconductor layer and the second
semiconductor layer each contain carbon nanotubes as the semiconductor material, and
a concentration of carbon nanotubes of the second semiconductor layer is higher than a concentration of carbon nanotubes of the first semiconductor layer.
8. The memory array according to claim 1, wherein
the memory elements each have a semiconductor layer formed of a semiconductor material applied so as to be in contact with the insulating layer in the area between the first electrode and the second electrode,
the applied layer is formed of an insulating material applied so as to be in contact with the semiconductor layer from a side opposite the insulating layer in the area between the first electrode and the second electrode, and is a first insulating layer or a second insulating layer that changes electrical characteristics of the semiconductor layer into electrical characteristics different from each other,
out of the two kinds of memory elements, one kind of memory element is a memory element having the first insulating layer, whereas another kind of memory element is a memory element having the second insulating layer, and

the one kind of memory element and the other kind of memory element record respective pieces of information different from each other by a difference in the electrical, characteristics of the semiconductor layer by the first insulating layer and the second insulating layer.
9. The memory array according to claim 2 or 8, wherein the semiconductor layer contains one or more selected from the group consisting of carbon nanotubes, graphene, fullerenes, and organic semiconductors.
10. The memory array according to any one of claims 2, 8, and 9, wherein the semiconductor layer contains carbon nanotubes.
11. The memory array according to any one of claims 6, 7, 9, and 10, wherein the carbon nanotubes contain a carbon nanotube composite in which a conjugated polymer is attached to at least part of surfaces of the carbon nanotubes.
12. A method for manufacturing a memory array including a plurality of first wires, at least one second wire crossing the first wires, and a plurality of memory elements provided in correspondence with respective intersections of the first wires and the at least one second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the first wires, the at least one second wire, and the first wires, the at least one second wire, and the

memory elements being formed on a substrate,
the method comprising an application process of forming an applied layer in an area between the first electrode and the second electrode of at least one memory element out of the memory elements by application.
13. The method for manufacturing a memory array according
to claim 12, wherein
the applied layer is a semiconductor layer, and the application process forms the semiconductor layer in the area between the first electrode and the second electrode of a memory element to which the applied layer is to be applied selected out of the memory elements in correspondence with information to be recorded.
14. The method for manufacturing a memory array according
to claim 12, wherein
the applied layer is a first semiconductor layer or a second semiconductor layer, the first and the second semiconductor layers being different from each other in electrical characteristics, and
the application process forms the first semiconductor layer or the second semiconductor layer in the area between the first electrode and the second electrode of each of the memory elements in correspondence with information to be performed.
15. The method for manufacturing a memory array according
to claim 12, wherein
the applied layer is a first insulating layer or a second insulating layer different from each other in electrical characteristics,
a semiconductor layer being in contact with the

insulating layer is formed in advance in the area between the first electrode and the second electrode of each of the memory elements, and
the application process forms the first insulating layer or the second insulating layer so that the first or second insulating layer to be formed is in contact with the semiconductor layer from a side opposite the insulating layer in the area between the first electrode and the second electrode of each of the memory elements in correspondence with information to be recorded.
16. The method for manufacturing a memory array according to any one of claims 12 to 15, wherein the application is any one selected from the group consisting of ink jetting, dispensing, and spraying.
17. A memory array sheet comprising a combination of a plurality of memory arrays according to any one of claims 1 to 11 formed on a sheet,
respective pieces of information recorded in the memory arrays formed on the sheet being different from each other.
18. A memory array sheet comprising a combination of a
plurality of memory arrays each including a plurality of
first wires, at least one second wire crossing the first
wires, and a plurality of memory elements provided in
correspondence with respective intersections of the first
wires and the at least one second wire, the memory arrays
being formed on a sheet,
the memory elements including two kinds of memory elements including a memory element with a first wire pattern electrically connected to both the first wire and

the second wire and a memory element with a second wire pattern not electrically connected to at least either the first wire or the second wire,
the first wire pattern and the second wire pattern being formed of an electric conductive material applied to the sheet,
information to be recorded in the memory arrays being determined by arrangement with any combination of the two kinds of memory elements,
respective pieces of information recorded in the memory arrays formed on the sheet being different from each other.
19. The memory array sheet according to claim 18, wherein
the memory element with the first wire pattern has a
first electrode electrically connected to one of the first wires, a second electrode electrically connected to the first electrode via a semiconductor layer, and a third electrode electrically connected to one of the at least one second wire, and
the memory element with the second wire pattern lacks at least one of electric connection between one of the first wires and the first electrode, electric connection between the first electrode and the second electrode, and electric connection between one of the at least one second wire and the third electrode.
20. A method for manufacturing a memory array sheet
including a combination of a plurality of memory arrays
each including a plurality of first wires, at least one
second wire crossing the first wires, and a plurality of
memory elements provided in correspondence with respective
intersections of the first wires and the at least one

second wire and each having a first electrode and a second electrode arranged spaced apart from each other, a third electrode connected to one of the at least one second wire, and an insulating layer that electrically insulates the first electrode and the second electrode and the third electrode from each other, the memory arrays being formed on a sheet,
the method for manufacturing a memory array sheet comprising an application process of forming an applied layer by application in an area between the first electrode and the second electrode of at least one memory element out of the memory elements,
respective pieces of information different from each other being recorded in the memory arrays formed on the sheet.
21. The method for manufacturing a memory array sheet
according to claim 20, wherein
the applied layer is a semiconductor layer, and the application process forms the semiconductor layer in the area between the first electrode and the second electrode of a memory element to which the applied layer is to be applied selected out of the memory elements in correspondence with information to be recorded.
22. The method for manufacturing a memory array sheet _ -
according to claim 20, wherein
the applied layer is a first semiconductor layer or a second semiconductor layer, the first and the second semiconductor layers being different from each other in electrical characteristics, and
the application process forms the first semiconductor layer or the second semiconductor layer in the area between

the first electrode and the second electrode of each of the memory elements in correspondence with information to be performed.
23. The method for manufacturing a memory array sheet
according to claim 20, wherein
the applied layer is-a first insulating layer or a second insulating layer different from each other in electrical characteristics,
a semiconductor layer being in contact with the insulating layer is formed in advance in the area between the first electrode and the second electrode of each of the memory elements, and
the application process forms the first insulating layer or the second insulating layer so that the first or second insulating layer to be formed is in contact with the semiconductor layer from a side opposite the insulating layer in the area between the first electrode and the second electrode of each of the memory elements in correspondence with information to be recorded.
24. A method for manufacturing a memory array sheet
including a combination of a plurality of memory arrays
each including a plurality of first wires, at least one
second wire crossing the first wires, and a plurality of
memory elements provided in correspondence with respective
intersections of the first wires and the at least one
second wire, the memory arrays being formed on a sheet,
the method for manufacturing a memory array sheet comprising, for each memory element included in the memory elements, an application process of forming a first wire pattern, in which both the first wire and the second wire and the memory element are electrically connected to each