Claims:An apparatus comprising:
a memory bandwidth monitor per thread local to a core, each thread’s local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QoS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and
execution resources to support execution of at least one thread of the core.
, Description:RELATED APPLICATION
[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/214,851 filed March 27, 2021 and titled “MEMORY BANDWIDTH CONTROL IN A CORE” the entire disclosure of which is hereby incorporated by reference.

FIELD OF INVENTION
[0002] The field of invention relates generally to computer architecture, and, more specifically, to allocating shared resources.
BACKGROUND
[0003] Processor cores in multicore processors may use shared system resources such as caches (e.g., a last level cache or LLC), system memory, input/output (I/O) devices, and interconnects. The quality of service provided to applications may be degraded and/or unpredictable due to contention for these or other shared resources.
[0004] Some processors include technologies, such as Resource Director Technology (RDT) from Intel Corporation, that enable visibility into and/or control over how shared resources such as LLC and memory bandwidth are being used by different applications executing on the processor. For example, such technologies may provide for system software to allocate different amounts of a resource to different applications and/or monitor resource usage and temporarily prevent access to a resource by a low priority application that exceeds a quota.

BRIEF DESCRIPTION OF DRAWINGS
[0005] Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:
[0006] FIG. 1 illustrates a block diagram of a system in which per thread memory bandwidth is supported.
[0007] FIG. 2 illustrates embodiments of the IA32_PQR_ASSOC MSR and IA32_Qos_Core_BW_Thrtl_N MSRs.
[0008] FIG. 3 illustrates examples of the mapping of software exposed MSRs to microarchitectural resources.
[0009] FIG. 4 illustrates an exemplary method flow that involves changing memory bandwidth in a core.
[0010] FIG. 5 illustrates embodiments of an exemplary system.
[0011] FIG. 6 illustrates a block diagram of embodiments of a processor 600 that may have more than one core, may have an integrated memory controller, and may have integrated graphics.
[0012] FIG. 7(A) is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue/execution pipeline according to embodiments of the invention.
[0013] FIG. 7(B) is a block diagram illustrating both an exemplary embodiment of an in-order architecture core and an exemplary register renaming, out-of-order issue/execution architecture core to be included in a processor according to embodiments of the invention.
[0014] FIG. 8 illustrates embodiments of execution unit(s) circuitry, such as execution unit(s) circuitry 762 of FIG. 7(B).
[0015] FIG. 9 is a block diagram of a register architecture 900 according to some embodiments.
[0016] FIG. 10 illustrates embodiments of an instruction format.
[0017] FIG. 11 illustrates embodiments of the addressing field 1005.
[0018] FIG. 12 illustrates embodiments of a first prefix 1001(A).
[0019] FIGS. 13(A)-(D) illustrate embodiments of how the R, X, and B fields of the first prefix 1001(A) are used.
[0020] FIGS. 14(A)-(B) illustrate embodiments of a second prefix 1001(B).
[0021] FIG. 15 illustrates embodiments of a third prefix 1001(C).
[0022] FIG. 16 illustrates a block diagram contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set according to embodiments of the invention.
DETAILED DESCRIPTION
[0023] The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for adjusting memory bandwidth of a core.
[0024] In the following description, numerous specific details are set forth. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure the understanding of this description.