Claims:1. An apparatus comprising:
a memory which is logically partitioned into a first section and a second section, wherein the first section is online in a low power mode;
logic to determine whether user memory in the second section is greater than available space in the first section; and
a power control unit communicatively coupled to the memory, wherein the power control unit is to receive instructions from an operating system to move contents from the second section to the first section in response to a determination by the logic that the user memory in the second section is less than the available space in the first section.

, Description:BACKGROUND
[0001] More than 20% to 50% of mobile stand-by power is attributed towards memory (e.g., dynamic random access memory (DRAM)) self-refresh. DRAM consists of a transistor and a capacitor. The capacitor is charged regularly for it to retain the data. So, even during standby the DRAM continuously consumes power to retain data. Consider a system with 8 GB random access memory (RAM). Higher RAM is needed in a system for better performance but has the side-effect of draining more power due to higher number of capacitors to refresh.

BRIEF DESCRIPTION OF THE DRAWINGS
[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
[0003] Fig. 1 illustrates a memory view showing logical and physical partitions for partial array self-refresh.
[0004] Fig. 2 illustrates a logical view of a memory partitioned by an operating system to reduce power consumption, in accordance with some embodiments.
[0005] Fig. 3 illustrates a flowchart of partial array self-refresh to manage memory power performance, in accordance with some embodiments.
[0006] Fig. 4 illustrates a system-level flowchart for low power entry, in accordance with some embodiments.
[0007] Fig. 5 illustrates a system-level flowchart for low power exit, in accordance with some embodiments.
[0008] Fig. 6 illustrates a smart device or a computer system or an SoC (System-on-Chip) with hardware and software to manage memory to reduce power consumption, in accordance with various embodiments.

DETAILED DESCRIPTION
[0009] When a system is idle and nothing much is running in the background, the RAM utilization of the system is low (e.g., just half). This can further be reduced by flushing. Currently in most computing systems (e.g., mobile devices such as phones, laptops, tablets) refresh current is passed through the RAM to refresh the entire 100% of RAM space even if 50% of the space is being used. The excess refresh current is a waste of power. One way to reduce this excess refresh is by refreshing at lower level granularity. In that regards, the RAM is divided into several segments or banks. Each segment can be individually refreshed. For example, if only four segments from a total of eight segments contain valid data, then merely four segments can be refreshed, the other segments may not be refreshed, thus saving power. This selective refresh technique is generally referred to as Partial Array Self Refresh (PASR).