FIELD OF THE INVENTION
This invention relates to Memory Module for Data Acquisition Unit (DAU) of Flight Data
Recorder (FDR) and, more particularly, to storing of flight data in memory module.
BACKGROUND OF THE INVENTION
Flight data recorders are monitoring and recording instruments, carried aboard an
aircraft, which systematically monitor and store the instantaneous values of various aircraft
parameters. Early recorders were analog electromechanical devices which periodically marked,
in analog form, the value of a given airplane parameter on a moving wire or other permanent
storage medium. The time of occurrence of the parameter was also suitably scribed into the
medium opposite the mark for the sensed parameter. Subsequently, digital flight data recorders
have been developed which operate by converting each analog aircraft parameter into a
corresponding digital signal, and storing the digital signals on a permanent storage medium
such as magnetic tape.
The numerous mechanical parts employed in the analog and digital type
electromechanical flight data recorders have rendered such units expensive to construct and
bulky in design, requiring periodic maintenance of the mechanical parts. In addition, extraction
of the stored data from these data recorders requires physical removal of the storage medium.
The development of solid state memory devices, such as electrically erasable read-only
memory, has led to the design of all solid state flight data recorders. The solid state flight data
recorders commonly employ a data acquisition system (DAS) which receives and processes the
various aircraft input signals to be monitored and stored under the control of a central
processing unit (CPU). The analog signals are converted to digital signals by the DAS and,
under CPU control, are passed over a data bus to the solid state memory devices.
Programming within the CPU controls the processing of input airplane signals to corresponding
digital signals through the DAS and the subsequent transference of these digital signals to
controlled locations in the solid state memory.
The signals representative of monitored aircraft parameters are typically either discrete
level signals or analog signals. Discrete signals are typically switch positions and produce either
a high or a low level output depending upon the status of the particular switch. A typical
example in an aircraft is a squat switch, which indicates whether or not a load is being borne by
the landing gear.
The Data acquisition unit, the main LRU in the system. It acquires data from cockpit
voice, analog inputs, thermocouples, RTDs, Tacho, discrete inputs, MIL1553B bus & ARINC
429 channels from the aircraft. The acquired data is stored in Flash memory available within the
DAU and the selected parameters are sent to Recorder Unit (RU) through ARINC 717 interface.
The stored parameters in DAU flash memory are milked out through Ethernet 10/100 port.
These parameters are used for post flight & engine run analysis.
SUMMARY OF PRESENT INVENTION
The present invention, therefore, is directed to Memory Module for Data Acquisition Unit
(DAU) of Flight Data Recorder (FDR).
An aspect of the present invention is the ability of communication module of storing
10GB of data or 10 hours of flight data information.
A further aspect of the invention is the universal application of the present memory
module to any Data Acquisition Unit (DAU). All aircraft parameter signals may be assigned to
any of the multiple data acquisition system inputs under CPU control. Further, the memory
module is responsive to CPU control to select the multiple sectors of flash memory. Briefly,
according to the invention, memory module for an aircraft flight data recorder is responsive to a
central processor unit (CPU) for selectively storing of flight data after digital conversion.
Further memory module is having Flash memory device and has a CPLD, which
provides the glue logic required to interface the multiplexed data and address lines of the flash
device to the processor. The DAU Memory module is designed around the Ultra NAND flash
memory. It supports up to 1G Byte of memory storage.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the present invention become more apparent and
descriptive in the description when considered together with figures/flow charts presented:
Figure 1: is a Block Diagram of Memory Module of DAU of FDR
Figure 2: is a Block Diagram of Micro Controller Interface with Flash Memory in
Memory Module
DETAILED DESCRIPTION
The DAU Memory Module is designed around the Ultra NAND flash memory. It supports
up to 1G Byte of memory storage. A CPLD is used to interface the Flash Memory devices to the
processor. The block diagram of DAU memory card is shown in Figure-1.
The heart of the module is NAND Flash Memory of 1GB storage space. A total of 10
chips is used to realize 10GB of memory. The major building blocks of the card are:
• NAND Flash memory
• CPLD
FLASH Memory:
Flash Chip is used as the Flash memory. The Flash memory has 256MB memory. The
Flash memory is interfaced to the CPLD as shown in Figure-2.
The Flash Chips has addresses multiplexed into 8 Input/Output’s (I/O’s). Command,
address and data are all written through I/O's by bringing write enable signal (WE) to low while
Chip enable (CE) is low which is latched on the rising edge of WE. Command Latch Enable
(CLE) and Address Latch Enable (ALE) are used to multiplex command and address
respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset
Command, Status Read Command, etc require just one cycle bus. Some other commands, like
page read and block erase and page program, require two cycles: one cycle for setup and the
other cycle for execution.
The 256M byte (X8 device) physical space requires 30(X8) addresses, thereby requiring
five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order.
Page Read and Page Program need the same five address cycles following the required
command input. In Block Erase operation, however, only the three row address cycles are used.
Device operations are selected by writing specific commands into the command register.
Interface Requirements:
The following signals are terminated on the PCB edge connector:
1. Sixteen Address lines
1. Sixteen Data lines
2. Read signal from the Processor
3. Write signal from the Processor
4. Board select signal
5. Power Supply Lines (+5V, +3V3 and Ground)
Mechanical Requirements:
1. The Module size is 180mm X 120 mm.
2. The PCB edge connector is of 59-pin male connector with 90° bent pins.
3. One test connector of 40 pins
4. The Module is having provision for mounting Wedge locks.

WE CLAIMS:-
Accordingly, the description of the present invention is to be considered as illustrative only and is for the purpose of teaching those skilled in the art of the best mode of carrying out the invention. The details may be varied substantially without departing from the spirit of the invention, and exclusive use of all modifications which are within the scope of the appended claims is reserved. The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. Memory Module for DAU responsive to a central processor unit (CPU) for storing digitized aircraft data. A dedicated microprocessor/micro controller takes care of all the local I/O activities. Said memory module comprising:
Flash Memory for used to supports up to 1G Byte of memory storage; CPLD provides the glue logic required to interface the multiplexed data and address lines of the flash device to the processor; and Bus Buffer is used for interfacing the control signals , address and data lines from the processor to memory module;

2. Memory Module for DAU of claim 1 wherein module is used to realize 10GB of memory with 10 chips of 1GB each.

3. Memory Module of claim 2 wherein Flash memory of chip of memory module is replaceable in case of problem in any chip.

4. Memory Module of claim 1 wherein CPLD provides the glue logic required to interface the multiplexed data and address lines of the flash device to the processor.

5. Memory Module of claim 4 wherein CPLD generates addresses for Flash Chips, multiplexed into 8 Input/Output’s (I/O’s). Command, address and data are all written through I/O's by bringing write enable signal (WE) to low while Chip enable (CE) is low which is latched on the rising edge of WE. Command Latch Enable (CLE) and Address Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins.

6. Memory Module of claim 5 wherein reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.

7. Memory Module as claimed in any of the proceeding claims wherein Page Read and Page Program need the five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. ,TagSPECI:As per Annexure-II