1. A semiconductor device, comprising:
a drift layer disposed on a substrate, wherein the drift layer comprises a non-planar surface comprising a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device, and wherein each of the repeating features has dopant concentration higher than a remainder of the drift layer.
2. The device as claimed in claim 1, comprising a non-planar well region disposed conformally along a portion of the non-planar surface of the drift layer.
3. The device as claimed in claim 2, wherein a height of each of the plurality of repeating features is less than or equal to approximately 10% of a thickness of the drift layer.
4. The device as claimed in claim 2, comprising a non-planar source contact disposed conformally over at least a portion of the non-planar well region.
5. The device as claimed in claim 2, comprising a second non-planar well region disposed conformally along a second portion of the non-planar surface of the drift layer, and comprising a non-planar drain contact disposed conformally over at least a portion of the second non-planar well region.
6. The device as claimed in claim 2, r comprising a non-planar dielectric layer disposed conformally over at least a portion of the drift layer and a portion of the well region and a non-planar gate disposed conformally over at least a portion of the non-planar dielectric layer.

7. The device as claimed in claim 1, wherein the drift layer comprises a silicon carbide (SiC) drift layer.
8. The device as claimed in claim 1, wherein the repeating features comprise repeating triangular peak features.
9. The device as claimed in claim 8, wherein the repeating triangular peak features provide an increase in a width of the channel equal to approximately 2a/b, wherein a is a length of a side of the repeating triangular peak features, and wherein b is a length of a base of the repeating triangular peak features or a pitch of the repeating triangular peak features.
10. The device as claimed in claim 1, wherein the repeating features comprise repeating rectangular or trapezoidal peak features.
11. The device as claimed in claim 10, wherein the repeating rectangular peak features provide an increase in a width of the channel region equal to approximately (2a+b)/b, wherein a is a height of the repeating rectangular peak features, and wherein b is a pitch of the repeating rectangular peak features.
12. The device as claimed in claim 1, wherein the dopant concentration in the repeating features is less than or equal to approximately twice a critical charge of the drift layer divided by a width of the repeating features.
13. The device as claimed in claim 1, wherein the semiconductor device is a cellular semiconductor device having a triangular, square, or honeycomb cellular design.
14. A method of manufacturing a semiconductor device, the method comprising:

forming an epitaxial semiconductor layer having a non-planar surface, wherein the non-planar surface comprises a plurality of repeating triangular, rectangular, or rounded features having a higher doping than a remainder of the epitaxial semiconductor layer;
forming a non-planar well region from at least a portion of the non-planar surface of the epitaxial semiconductor layer; and
forming a non-planar n+ or p+ region from at least a portion of the non-planar well region.
15. The method as claimed in claim 15, comprising:
depositing a non-planar dielectric layer conformally over at least a portion of the epitaxial semiconductor layer; and
depositing a non-planar gate conformally over at least a portion of the non-planar dielectric layer.
16. The method as claimed in claim 14, wherein forming the epitaxial semiconductor layer having the non-planar surface comprises using sloped resist mask techniques, gray scale lithographic techniques, or combinations thereof.
17. The method as claimed in claim 14, wherein forming the epitaxial semiconductor layer comprises forming the repeating triangular, rectangular, or rounded features with a dopant concentration less than or equal to approximately twice a critical charge of the epitaxial semiconductor layer divided by a width of the repeating triangular, rectangular, or rounded features.
18. The method as claimed in claim 14, wherein forming the epitaxial semiconductor layer, forming the non-planar well region, and forming the non-planar n+ or p+ region each comprise using ion implantation to alter a dopant concentration in a respective portion of the epitaxial semiconductor layer.
19. A semiconductor device, comprising:

a drift layer having a thickness, wherein the drift layer comprises a non-planar surface having a plurality of trench features extending a depth into the drift layer, and wherein the depth is less than or equal to approximately 10% of the thickness of the drift layer;
a non-planar p-well region conformally disposed in at least a portion of the non-planar surface of the drift layer;
a non-planar n+ region conformally disposed in at least a portion of the non-planar p-well region;
a non-planar dielectric layer conformally disposed over at least a portion of the drift layer, a portion of the p-well region, and a portion of the n+ region; and
a non-planar gate conformally disposed over at least a portion of the non-planar dielectric layer.
20. The device as claimed in claim 19, wherein a portion of the drift layer disposed between each of the plurality of trench features has a dopant concentration that is higher than a dopant concentration in a remainder of the drift layer and less than or equal to approximately twice a critical charge of the drift layer divided by a width of the plurality of trench features.
21. The device as claimed in claim 19, wherein the drift layer comprises a silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or germanium (Ge) drift layer.