Field of the Invention:
This present invention relates to driving of Plasma Display Panel (PDP) and particularly relates to a method and an apparatus for driving an alternating current (AC) Plasma display panel (PDP) which leads to improvement of Black Luminance (BL), dark room contrast ratio (DRCR) and reduction of address voltage.
Background of the Invention:
PDP is a flat panel display device which uses plasma, created by inert gas (He + Xe, Ne+Xe, He+Xe+Ne) mixture discharge process, to display character or images, can be divided into millions of pixels which are formed at the intersection of three electrodes namely sustain electrodes, scan electrodes formed on an upper substrate and address electrodes or data electrodes formed on an lower substrate. The PDP with three electrodes driven by an AC voltage is called the AC surface discharge type PDP. The AC surface discharge type PDP has advantages of wide viewing angle, large screen area, high brightness and contrast, low power consumption and excellent image quality which can now exceed the quality of Color Picture Tubes (CPTs) available in the market.
According to discharge physics, when plasma is created in the panel, UV light is emitted. This UV light falls on the Red, Green and Blue phosphors which emit visible light and thereby display images, picture and video.
The PDP electrode has an mxn matrix configuration shown in the FIG.1. The AC
PDP has address electrodes A1 Am in the column direction and Scan
electrodes Y1 Yn and Sustain Electrodes X1 Xn in the row direction.
Each discharge cell of an AC PDP is formed at the junction of three electrodes namely scan electrode Y and sustain electrode X formed on a front substrate and address electrode A formed on a back substrate.
Generally PDP is a System Architecture Digital Matrix Display Design (SADMDD), which consists of embedded electronics integrated with the panel to display the image or moving picture. To produce an image on the panel, standard waveforms are applied to the Scan and Sustain and the address electrodes. Each line of the surface discharge type AC PDP having three electrodes is driven with one frame time by dividing the time into a number of subfields. Each subfield consists of a reset period, an address period and sustain period.
One example of a frame structure for driving PDP is illustrated in FIG.2. Figure 2 shows the display time period of one frame divided into 8 subfields capable of expressing 256(2^8=256) gray levels using 8bit video data corresponding to 8 subfields. One frame time period works out to be16.67ms corresponding to a frame repetition rate of 60 Hz.
Every subfield is divided into a reset period, address period and sustain period. During the reset period the on and off pixels from the previous subfield are converted to the off state with a well-established wall voltage. In addition this period creates sufficient priming to ensure that there is a discharge during the address phase. During the address period, a discharge (between address A-scan Y) is caused in the cells that need to be turned on by the application of the address pulse. The final phase is the Sustain Period during which the cells selected during the address period are turned on by application of sustain pulses thereby causing a surface discharge between X and Y electrodes.
The reset period erases the majority of wall charges accumulated on the dielectric surface during the previous subfield and produces a near-neutral, initial surface condition before the address period. This condition occurs as a result of a continuous weak discharge caused by the ramp waveform. The remaining wall charges on the dielectric surface are required to assist the address discharge.
The reset period is divided into ramp up and ramp down phase. During the ramp up phase, the positive going ramp voltage waveform is applied to create weak discharge at each pixel site. This discharge causes accumulation of wall charges of positive (+) polarity on the address electrode A and the wall charges of negative (-) polarity on the scan electrode Y. A small amount of wall charge of positive polarity (+) accumulates on the sustain electrode X because the sustain electrode is maintained at the ground voltage.
During the ramp down phase, the negative going ramp voltage waveform is applied to the scan electrode to also create a weak discharge at each pixel site. The positive (+) wall charges on the Sustain Electrode (X) are eliminated by the discharge between the sustain electrode X and the scan electrode Y. During this falling ramp period the negative (-) wall charges accumulated on the Scan electrode Y are in part transferred to the sustain electrode X. The ramp down portion of the reset pulse causes weak erase discharge at each discharge cell to erase the excess wall charges from the electrodes Y, X and A, so that the remaining wall charges are uniformly distributed and are capable of producing a stable address discharge during the address phase.
The slopes of the ramp voltages are adjusted to ensure that the plasma in each pixel remains in the positive resistance region so as to provide constant voltage drop across the discharged gas, resulting in a predictable wall voltage state.
During the reset period, the ramp up stage goes up to the high DC voltage ,V reset level and during ramp down period, the ramp down stage goes down to the negative DC voltage (-Vy) and also to the scan reference voltage V scan level.
In address period, negative scanning pulse is sequentially applied to the scan electrode Y and at the same time, positive data pulse is applied to the address electrode A in synchronization with the scanning pulse. The voltage difference between the scan pulse and the data pulse is added to the wall voltage generated in initialization period (i.e. reset period) to produce address discharge within the cells supplied with the data pulse. The scan voltage waveform applied
within the scanning period helps to isolate the one row electrode selected by data pulse from another row electrode. For proper addressing the selective discharge is required to select the correct row electrode during address period.
In the sustain period, the sustaining pulse is alternately applied to the scan electrode Y and the sustain electrode X. then the wall voltage within the cells selected by the address discharge is added to the sustain voltage waveform to cause the sustain discharge in only ON cells which constitute the display discharge giving the main light output between the scan electrode and the sustain electrode. No discharge is occurred within the cells which are in the OFF state.
Finally after the sustain discharge has completed, the above process is repeated for the next subfield until the last subfield after which the next row is scanned. In this fashion the complete PDP matrix is addressed and an image is displayed. The basic problem faced in the prior art due to conventional waveform is that the negative bias voltage applied during ramp down period is low. This results in the requirement of high reset voltage during ramp up phase applied to scan electrode and the consequent increase in switching noise and high cost of electronic devices used in the driving circuit of PDP. In addition, the high value of X Shelf voltage (which is applied to sustain electrode during earlier ramp down period to whole address period) results in high Black Luminance (BL) thereby degrading the Dark Room Contrast Ratio (DRCR). In the conventional waveform, the address voltage is also high (about 70V) and this reduces the life time of expensive Integrated Circuits used in address driver circuit.
In US Patent no. RE37, 444E an apparatus and method for driving a display panel is described in which write operation of the display data by a light emission is executed by carrying out a selective write discharge utilizing a memory function, are adapted to execute a write discharge to all cells and helps to create erase discharge for all cells before selective write discharge. In US Patent no. 7,098, 603 B2 a methods and apparatus for driving a plasma display panel in which a discharge cells are formed to a crossing point of three electrodes X sustain, Y scan and address electrodes includes maintaining the Y scan electrodes lines at a reference level during the reset period and the sustain period ; and addressing the Y scan electrode lines by biasing the Y scan electrode to a first level and simultaneously applying a scan signal to the reference level to Y electrode lines during address period. None of the prior art teachings are able to solve the problem of strong discharge resulting in high Black luminance.
Object of the invention:
It has been already proposed that the conventional waveform used for driving PDPs is characterized by high address voltage, high X Shelf voltage and high reset voltage levels. The X Shelf voltage is applied to sustain electrode starting
from earlier ramp down period and continuing till the completion of the address period. As a result, the Dark room Contrast Ratio (DRCR) is low in conventional driving waveform because of the high background luminance generated within reset period resulting from unwanted strong discharge between scan and sustain electrodes. The high reset voltage applied to scan electrode during ramp up phase results in high switching noise and expensive electronic devices used in driving circuit of PDP.
The principle object of the invention is to provide a new driving waveform for driving PDP which will result in reduction of High reset voltage i.e. V reset from range 300V - 270V to 160-180V and address voltage is reduced by 15V to 20V with respect to conventional applied voltage which is generally applied within range of 60V to 70V during address period resulting in stable selective discharge The reduction is made possible by a combination of higher negative bias voltage i.e. V negative Bias in the range from -40 V to -200V and lower X Shelf Voltage down from Vsus level to about 10-40% lower.
Yet another objective of the present invention is to reduce the Black Luminance (BL) which will result in an increase of the Dark room Contrast Ratio (DRCR) and thereby better picture quality.
STATEMENT OF THE INVENTION:
Accordingly the invention provides a method of driving a surface discharge type Alternating Current Plasma Display panel (PDP) having three electrodes including a discharge cells at the intersection point of the three electrodes, Address, Scan and Sustain electrode by applying driving signals to said electrodes and in order to display information on AC PDP. One frame of image information is divided into a number of subfields and each subfield has reset period, address period and sustain period comprising of producing a weak discharge during reset period by applying highly reduced Xshelf voltage to said sustain electrode and creation of a large volume of wall charges in controlled manner accumulated on the said scan electrode resulting in increase in amplitude of Ramp down as a higher value of negative biased voltage is applied to said scan electrode of reset period. This allows application of low reset voltage to said Scan electrode during ramp up phase of reset period resulting in controlled discharge and decrease in amplitude of Ramp up .Voltage rates of change for ramp up and ramp down exhibit within range of 1.5 V/us to 2.3 V/us and 1.7 V/us to 2.7 V/us respectively, as a result of which weak discharges occur due to application of said voltage levels to said Scan and sustain electrodes leads to low light output within reset period reducing the Black Luminance (BL) i.e. Back ground Luminance during reset period, thus increasing Dark Room Contrast Ratio (DRCR). Also the higher value of negative biased voltage applied to said scan electrode results in accumulation of more wall charges inside the pixel leading to high wall voltage during ramp down phase of reset period and consequent reduction in the address voltage applied during address period. Finally application of sustain voltage to both said scan and
sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in PDP. There is also provided an apparatus for driving the surface discharge type Alternating Current Plasma Display panel (PDP).
Brief descriptions of the Drawings:
The accompanying drawings, which are incorporated in and constitute a part of specification, illustrate an exemplary embodiment of the invention and together with the descriptions, give to explain the principle of the invention.
Fig.1 illustrates a cross section view of the panel used for surface discharge type AC PDP.
Fig.2 illustrates the driving apparatus with electrode arrangements in horizontal and vertical direction of a surface discharge type an AC PDP and discharge cell formation at the crossing point of three electrodes.
Fig.3 illustrates the single frame structure, corresponding number of subfields (SF1-SF8), three division periods and sustain distributions of corresponding subfield used in the PDP driving.
Fig.4 illustrates the conventional driving waveform applied to three electrodes, Y scan, X sustain and A address used in the PDP.
Fig.5 illustrates a waveform showing a driving voltage levels in driving an Ac PDP in accordance with the preferred embodiment of the present invention.
Fig.6 illustrates a waveform diagram for explaining the principle of present invention including all improvements achieved in the panel.
Fig.7 illustrates a part of waveform showing sharp transition in waveform of present invention.
Fig.8 illustrates a graph between the Reset voltages (V reset) and Negative Bias Voltage (V negative).
Fig.9 illustrates a graph between the Black Luminance (BL) and Negative Bias Voltage (V negative).
Fig. 10 illustrates a graph between the Dark Room Contrast Ratio (DRCR) and Negative Bias Voltage (V negative).
Fig. 11 illustrates a graph between the X shelf Voltage (V xshelf) and Negative Bias Voltage (V negative).
Detailed descriptions of the invention with reference to the drawings:
In the following description, the object of this invention is described in according to the accompanying drawings. This invention is capable of modification of various obvious drawbacks of the conventional AC PDP in reference to the following drawings and descriptions.
The driving method of surface discharge type AC PDP according to the present invention will be described in Fig.5 which illustrates the new waveform diagram showing the operative voltage level in driving AC PDP in accordance with the present invention.
Before starting the detailed description of the present invention, it is necessary to discuss the conventional AC PDP for clear understanding of the present invention. Figure 1 illustrates the cross sectional view AC PDP with straight barrier ribs.
As in figure 1, the front glass substrate (1) and back glass substrate (2) are shown. In the front glass substrate (1), display electrodes are made of transparent ITO sheet (3). To reduce the resistance of the display electrode, opaque electrically conducting bus electrodes (4) are made over the ITO electrodes. The display electrode is covered with a transparent dielectric layer (5) to limit the discharge current. Then the electron emissive layer (6) is deposited over the transparent dielectric layer (5). On the back glass substrate (2), a plurality of address electrodes (7) are formed with one address electrode (7) is formed in each sub-pixel. The address electrodes (7) are covered with a dielectric layer (8) to limit the discharge current and for light reflection. The straight channel barrier ribs (9) are formed over the dielectric layer (8). The R (10a), G (10b), B (10c) phosphor layers are formed in the barrier rib (9) channel spaces.
The resolution of SDPDP (standard definition PDP) is illustrated as a example which is 852x480 where 852x3=2556 vertical lines i.e. the address lines(Red, Green and Blue) coming from address driver, 480 horizontal lines coming from scan and sustain driver respectively
Figure 2 illustrates driving apparatus with electrode arrangements in the surface discharge type AC PDP in present invention and in this figure, the discharge cell (11) is formed at the crossing point of three electrodes such as Scan Y, Sustain X and Address A. In other way this discharge cell is called the one sub pixel; one digital pixel consists of three sub pixels i.e. Red, Green and Blue. The AC PDP has a millions of pixels formed in this way. The apparatus for driving AC PDP consists of microcontroller based system architecture design consisting of power supply, video section and three drivers such as scan sustain and address drivers' integration with logic timing controller. First the video section provides the digital bits to the logic controller board which generates all control signals for Scan,
Sustain and Address drivers driving sequentially to Scan, Sustain and Address electrodes. The power supply section provides the different DC voltages to these above mentioned parts of system. The apparatus for driving the display panel comprises driving means for supplying a plurality of driving voltage pulses and control means which controls a sequence of supplying a plurality of driving voltage pulses.
The address driver supplies the data signal in form of voltage which is reduced by 15V to 20V with respect to conventional applied voltage which is generally applied within range of 60V to 70V to address electrodes A1 to Am resulting in stable selective discharge during address period after gamma correction and image processing under control of timing controller.
The scan driver simultaneously applies a ramp up signal waveform rising until a ramp up voltage V reset (e.g. 160-180V) and ramp down signal waveform falling until ground voltage (0V) or to the negative bias voltage -Vy (e.g. -90 to -120V) during reset period to the scan electrodes Y1 to Yn under control of timing controller to initialize the entire screen. Further the scan driver sequentially applies the scanning pulse of scan voltage (e.g. 110V) to scan electrodes falling from ground voltage (0V) to negative scan voltage level -Vy during the address period to select the scan line. Again the scan driver supplies simultaneously the sustain pulses of sustain voltage level V Sus (e.g. 200V) to scan electrodes Y1 to Yn to provide the brightness during the sustain period. Voltage rates of change for ramp up and ramp down exhibit within range of 1.5 V/us to 2.3 V/us and 1.7 V/us to 2.7 V/us respectively.
The sustain Driver applies a Direct current (DC) Voltage that is X shelf voltage, 20-40% lower of the sustain voltage during the ramp down period of reset phase and the address period to Sustain electrodes X1 to Xn under control of timing controller. Further the sustain driver simultaneously applies the sustain pulses of sustain voltage level V Sus(e.g. 200V) to Sustain electrodes X1 to Xn and operates alternatively with the scan driver.
The driving circuits apply voltage waveforms to three electrodes (scanY, sustainX and address A) of PDP using 8 to 12bit binary code coming from the Video board to Logic board for based on the subfield method.
Figure.3 illustrates the frame structure as well as subfield methods used in the AC PDP. This subfield method uses a number of subfields divided from 1 frame (16.67ms) for displaying image. This figure illustrates one frame is divided into 8 subfields SF1-SF8 for 8 bit data. All subfields have assigned luminance level based on the binary code 1(2°), 2(21), 4(22), 8(23), 16(24), 32(25), 64(26), 128(27) in the sustain period for 8bit video data.
Figure 4 illustrates the conventional driving waveform of surface discharge type AC PDP. In this figure, the driving voltage waveforms are applied to the corresponding three electrodes Y scan, X sustain and A address. The driving
scheme includes number of subfields and each subfield introduces three periods such as reset period, address period and sustain period. During one subfield three driving waveforms are applied simultaneously to three electrodes. During the reset period, the scan waveform (Y scan) introduces ramp up and ramp down stage, the ground voltage (0V) is maintained to the sustain electrode(X sustain) up to ramp up stage and the ground voltage is maintained to the address electrode (A address) up to ramp down period. Before starting the ramp down period the sustain voltage or less than sustain voltage is applied to the sustain electrode (X sustain) up to end of the address period, this voltage is called "X shelf Voltage (V x shelf)". During the address period, the negative scan pulse is applied to the scan electrode for scanning the address lines and simultaneously the positive address pulse of address voltage (e.g. 70V) is applied to the address electrode for selecting the particular line. During the Sustain period, the alternating sustaining pulses are applied to the scan and sustain electrode for creating the sustain discharge of selected cells.
In the reset period, reset pulse of ramp up waveform is provided to the scan electrode Y during ramp up phase that rises from scan base voltage level ,Vsus(e.g. 200V) to predetermined reset voltage level ,V reset(e.g. 270V). The reset pulse of ramp up waveform causes ramp up discharge during ramp up phase at the discharge cell in the entire screen. The ramp up discharge serves to build the wall charges on the dielectric surface of three electrodes. The reset pulse of ramp down waveform is provided to the scan electrode Y during ramp down period that goes down from scan base voltage level ,Vsus( e.g. 200V) to negative bias voltage level, -V y( e.g. -40V).The reset pulse of ramp down waveform causes ramp down discharge i.e. weak erasure discharge at each of the discharge cell to erase a portion of the wall charges from the electrode Y, X and A respectively excessively formed and simultaneously serve to build the same surface condition means the wall charge formation to the respectively three electrodes uniformly enough to cause stable address discharge to select the cell.
The pulse of X shelf voltage waveform is applied to the Sustain electrode X starting from earlier ramp down period to the end of address period that rises from ground potential (0V) to the sustain voltage or less than sustain voltage say V xshelf (e.g. 185V).This voltage waveform introduces the sharp transition that controls the strong light emission during the reset period.
In the address period, the negative pulse of scanning voltage waveform Vscan (e.g. 80V) is applied to the scan electrodes Y and simultaneously the positive pulse of address voltage V add (e.g.70V) is applied to the address electrodes A The resultant voltage is added to the wall voltage generated ramp down discharge to cause the stable address discharge for selecting the cells.
In sustain period, the alternating pulses of sustain voltage waveform are applied to the scan Y and sustain X electrode. The sustain voltage of V sus (e.g.200V) is
added to the wall voltage produced in the address discharge enough to create the strong sustain discharge i.e. surface discharge between the scan Y and sustain X electrode. This discharge produces the main light output i.e.dispaly Luminance from the selected ON cells.
The conventional driving waveform of AC PDP of figure 4 has some drawbacks based on the performance of panel. These are high Black Luminance which leads to low Dark Room Contrast Ratio (DRCR) and high address voltage V add (e.g.70V). The picture quality in the Black Condition (grey level "0" at no load condition) is not good as strong light output is obtained in the black condition. This strong light output comes mainly from strong reset discharge in reset period. In this waveform the Scan base voltage Vsus (e.g.200V) and very high X shelf Voltage, V xshelf (e.g. 185V) is applied. Before starting the Ramp down period, the strong discharge takes place between the Scan Y and Sustain X electrode due to high X shelf Voltage level and produces the strong light output which degrades the picture quality in the black condition so that the dark room contrast is reduced. The wall voltage generated during the ramp down period is low, so high address voltage (V add) is needed i.e. 70V for addressing.
Figure 5 illustrates the modified driving voltage waveform diagram showing the new voltage level in the different stage of driving waveform in accordance with present invention. The voltage levels in the driving waveform mainly remove the above drawbacks in the conventional driving waveform. In the new driving waveform, the main changes are voltage levels at the X shelf stage and also at reset stage. In present waveform the X shelf voltage, V Xshelf (e.g. 150V), 20-40% lower of sustain voltage level V sus instead of conventional (e.g.185V) and also the simultaneous change of Negative Bias Voltage, -Vy (e.g. -120V) instead of conventional (e.g. -40V) are applied to the sustain and scan electrodes during reset and address period. Due to above changes of voltage levels, the reset voltage are automatically reduced (e.g. 180V or less) in the full sustaining condition in the panel. The Black Luminance (BL) in the grey level "0" is greatly reduced from earlier level of 0.81cd/m2 to 0.02cd/m2 and more particular to 0.18cd/m2 in the entire screen resulting in improvement of picture quality in the black condition which leads to higher Dark Room Contrast Ratio (DRCR)(e.g. from earlier 600 to 24000). According to present invention another advantage in the panel performance is reduction of address voltage, address voltage is reduced by 15V to 20V with respect to conventional applied voltage which is generally applied within range of 60V to 70V(e.g. 45Vto 55V from earlier 60V-70V) resulting in stable selective discharge during full firing condition in the panel.
Figure 6 illustrates the potential difference of two waveforms applied to two electrodes Y scan and X sustain of AC PDP respectively. Here Y-X (12) represents, the potential difference between the two waveforms Y scan and X sustain applied to corresponding scan and sustain electrodes, this resultant waveform creates the discharge between Y scan and X sustain electrodes and
associated with the address voltage waveform applied to the address electrode during individual subfield. In this waveform the main changes reflected are the sharp transition of lower amplitude due to lower X shelf voltage before starting the ramp down period. After this stage the voltage during ramp down phase went down to -VY (e.g. -270V i.e. X shelf Voltage 150V + Negative Biased Voltage 120V).This X shelf transition during reset period results in earlier ramp down phase controlling the strong discharge between Y scan and X sustain. As a result weak discharge takes place resulting in small light output during reset period so that the black luminance is reduced to a great extent. The dark room contrast is also increased as luminance in the black condition is reduced.
In figure 6, the positive pulse of sustain voltage (13) shows waveform of V sus =200V and the Negative pulse of sustain voltage (14) shows waveform of V sus= 200V alternately. This resultant waveform of Y and X electrodes during sustain period creates the sustain discharge with the help of wall voltage produced during the address period and the main light output i.e. the actual luminance is generated from selected ON cells.
Figure 7 represents the reset period of the Y - X waveform. In this figure, the sharp transition (16) due to X shelf voltage, V xshelf controls the luminance during reset period. Here the symbol "V" indicates the change of voltage from ground level to X shelf voltage level i.e. the voltage difference between the sustain voltage, V sus and X shelf voltage, V xshelf (e.g. AV=V sus -V xshelf=200V-150V=50V )in the new waveform instead of earlier AV(e.g. AV=V sus -V xshelf=200V-185V=15V). The lower value of X shelf Voltage level limits the strong discharge between Y scan and X sustain before starting of ramp down period as X shelf Voltage of new driving waveform is 150V as compare to earlier 185V. To maintain the weak discharge during reset period the discharge voltage condition should be maintained i.e. the voltage difference between the scan Y and sustain X during the reset period plus wall voltage, V wall should be less than the breakdown voltage between scan Y and sustain X. So the weak discharge is so controlled to reduce the black luminance (BL). Before starting of ramp down period in conventional waveform the voltage difference between Y scan and X sustain with high wall voltage due to high reset voltage within the ramp up phase (e.g. 15V +reset 270V) is so greater than the voltage difference between Y scan and X sustain with low wall voltage due to low reset voltage within the ramp up period (e.g. 50V+reset 180V) in modified waveform. So this low resultant voltage waveform does not exceed the breakdown voltage of Y and X resulting weak discharge to create low light output during reset period. But previously, the voltage difference along with high wall voltage exceeds the breakdown voltage of X and Y, resulting in strong discharge before starting of ramp down period. This strong discharge creates the background light within this phase increasing the black luminance.
In the figure 7, ramp rate (15) of ramp up phase and ramp rate (17) of ramp down phase also control the sustaining and firing of panel. In present invention ramp
rate of ramp up phase is 1.5 V/us to 2.3 V/us and more preferably within range of 1.6 V/us to 1.9 V/us and ramp rate of ramp down phase within range of 1.7 V/us to 2.7 V/us and more preferably within range of 2.1 V/us to 2.3 V/us as compare to about 2.7 V/us and about 1.7V/us respectively in conventional waveform.
In the new driving waveform of present invention, due to higher value of negative biased voltage, V negative (e.g. -Vy=120V), reset voltage (e.g. V reset=270V) is decreased at great extent to reset voltage (e.g. V reset=180V). The reduction of reset voltage V reset results in reduction of high voltage switching noise and use of cheap electronics components in the circuit.
In present invention, address voltage is reduced by 15V to 20V with respect to conventional applied voltage which is generally applied within range of 60V to 70V during address period resulting in stable selective discharge at full firing condition of panel. The address voltage V address (V breakdown - V wall) decreases as V wall increases due to high negative voltage applied to the ramp down period with low X shelf voltage level applied during ramp down and whole address period. The V breakdown is the inert gas break down voltage between Y scan and A address for facing discharge. The wall voltage is increasing resulting in decrease of address voltage.
Figure 8 illustrates the graph of Reset Voltage, V reset versus Negative Voltage, V negative. In this graph, the variation of reset voltage with various negative voltage (-40V to -200V) are observed at the proper sustaining condition with corresponding fixed value of x shelf Voltage. The inventors have taken five variations of the reset voltage with negative biased voltage in five fixed values of x shelf voltage (185V to 140V) for demonstration.
Figure 9 represents the graph of Black Luminance (BL) Versus Negative Voltage, V negative .In this graph, by varying negative Voltage; the different values of Black Luminance are obtained. The inventors have taken five black luminance variations with corresponding five X shelf voltage. The inventors selected the V xshelf in range of (140V to 160V), more particularly in range of (150V to 155V) and negative voltages V negative in range of (-40V to -200V), more particularly in range of (-105V to -120V) in the experiment and observed black luminance is low with in above mentioned ranges.
Figure 10 represents the graph of Dark Room Contrast Ratio (DRCR) versus Negative voltage. The inventors observed values of DRCR with respect to negative voltage. The inventors found that when V xshelf lies in range of (140V to 160V), more particularly in range of (150V - 155V) and negative voltages V negative in range of (-40V to -200V), more particularly in range of (-105V to -120V) higher values of DRCR up to 24000 is obtained.
Figure 11 represents the graph between X shelf voltage and Negative voltage. In this graph, two optimized values (18) are shown. For Example the inventors
selected points in this graph whereas V xshelf is 150V and 155V and V negative is -105V and -120V and setting these values in the waveform, the reset voltage is automatically reduced to with in range 170V-180V-190V and the address voltage is also reduced to 50V- 52V-55V.
The present invention reduce black luminance as well as address voltage by achieving the proper voltage levels during reset phase and also the ramp rates of reset control in the driving waveform. This invention covers the all modifications and provides the high performance improvements such as high contrast.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in limiting sense .Various modifications of the disclosed embodiments, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined.

We claim:
1. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) having three electrodes including a discharge cells at the
intersection point of the three electrodes, Address, Scan and Sustain electrode
by applying driving signals to said electrodes and in order to display information
on AC PDP, one frame of image information is divided into a number of subfields
and each subfield has reset period, address period and sustain period,
comprising
Production of weak discharge during reset period by applying highly reduced Xshelf voltage to said sustain electrode
Applying low reset voltage to said Scan electrode during ramp up phase of reset period resulting in controlled discharge and decrease in amplitude of Ramp up,
large volume of wall charges in controlled manner accumulated on the said scan electrode resulting in increase in amplitude of Ramp down as a higher value of negative biased voltage is applied to said scan electrode during ramp down phase of reset period,
Voltage rates of change for ramp up and ramp down exhibit within range of 1.5 V/us to 2.3 V/us and 1.7 V/us to 2.7 V/us respectively, results in
weak discharges occur due to application of said voltage levels to said Scan and sustain electrodes leads to low light output within reset period reducing the Black Luminance (BL) i.e. Back ground Luminance during reset period, thus increasing Dark Room Contrast Ratio (DRCR),
a higher value of negative biased voltage is applied to said scan electrode resulting in accumulation of more wall charges on the said scan electrodes leads to high wall voltage during ramp down phase of reset period,
said wall voltage reduces the address voltage applied during address period to enable the stable selective discharge on said discharge cells , applying sustain voltage to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in PDP.
2. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein, said Xshelf voltage is
reduced within range of 10% to 40% of sustain voltage applied and more
preferably within range of 20% to 40% of sustain voltage to said sustain
electrode for providing sharp transition resulting in weak discharge during reset
period.
3. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein, said reset voltage is applied
within range of 155V to 270V and more preferably within range of 170V to 190V
to said Scan electrode during ramp up phase of reset period resulting in
controlled discharge and decrease in amplitude of Ramp up.
4. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein, said negative biased voltage
is applied with in range of -40V to -200V and more preferably within range of -
90V to -120V to said Scan electrode during ramp down phase of reset period
generating large volume of wall charges in controlled manner accumulated on
the said scan electrode resulting in increase in amplitude of Ramp down.
5. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein, said voltage change of rates
for ramp up and ramp down exhibit more preferably within range of 1.6 V/us to
1.9 V/us and 2.1 V/us to 2.3 V/us respectively.
6. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein, said Black Luminance (BL)
or back ground Luminance is reduced to 0.02 cd/m2 to 0.18 cd/m2 in the entire
screen.
7. A method of driving a surface discharge type Alternating Current Plasma
Display panel (PDP) as claimed in claim 1, wherein said address voltage is
reduced by 15V to 20V with respect to conventional applied voltage which is
generally applied within range of 60V to 70V during address period resulting in
stable selective discharge
8. A Driving apparatus of plasma display panel comprising:
a driving circuit applying to the plasma display,
logic controller which controls the driving voltage pulses to sustain, scan and address electrodes
sustain driver applying highly reduced Xshelf voltage to sustain electrode, results in production of weak discharge during reset period
scan driver applying low reset voltage to Scan electrode during ramp up phase of reset period resulting in controlled discharge and decrease in amplitude of Ramp up ,
scan driver applying a higher value of negative biased voltage during ramp down phase of reset period to scan electrode resulting in large volume of wall charges in controlled manner accumulated on the said scan electrode results in increase in amplitude of Ramp down
Voltage rates of change for ramp up and ramp down exhibit within range of 1.5 V/us to 2.3 V/us and 1.7 V/us to 2.7 V/us respectively, results in
weak discharges occur due to application of said voltage levels to said Scan and sustain electrodes leads to low light output reducing the Black Luminance (BL) i.e. Back ground Luminance during reset period, thus increasing Dark Room Contrast Ratio (DRCR),
a higher value of negative biased voltage is applied through scan driver to said scan electrode resulting in accumulation of more wall charges on the said scan electrodes leads to high wall voltage during ramp down phase of reset period,
said wall voltage reduces the address voltage applied through address driver during address period to enable the stable selective discharge on said discharge cells ,
sustain voltage is applied through both scan and sustain driver to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in PDP.
9. The apparatus as claimed in claim 8, wherein, said Xshelf voltage is reduced
within range of 10% to 40% of sustain voltage applied and more preferably within
range of 20% to 40% of sustain voltage to said sustain electrode for providing
sharp transition resulting in weak discharge during reset period.
10. The apparatus as claimed in claim 8, wherein, said reset voltage is applied
within range of 155V to 270V and more preferably within range of 170V to 190V
to said Scan electrode during ramp up phase of reset period resulting in
controlled discharge and decrease in amplitude of Ramp up.
11. The apparatus as claimed in claim 8, wherein, said negative biased voltage is
applied with in range of -40V to -200V and more preferably within range of -90V
to -120V to said Scan electrode during ramp down phase of reset period of
generating large volume of wall charges in controlled manner accumulated on
the said scan electrode resulting in increase in amplitude of Ramp down.

12. The apparatus as claimed in claim 8, wherein, said voltage change rates for
ramp up and ramp down exhibit more preferably within range of 1.6 V/us to 1.9
V/us and 2.1 V/us to 2.3 V/us respectively.
13. The apparatus as claimed in claim 8, wherein, said Black Luminance (BL) or
back ground Luminance is reduced to 0.02 cd/m2 to 0.18 cd/m2 in the entire
screen.
14. The apparatus as claimed in claim 8, wherein, wherein said address voltage
is reduced by 15V to 20V with respect to conventional applied voltage which is
generally applied within range of 60V to 70V during address period resulting in stable selective discharge
15. A method of driving and an apparatus for driving a surface discharge type Alternating Current Plasma Display panel (PDP) substantially herein described with reference to the accompanying drawings.