DESC:
TECHNICAL FIELD
[0001] The present disclosure relates to magnetic recording systems, and more particularly to methods and system/apparatus for interpolative timing recovery for two-dimensional magnetic recording system.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] In order to sustain continued growth in capacity of hard disk drives, significant efforts have been put on storage techniques like Heat-Assisted Magnetic Recording (HAMR) and Bit-Patterned Media (BPM). The major drawbacks of these techniques lie in the need for radical changes to conventional media. Keeping these drawbacks in mind, few existing implementations discuss the feasibility of ultra-high storage densities approaching 10 Tb/in2 on conventional media, and propose to achieve this using shingled writing and two-dimensional readback. Two-dimensional readback involves using a class of generic multi-dimensional communication theoretic algorithms to retrieve data in a reliable manner. The two-dimensional magnetic recording (TDMR) scheme/system is a purely signal processing and systems based technology to enable ultra-high storage densities. However, TDMR channels come with a price of 2-D Inter Symbol Interference (ISI) and noise, and therefore signal processing becomes significantly more complex in comparison to that of traditional 1-D recording, which calls for novel multi-dimensional signal processing techniques for each of the corresponding processes associated with 1-D storage channels. Timing recovery is one such necessary process in TDMR systems. While several state of the art solutions exist for 1-D magnetic recording systems and the field fairly well developed, solutions for the TDMR paradigm are still emerging.
[0004] The theoretical estimate for the limit of areal bit-density in magnetic recording systems is around 20 Tb/in2 at room temperatures, wherein beyond this limit, signal-to-noise ratio (SNR) degradation is too high for reliable recovery of information bits using classical algorithms. Existing perpendicular magnetic recording (PMR) systems are found to saturate at areal densities close to 1Tb/in2 showing that there is still potential for improvement in bit densities in magnetic recording systems. Sustainable growth in storage systems is not achievable without seeking newer, superior technologies that are capable of helping us reach the theoretical barriers determined by physical laws. The TDMR paradigm proposed in an existing solution offer boost of areal densities up to 2 Tb/in2, in which the solution/technology uses a shingled write process to store data and retrieve. A full blown TDMR requires a 2D read/write process for retrieval of the data. This 2D read process comprises the same communication theoretic processes associated with 1D magnetic recording channels, but involves more complex and generic multi-dimensional algorithms for reliably retrieving data.
[0005] Therefore, in sum, although timing recovery problem is well studied and fairly well-established for 1D magnetic recording systems, no solutions address the timing recovery problem in TDMR systems, which is significantly more complex as this involves the design of an algorithm that takes in to account potentially non-separable nature of the channel, and severe ISI effects from cross tracks and down tracks during the read process.
[0006] In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[0007] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0008] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[0009] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all Marcus groups used in the appended claims.

OBJECTS OF THE INVENTION
[0010] It is a general object of the present disclosure to provide methods and system/apparatus for interpolative timing recovery for two-dimensional magnetic recording system.
[0011] It is another object of the present disclosure to provide an apparatus for enhancing read performance in a two-dimensional magnetic recording (TDMR) system.
[0012] It is yet another object of the present disclosure to provide a method for enhancing read performance in a two-dimensional magnetic recording (TDMR) system.

SUMMARY
[0013] The present disclosure relates to magnetic recording systems, and more particularly to methods and system/apparatus for interpolative timing recovery for two-dimensional magnetic recording system.
[0014] Embodiments of the present disclosure provide an efficient, effective, reliable, improved device and method. The system/apparatus and method that enables for interpolative timing recovery for two-dimensional magnetic recording system.
[0015] Accordingly, an aspect of the present disclosure relates to an apparatus for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements by timing recovery. The apparatus can include a filter unit, a timing error detector, and a timing recovery mechanism. The filter unit can filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate. The timing error detector can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for the aforesaid filtered sample estimates. The timing error detector can include a timing recovery mechanism for scanning the said grid defining the said plurality of read elements for enhancing read performance in the TDMR system, and wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.
[0016] In an aspect, one or more oversampled signals can be generated from one or more read back signals, the one or more read back signals are obtained using at least one read head, and wherein said at least one read head comprise one or more analog to digital converters (ADCs). from one or more read back signals, the one or more read back signals are obtained using at least one read head, and wherein said at least one read head comprise one or more analog to digital converters (ADCs).
[0017] In an aspect, one or more read back signals can be generated when said at least one read head moves along one or more tracks of said at least one TDMR storage medium sensing magnetic polarities and producing said one or more read back signals.
[0018] In an aspect, filter unit can be an interpolation filter, wherein the number of samples used for filtering corresponds to the order of the interpolation filter.
[0019] In an aspect, filter unit can include one or more decision estimates.
[0020] In an aspect, the oversampled signals can include a fractional part and an integer part.
[0021] In an aspect, timing error estimates can be computed using the Mueller and Muller (M&M) timing error detector (TED).
[0022] In an aspect, the offsets can incldue at least of fractional portions and integer portions.
[0023] In an aspect, the apparatus can include a phase locked loop (PLL) update unit to calculate offsets associated with said timing error estimates. In another aspect, the phase locked loop (PLL) update unit can include electronic oscillators, loop filters, and one or more shift registers to store integral gain components and said timing error estimates across the direction of traversal.
[0024] An aspect of the present disclosure relates to a method for enhancing read performance in a two-dimensional magnetic recording (TDMR) system including a grid defining a plurality of read elements by timing recovery. The method includes the steps of: an apparatus that can filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate; the apparatus can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate; and the apparatus can scan said grid defining said plurality of read elements to compute said timing error estimates, wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.
[0025] The grid defines a plurality of read elements. For simplicity, only recording word/address lines are shown in the diagram. There may be a separate set of lines for reading the information and parallel data recording and retrieval (readout). The information from a horizontal layer may be recorded and retrieved with one shot in case of an implementation of a memory with non moving parts. By “one shot,” it is meant that the information from the entire surface/layer would be recorded and retrieved simultaneously or in parallel due to the grid implementation as shown above. In contrast, if a recording write/read head flying over the medium at some finite separation, similar to the head/media design in the conventional magnetic hard drive, used, the information may be recorded and retrieved sequentially or in a “bit”-by-“bit” order (e.g., the recording head may write and read information sequentially from each bit cell across the entire thickness). The grid may be similar to grids used in semiconductor RAM, such as, for example, magnetoresistive RAM, with an exception that the information is recorded and retrieved from the grid itself. In the latter case, the grid is equivalent to one magnetic layer.
[0026] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing FIG.s in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0028] In the figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0029] FIG. 1 illustrates a channel response for TDMR system (Gaussian channel response model), as available in the prior-art.
[0030] FIG. 2 illustrates an exemplary architecture of the phase locked loop (PLL) based timing recovery, as available in the prior-art.
[0031] FIG. 3 illustrates a conventional interpolative timing recovery system, as available in the prior-art.
[0032] FIG. 4 illustrates exemplary interpolation of desired samples from the sampled readback signal, in accordance with an embodiment of the present invention.
[0033] FIG. 5 illustrates an exemplary Traversal over the 2D sampled readback signal, wherein the timing estimates are provided along the x and y directions are computed simultaneously, in accordance with an embodiment of the present invention.
[0034] FIG. 6 illustrates a block diagram of a filter module (traversal unit for a 2D grid) to calculate row/column and position offsets for the next iteration according to the method of grid traversal discussed earlier, in accordance with an embodiment of the present invention.
[0035] FIG. 7 illustrates an exemplary implementation of a fraction computation or computing module of a proposed system, in accordance with an embodiment of the present invention.
[0036] FIG. 8 illustrates an exemplary Filter bank containing the stack of optimal filters for varying values of Mx, My, in accordance with an embodiment of the present invention.
[0037] FIG. 9 illustrates an exemplary implementation of the multiply and accumulate unit computes the estimate of the final interpolated value, in accordance with an embodiment of the present invention.
[0038] FIG. 10 illustrates an exemplary implementation of an M&M TED module for calculation of error estimate along a direction of traversal, in accordance with an embodiment of the present invention.
[0039] FIG. 11 illustrates an exemplary implementation of M&M TED across for error estimatation across the direction of traversal is calculated, in accordance with an embodiment of the present invention.
[0040] FIG. 12 illustrates two sets of shift registers that store values of decision estimates along the rows and columns, in accordance with an embodiment of the present invention.
[0041] FIG. 13 illustrates two sets of shift registers that store the values of the decision estimates along the row, in accordance with an embodiment of the present invention.
[0042] FIG. 14 illustrates an exemplary implementation of VCO and two loop filters for calculating the value of the timing estimates, in accordance with an embodiment of the present invention.
[0043] FIG. 15 illustrates two sets of shift registers store the values of the integral gains along the rows and columns, in accordance with an embodiment of the present invention
[0044] FIG. 16 illustrates two sets of shift registers store the values of the timing estimates along the rows and columns, SR(k) refers to the Kth register, in accordance with an embodiment of the present invention.
[0045] FIGs. 17 A-C illustrates a simulation result of a proposed system for error tracking performance (samples along the diagonals), in accordance with an embodiment of the present invention.
[0046] FIG. 18 illustrates a graph representing derived plot of MSE, in accordance with an embodiment of the present invention.
[0047] FIG. 19 illustrates exemplary functional modules of a proposed appartus, in accordance with an embodiment of the present disclosure.
[0048] FIG. 20 illustrate an exemplary flow diagram of the proposed apparatus, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0049] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0050] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.
[0051] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[0052] Timing Recovery is an important stage in receiver process of a communication system that facilitates detection and decoding of read back signals using sophisticated signal processing and coding algorithms. Several mixed signal phase-locked-loop (PLL) based circuits have been proposed, and are used in receivers to accomplish timing recovery. Storage channels are special communication channels that impose a high demand on the level of reliability. The present invention proposes a complete digital implementation of a timing recovery scheme based on an interpolation filter approach for two-dimensional magnetic recording (TDMR) systems. Magnetic recording channels vary slowly with time due to wear and tear, temperature variations, and read fly height variations among other factors. The channel response is taken into account to arrive at an optimal strategy to derive necessary interpolation filter, wherein the proposed technology can be modified by changing channel response appropriately for optical recording systems. A hardware prototype for non- separable targets can be synthesized and tested on a field-programmable-gate-array (FPGA) and simulated using read-back signals modelled taking practical considerations into account. The induced timing errors are compared to estimated timing offsets to quantify the veracity of the architecture.
[0053] In an aspect, an exemplary hardware prototype has been demonstrated for a 64×64 bit sequence, whose design is a fixed-point implementation and is tested using a simulated read-back signal and results are shown to prove convergence of theoretical results with fixed-point implementation. The proposed design is believed to be the first architectural solution to timing recovery problem in TDMR systems.
[0054] The proposed invention addresses synchronization problem in TDMR systems, wherein it would be appreciated that although the proposed system is designed keeping TDMR systems in mind, the same can be extended to other storage systems such as optical channels where timing recovery in the communication theoretic perspective plays a vital role.
[0055] In an aspect, the present invention uses algorithms that help build a prototype of a timing recovery architecture targeted at TDMR systems, wherein the proposed design is also optimized for balanced throughput, power and area requirements. In an exemplary implementation, hardware prototype for non-separable targets has been synthesized and tested for Virtex-7 FPGA using Xilinx VC707 Evaluation Platform.
[0056] In an aspect, in magnetic and optical storage media, information bits to be stored are written on specified tracks, wherein a read back signal is generated as the read head moves along the tracks sensing the magnetic polarities and producing a corresponding electronic signal. Each track is further divided into sectors of fixed sizes. In practical situations, one cannot assume that statistical properties of media/storage channel are same across all tracks or sectors. The underlying storage channel properties vary slowly across the media. These non-stationary properties need to be taken into account for accurate information retrieval, and as a result, several components in the read-back process need to tune themselves at regular intervals. To facilitate this re-tuning, a known data-sequence called the preamble is provided at the beginning of every sector, wherein several system components like the timing and equalization use the preamble to tune their parameters, prior to reading the information bits. During the read process, every bit suffers from inter-symbol interference (ISI) from the surrounding bits along the same track. ISI from bits in surrounding tracks, called inter-track interference (ITI), is minimized by providing guard bands between two consecutive tracks. In present technologies, around 10% of write space is dedicated to the preamble.
[0057] In 1D magnetic recording, the effects of ITI are not considered since these effects are minimal, whereas in two dimensional magnetic recording (TDMR) systems, these effects play a much more significant role. The proposed hardware implementation of this invention offers a synchronization scheme for TDMR systems, although, as mentioned earlier, the same can be extended to other relevant storage paradigms after making appropriate changes to the filter structures. Furthermore, a separable PLL can also be implemented using the proposed architecture/invention along the down-track and cross-track directions.
[0058] Traditional timing recovery systems in 1D read channel architectures are based on PLLs that consists of an analog to digital converter (ADC), a timing error detector (TED), a loop filter (LF), and a voltage controlled oscillator (VCO), wherein output of the VCO serves as the clock to the ADC. Decision directed timing recovery schemes involve using a detector to provide decision estimates to TED in order to compute phase error estimates. This detector is usually a low latency preliminary detector. PLL based timing recovery systems need a dynamic clock adjustment system that varies the baud rate clock according to the estimated timing offsets. This makes expensive analog circuitry necessary to vary the clock frequency.
[0059] Complete digital timing recovery schemes involve oversampling the read back signal to obtain optimal samples for usage in the subsequent detection scheme. The interpolation stage must be optimized to make the timing recovery scheme practical by reducing the oversampling rate and making it feasible for implementation by present VLSI technologies. The present invention proposes a hardware implementation of such an ITR scheme that is modified for the needs of TDMR.
[0060] In an aspect, an apparatus for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements by timing recovery. The apparatus can include a filter unit, a timing error detector, and a timing recovery mechanism. The filter unit can filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate. The timing error detector can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate. The the timing error detector can include a timing recovery mechanism for scanning the said grid defining the said plurality of read elements for enhancing read performance in the TDMR system, and wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.
Channel Model and Readback Signal Model
[0061] Channel response for TDMR systems, as shown in FIG. 1, can be modelled as a 2-D Gaussian function

where a is the amplitude, and represent the pulse width along the x and y directions respectively. The readback signal can be modelled as a convolution of the written data and the channel response in (1).

[0062] where, represent the symbol rates along x and y directions. The respective timing errors are represented by and The binary NRZ data stored on the storage media is given by dk. The amplitude noise, n(t) is assumed to be normally distributed over the 2-D grid. FIG. 1 illustrates a channel response for TDMR system (Gaussian channel response model), as available in the prior-art.
Timing Error Model
[0063] Timing errors in the 2-D case are modelled as phase, frequency and jitter errors along the and directions. Phase errors in 2-D occur due to positional offsets of the read head along a two-dimensional grid. Frequency errors occur due to variations in velocity along the x and y directions. In addition to phase and frequency errors, there is a jitter component as well. The model can be represented as

where,

[0064] The phase offsets are represented by the scalars in A, while the frequency offsets along both directions are represented by the components of B. The non-diagonal values of B reflect the non-separable nature of the model due to frequency errors. For negligible values of the non-diagonal elements, the read- back signal described in (2) becomes separable and 1-D equalization and detection schemes can be used separately along the two directions.
Timing Recovery and PLL based techniques
[0065] The read-back signal has timing errors induced along the and directions. On sampling the read-back signal at baud-rate, the below is obtained

represents the coordinates of the data samples. The first term in (4) represent the data bit. The second term represents the 2D ISI that needs to be mitigated by the equalizer. The third term is the electronic noise associated with the read-back process respectively. The sample is clearly distorted by the presence of timing errors.
[0066] FIG. 2 illustrates an exemplary architecture of the phase locked loop (PLL) based timing recovery, as available in the prior-art. A PLL-based timing recovery scheme attempts to correct the induced errors by producing accurate timing estimates, . These estimates are generated based on the previously processed read-back signal samples. The corrected sample is given by

It is assumed here that an ideal 2-D signal detector is available, which provides the correct decisions prior to the read-back process. The proposed invention uses a 2-D timing error detector (TED) to provide estimates of the timing offsets along both directions. The TED receives feedback from the detector and generates timing error components ex and ey given by


The errors are then processed by a PLL update module comprising of a combination of a 2-D voltage controlled oscillator (VCO) and a loop filter (LF). The PLL update equations are given by

where, Kx (px)and Kx (py)are the proportional scaling factors for ex and ey. Kx (ix) and Kx (iy)are integral scaling constants for ex along the x and y directions. K(ix)y and Ky(iy)are integral scaling constants for ex along the x and y directions. Timing estimates obtained in (8) and (9) converge with the induced timing errors in (3).

Proposed Interpolative Timing Recovery
[0067] FIG. 3 illustrates a conventional interpolative timing recovery system, as available in the prior-art. With reference to FIG. 3 showing an existing interpolative timing recovery, it is to be appreciated that PLL-based scheme requires an analog-to-digital converter (ADC) with an adjustable sampling clock in order to correctly sample at appropriate points. The problem is amplified in case of TDMR systems since in addition to this kind of an ADC along the direction, there is also a need of a feedback mechanism to control the servo to offset errors along the direction. To bypass these issues, a complete interpolation-based scheme was proposed using low-pass sinc interpolation filter.
[0068] FIGs. 1-3 illustrate the prior art scheme, wherein although the PLL is part of the scheme, an interpolator is used to find the estimate of the desired sampling point. FIG. 4 shows the schematic of the 2-D interpolation concept. Upon oversampling the read-back signal along the and directions, following is obtained:


are the oversampling periods along the x and y directions.
Using samples obtained in (10), an estimate is detemined. The sampling instants can be recasted as

and represent the integer and fractional parts of the desired sampling instant. The estimate of can computed using 2-D fractional interpolation as

It has been seen that estimates of necessary received samples can be obtained by
(13)
, wherein the optimal filter can be computed by minimizing following MSE cost function
(14)
Gradient of this cost function can be equated to zero to derive optimal interpolation filter for a given value of .The optimal filter obtained using this derivation can be expressed as (15)
Proposed Architecture of 2D Interpolative Timing Recovery
[0069] This section proposed a generic architecture for 2D interpolation based timing recovery, wherein the proposed 2D timing recovery scheme offers flexibility of parallelizing several points of computation. A carefully pipelined architecture can offer higher throughputs than the simplistic translation of 1D timing recovery techniques. This higher throughput comes at the cost of higher power and area requirements. It is therefore imperative to choose the optimal scheme for 2D interpolative timing recovery so as to produce a high-throughput, low-power and low-area design.
O(n2) and O(n) Algorithms for Timing Recovery
[0070] Each point of computation on a 2D grid represents the point where the 2D readback signal needs to be sampled. This yields a single sample as output for detection. Furthermore, the computations at each point on the grid can be pipelined into three stages as follows:
[0071] Filtering stage- This is the stage when oversampled signals are obtained and filtered through an appropriate interpolation filter. The fractional and integer parts and respectively are the inputs to this stage, while the filtered sample estimate, is the output from this stage. The number of samples used for filtering corresponds to the order of the interpolation filter. This is the most power intensive stage in the design owing to a large number of calculations. This makes it necessary to optimize the quantization levels and the filter orders to make the filter as power efficient as possible.
[0072] Timing error detection-This stage computes the timing error estimate obtained using the M&M TED. The sample estimate, and the decision estimate are the inputs to this stage, while, the error estimates, along the and directions are the outputs of this stage.
[0073] PLL update-This stage is responsible for computing the value of the fractional unit, and the integer unit. The error estimates, along the and directions are the inputs and the fractional and integer portions are the outputs of this stage.
[0074] These stages do not have interdependencies that lead to latency changes in each stage. As a result, each stage executes its operations in 1 clock cycle. It is to be noted that usage of an ideal detector enables the timing error detection stage to execute itself in 1 cycle. However, extra latency would be necessary when the preliminary sequence detector has its own latency. Assuming that the preliminary sequence detector has a latency of ‘N’ cycles, the M&M TED needs N cycles to produce corresponding timing error estimates. This also necessitates the corresponding latency to be associated with the PLL update block. It is important to note that this additional latency in the PLL update unit has destabilizing effects on the timing recovery system and need to be factored in while deciding the proportional and integral gains.
[0075] Keeping the above features in mind, three architectures for the timing recovery scheme are proposed.
[0076] First Architecture: Timing recovery by spanning the 2D grid along each row:
[0077] This is a simple and exhaustive approach where timing error estimates are computed over the entire grid such that cycles are taken to span the entire grid. This method uses the least area since the same individual micro-architectural units can be used every cycle. The major drawback using this approach is the reduced throughput where every sector takes a minimum of cycles to be read back. Due to this minimal necessity in the number of components, this is also the most power efficient design. This scheme is mainly used as a reference to evaluate the efficacy of the next two schemes.
[0078] Second Architecture: Timing recovery by scanning the 2D grid simultaneously along the row and the column:
[0079] FIG. 5 illustrates an exemplary traversal over the 2D sampled readback signal, wherein the timing estimates are provided along the x and y directions are computed simultaneously, in accordance with an embodiment of the present invention. The timing estimates are computed simultaneously along the both the directions. Since the diagonal forms the starting point for every new set of computations, this architecture takes, cycles to cover the entire sized grid. This yields approximately twice the throughput as the previous architecture, for large sector sizes. This architecture uses twice the amount of area as compared to the previous method due to the requirement of twice the number of computational units. The power requirement of this architecture is expected to be the same as the previous architecture for large sector sizes. This is due to the lower number of cycles that the design needs to function despite the higher number of micro-architectural units functioning at a given point in time.
[0080] Third Architecture: Timing recovery by scanning multiple rows and multiple columns simultaneously: This scheme needs cycles to compute the timing estimates over an grid. This is done by starting off the next row’s/column’s filtering, TED and PLL update, while the previous row/column has finished processing its very first sample. However, it is estimated that this scheme would need times the area when compared to the first scheme. The power requirement of this architecture is expected to be times the power requirements of the first scheme.
[0081] Keeping these factors in mind, the second architecture is chosen for its efficacy in terms of throughput, area and power requirements.
Architecture for Timing Recovery
[0082] Filter: The filter module performs fraction computation and fractional interpolation to obtain the sample estimates. It also consists of a RAM block which contains the oversampled signals and decision estimates needed for the interpolation and timing error detection procedure. Two such units operate in parallel along the x and y directions. FIG. 6 illustrates a block diagram of a filter module (traversal unit for a 2D grid) to calculate row/column and position offsets for the next iteration according to the method of grid traversal discussed earlier, in accordance with an embodiment of the present invention.
[0083] Since a RAM block is used for storing the pre-computed filter coefficients, an extra latency of one clock cycle has to be taken into account. This block (as shown in FIG. 6) calculates the row/column and position offsets for the next iteration according to the method of grid traversal discussed earlier.
[0084] FIG. 7 illustrates an exemplary implementation of a fraction computation or computing module of a proposed system, in accordance with an embodiment of the present invention. As shown in FIG. 7 the values of and are computed. These computations serve to choose appropriate filters for the fractional interpolation. The values and serve as 7-bit addresses to a shared memory which is discussed later. Also, note that and serve as signals that interface the domain to the T domain. A straightforward implementation of this component would result in a very complex module whose multipliers and dividers would consume a significant amount of power. The architecture shown in FIG. 7 is a power efficient design that constrains the oversampling ratios to a particular form T/Ts= 1+2-n. This is not a major drawback as long as this ratio is above the necessary threshold for recoverable interpolation. This threshold is determined by empirical studies. The ratio is fixed to 1.125 for the exemplary implementation sake of the present invention.
[0085] Filter Bank: The order of the filter depends on the oversampling ratio. For a ratio of 1.125, a filter used are of order 8×8, with each filter coefficient quantized to 15 bits. The 2D array is converted to a vector form (stacking up the last column, then the penultimate one and so on) and the coefficients are then stored in a RAM. The values and are concatenated to form a single address bus that is used to access the filter bank RAM. The number of filters in the RAM depends on the quantization used for the fractional part. In this case (25×25 = 1024) filters are needed for the (-1: -5) long and . FIG. 8 illustrates an exemplary implementation of a single address bus formation that is used to access the filter bank RAM, in accordance with an embodiment of the present invention.
[0086] Shared Memory: The oversampled signals (sampled at Ts) along with decision estimates are stored in the RAM block. In the proposed algorithm, there are two clock domains -Ts and T. It is critical that metastability issues are avoided in the propsoed design. Keeping in mind this requirement, the interfacing between the two domains are avoiced by using a shared memory between the twoIt may be appreciated that, the parameters form the interface between the two domains,Ts and T. In addition to these, the sampled signal is another interface between the -Ts and Tdomains. By separating them out using a dual port memory, the metastability issues are avoided. It is to be noted that this memory is readily available in the FPGA as an IP- core. The memory is used to interface the two clock domains. The write addressing scheme is a simple scheme populating the 2D grid according to the sampled readback signal. It is assumed that a 64x64 grid size. The integer part is an output from the fraction computation unit and hence a signal from the T domain. The address indicating the location of the sample in the 2D grid is however, a signal from the Ts domain. In addition, in this implementation, the writes to the shared memory are completed prior to the reading. This allows us to reduce the complexities at the start of the operation of the circuit by avoiding possibilities of read-outs before or during the write process. It is to be noted that this scheme emulates the batch processing feature that is common to the ITR scheme in magnetic recording systems. In ASIC designs, reading and writing to and from the same address at the same time needs to be avoided.
[0087] Multiply Accumulate:This block performs the filtering operation. It needs sixty four multipliers, one 64 input adder and two register banks each 64 units wide with parallel load. These numbers depend on the order of the filter. The complexity of the architecture increases with increasing orders. High oversampling rates will need filters of lower orders. However, the price of analog ADC constrains the oversampling ratios. Since this module contains power intensive components like multipliers, this is the largest power consuming block in the design. The complexity of computation also means that this block puts a constraint on the maximum clock frequency that can be used. FIG. 9 illustrates an exemplary implementation of the multiply and accumulate unit computes the estimate of the final interpolated value, in accordance with an embodiment of the present invention
M&M TED
[0088] The MM TED module consists of two TED blocks that calculate the timing error along and across the direction of traversal. FIG. 10 illustrates an exemplary implementation of an M&M TED module for calculation of error estimate along a direction of traversal, in accordance with an embodiment of the present invention. For the row component, the rext and dextvalues are obtained from the shift registers for the column and vice versa. It also consists of a chain of shift registers to store the decision and sample estimates for the ‘across’ computation. Two such units operate in parallel along the and directions.
[0089] M&M TED Along: This module requires 2 multipliers, an adder/subtracter along with a (2.1) multiplexer and registers to store the previous values of the decision and sample estimates. For the points along the grid diagonal, the previous estimates for the row component are obtained from the shift registers of the column component and vice versa. In case of row component, this module calculates . For the column component, this calculates .
[0090] M&M TED Across: FIG. 11 illustrate an exemplary implementation of M&M TED across for error estimatation across the direction of traversal is calculated, in accordance with an embodiment of the present invention. This is a simple module which requires two multipliers and an adder/subtracter as shown in FIG. 11. In case of row component, this module calculates . For the column component, this calculates
[0091] Shift Registers (Decision and Sample Estimates): This module consists of a chain of registers with width equal to the size of the grid. The registers store the values of the decision and sample estimates. Since the length of the iterations reduces with increments in row/column position, an (n:1) multiplexer controlled by column/row signals manages the effective width of the shift register chain. FIG. 12 illustrates two sets of shift registers that store values of decision estimates along the rows and columns, in accordance with an embodiment of the present invention. FIG. 13 illustrates two sets of shift registers that store the values of the decision estimates along the row, in accordance with an embodiment of the present invention.
[0092] PLL Update: The PLL update module consists of two identical sub-modules to calculate the x and y offsets of the timing estimate. It also consists of two different types of shift register chains to store the integral gain components and timing estimates respectively. The shift registers essentially store the integral gain component and timing estimate values across the direction of traversal. Two such units operate in parallel along the x and y directions. The PLL update is a combination of a digital VCO and two loop filters. The loop filter is a first order loop filter to enable tracking of frequency offsets along x and y directions. This module thus consists of two 2-DPLL’s. for the row component is obtained from the shift registers of the row component and likewise for the column component. is fed back to the respective shift registers. for the row component are obtained from the shift registers of the row component and likewise for the column component. are fed back to the respective shift registers. For the points along the grid diagonal , the values of the sum of integral gains for the row component are obtained from the shift registers of the column component and vice versa. Two such modules are required to compute x and y components of the timing estimate. FIG. 14 illustrates an exemplary implementation of VCO and two loop filters for calculating the value of the timing estimates, in accordance with an embodiment of the present invention.
[0093] Shift Registers (Integral Gain): This module consists of a chain of registers with width equal to the size of the grid. The registers store the values of the sum of integral gains for ex and ey. Since the length of the iterations reduces with increments in row/column position, a (n:1) multiplexer ( n being the size of the grid, 64) controlled by column/row signals manages the effective width of the shift register chain. At each clock cycle, this module feeds the values of integral gains for the particular position on the grid. The updated values of the integral gains are fed back during the next clock cycle. FIG. 15 illustrates two sets of shift registers store the values of the integral gains along the rows and columns, in accordance with an embodiment of the present invention
[0094] Shift Registers (Timing Estimate): This module consists of a chain of registers with width equal to the size of the grid. The registers store the values of the timing estimates. Since the length of the iterations reduces with increments in row/column position, n (2:1 ) multiplexers controlled by column/row signals manages the effective width of the shift register chain. Since there is a latency of two clock cycles between the filter and the PLL update block along with an extra cycle due to the usage of a RAM for the filter bank, the output of the (n-3)th register ( ) is fed back to the filter module thereby completing the loop. At each clock cycle, this module feeds the values of timing estimates for the particular position on the grid. The updated values of the timing estimates are fed back during the next clock cycle. FIG. 16 illustrates two sets of shift registers store the values of the timing estimates along the rows and columns, SR(k) refers to the Kth register, in accordance with an embodiment of the present invention.
Experiments:
[0095] Error Tracking performance: FIGs. 17 A-C illustrates a simulation result of a proposed system for error tracking performance (samples along the diagonals), in accordance with an embodiment of the present invention.
[0096] The proposed ITR algorithm was simulated on a 2D readback signal generated from a grid of size 500*500, wherein parameters used to generate the readback signal are a=1, =0.5, and =0.5. P = [0.2,0.3]T represents 20% and 30% phase errors along the x and y directions respectively. The model is non-separable withB ¬= [0.01, 0.005, 0.01 0.005]. The jitter parameters are modelled using two Gaussian random variables Also, amplitude noise is modelled by . A 2-D filter of order 8*8 is used and filter coefficients are pre-random variables?calculated and store in memory. FIG. 18 illustrates a graph representing derived plot of MSE, in accordance with an embodiment of the present invention.
[0097] Filter modules (operating in parallel) that consist of a large number of multipliers and adders consumes the maximum amount of power. The rest of the components are not as power intensive. This further justifies using the second scheme over the third in algorithm for timing recovery since the increase in power by a factor of the sector size would drastically increase the power requirements.

[0098] Toanalyze the gains made by increasing the filter order and thereby deciding on the optimal order, a metric is defined as:

where n corresponds to a filter of the order n*n. Fig. 18 shows the empirically derived plot of MSE. There is significant gain when the order is increased from to n=2 to n=3. This data point distorts the overall figure and hence are excluded from the plot. It may be observe that increasing the order beyond 8 does not result in any significant drop in MSE.
[0099] In an aspect, the present invention focuses on a 2D timing recovery architecture based on interpolative timing recovery. The present invention further provides a 2D timing recovery architecture based on MMSE optimal timing recovery.
[00100] FIG. 19 illustrates exemplary functional modules of a proposed apparatus, in accordance with an embodiment of the present disclosure. As shown in FIG. 19, the apparatus can include a filter unit 1902, a timing error detector 1906, M&M TED 1908 and a timing recovery mechanism 1910.
[00101] In an embodiment, the filter unit 1902 can filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate. In another embodiment, the filter unit 1902 can include an interplotion filter 1904.
[00102] In an embodiment, the timing error detector 1906 can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate. In another embodiment, the timing error detector 1906 can include Mueller and Muller (M&M) timing error detector (TED) 1908 and timing recovery mechanism 1910. Timing error estimates can be computed using Mueller and Muller (M&M) timing error detector (TED) 1908.
[00103] In an embodiment, the timing error detector 1906 can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate. The the timing error detector 1906 can include a timing recovery mechanism 1910 for scanning said grid defining said plurality of read elements for enhancing read performance in the TDMR system, and wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.
[00104] In an embodiment, timing error estimates can be computed using Mueller and Muller (M&M) timing error detector (TED) 1908.
[00105] FIG. 20 illustrate an exemplary flow diagram of the proposed appartus, in accordance with an embodiment of the present disclosure.
[00106] At step 2002, an apparatus can filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate.
[00107] At step 2004, the apparatus can detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate.
[00108] At step 2006, the apparatus can scan said grid defining said plurality of read elements to compute said timing error estimates, wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.
[00109] The described systems and techniques can be implemented in electronic circuitry, computer hardware, firmware, software, or in combinations of them, such as the structural means disclosed in this specification and structural equivalents thereof. This can include at least one computer-readable medium embodying a program operable to cause one or more data processing apparatus (e.g., a signal processing device including a programmable hardware processor) to perform operations in support of the systems and devices, or simulations thereof for use in design of such systems and devices. Moreover, method implementations can be realized from a disclosed system, apparatus or device, and system, apparatus or device implementations can be realized from a disclosed method.
[00110] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refers to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[00111] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
,CLAIMS:
1. An apparatus 1900 for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements, by timing recovery, said appratus comprising:
a filter unit 1902 to filter one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate;
a timing error detector 1906 to detect timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate; wherein the timing error detector 1906 includes a timing recovery mechanism 1910 for scanning the said grid defining said plurality of read elements for enhancing read performance in the TDMR system, and wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.

2. The apparatus 1900 as claimed in claim 1, wherein said one or more oversampled signals are generated from one or more read back signals, the one or more read back signals are obtained using at least one read head, and wherein said at least one read head comprise one or more analog to digital converters (ADCs).

3. The apparatus 1900 as claimed in claim 2, wherein said one or more read back signals are generated when said at least one read head moves along one or more tracks of said at least one TDMR storage medium sensing magnetic polarities and producing said one or more read back signals.

4. The apparatus 1900 as claimed in claim 1, wherein said filter unit is an interpolation filter 1904, wherein the number of samples used for filtering corresponds to the order of the interpolation filter.

5. The apparatus 1900 as claimed in claim 1, wherein said filter unit 1902 comprises one or more decision estimates.

6. The apparatus 1900 as claimed in claim 1, wherein each of said one or more oversampled signals compirse a fractional part and an integer part.
7. The apparatus 1900 as claimed in claim 1, wherein said timing error estimates is computed using Mueller and Muller (M&M) timing error detector (TED) 1908.

8. The apparatus 1900 as claimed in claim 1, wherein said timing error detector 1906 compute said timing error estimates along and across the direction of traversal of the TDMR system.

9. The apparatus 1900 as claimed in claim 1, wherein said offsets comprise at least of fractional portions and integer portions.

10. The apparatus 1900 as claimed in claim 1, wherein said apparatus comprises a phase locked loop (PLL) update unit to calculate offsets associated with said timing error estimates, the phase locked loop (PLL) update unit includes electronic oscillators, loop filters, and one or more shift registers to store integral gain components and said timing error estimates across the direction of traversal.

11. A method for enhancing read performance in a two-dimensional magnetic recording (TDMR) system, including a grid defining a plurality of read elements, by timing recovery, said method comprising:
filtering 2002, at an apparatus 1900, one or more oversampled signals obtained from the TDMR system to generate at least one filtered sample having at least a filtered sample estimate;
detecting 2004, at said apparatus 1900, timing error for said filtered sample estimate and compute timing error estimates and decision estimates for said filtered sample estimate; and
scanning 2006, at said apparatus 1900, to compute said timing error estimates, said grid defining said plurality of read elements for enhancing read performance in the TDMR system, wherein the scanning is performed along each row of said grid or simultaneously along single row and single column of said grid or multiple rows and multiple columns simultaneously of said grid.