Field of the Invention
The present invention provides a low power content addressable memory system by restricting search to valid entries.
Background of the Invention
High densities CAMs (Content Addressable Memory) are most widely used for IP lookup /packet classifications operations in routers. The CAM circuits consume a good amount of power during lookup operations.
Figure 1 shows the search operation for a conventional high density CAM. For example, if the size of memory is M words for each of N bits and number of match lines is M then all the M match lines are precharged to vdd-vt through PRCH_ signal. In the worst case, if there is no data match or a hit condition; all the match lines would discharge. If average discharge current through one match line is Imatch worst case discharge current is M x Imatch , which takes a heavy toll on the power consumption of the content addressable memory circuit , wherein the searching each data word takes into account searching through individual CAM cell. However, if a status of validity or invalidity is set for a given word then charging and discharging process can be avoided for the invalid words in the memory cell.
Thus, a need is felt for a high-density content addressable memory circuit array, which would charge/discharge only for the valid word match lines.
Object and Summary of the Invention
To obviate the aforesaid drawbacks the object of the instant invention is to provide a low power content addressable memory by restricting the search only for valid entries.
Another object of the invention is to avoid precharging during the subsequent lookups as discharging of match lines for invalid entries during search operation is not required.
To achieve the aforementioned objectives the present invention provides a low power content addressable memory system comprising:
- an array of content addressable memory cells organized as a plurality of equal sized cam cell groups, each cam cell group having one or more cam cells;
- a valid entry tag bit associated with each said content addressable memory cell;
- a match output generator connected to the output of each cam cell; and
- an enabling means having its first input connected to the valid entry tag bit, its second input connected to a match control signal and its output connected to the corresponding match output generator such that said match output generator is enabled only if said valid entry tag bit indicates a valid entry.
This is accomplished by testing the validity of each cam cell and thereby testing the validity of the entire data word.
Brief Description of The Accompanying Drawings
The invention will now be described with reference to the accompanying drawings
Figure 1 shows a conventional content addressable memory cell.
Figure 2 illustrates a low power content addressable memory cell in accordance with the present invention.
Figure 3 illustrates the waveforms at different nodes of the content addressable memory in accordance with the present invention.
Detailed Description of the Invention
Figure 2 shows a CAM cell storing a tag bit with each word. If this bit is set, it indicates that the word is a valid entry else it is not a valid entry. The valid bit is logically ANDED with PRCH_ signal by using the logic and gate AND, to thereby enable the bit match operation and is then applied at the gates of the PMOS Mp and NMOS Mn. For a given word, if the valid bit is set then only match line evaluation of that particular word is of any significance. However, if the valid bit is assigned a zero value or it is not set, then the match lines for all the words in the cam cell array will always remain precharged, that eventually saves power by avoiding invalid charging and discharging of the match lines.
For a given CAM size of M words, if M/2 entries are the only valid entries then search operation is performed only for these entries and thus it results in low power consumption content addressable memory cell array.
The valid bit is also logically ANDED with match line sense amplifier output, wherein the match line sense amplifier is cascade structure of two logic inverters. If both the valid bit and the sense amplifier output are set then MATCHOUT, which is the output of the sense amplifier and will be set for indicating a hit, that would otherwise indicate an invalid entry.
Thus, it is clearly evident from the description of the matching circuitry undergoing a logic enablement operation through the circuitry provided by the logic and gates in the CAM circuits provided by the present invention.
Figure 3 shows the waveforms at different nodes of the content addressable memory cell shown in figure 2, during precharge and evaluation phase of valid and not a valid entry. It shows the logic level of PRCH, valid bit, PRCHV and match line during the precharge and evaluation phase, which clearly depicts that the match and mismatch mode operations are enabled for the valid bit being set to a logic high value.

We Claim:
1. A low power content addressable memory system, comprising:
a. an array of content addressable memory cells organized as a plurality of equal
sized cam cell groups, each cam cell group having one or more cam cells;
b. a valid entry tag bit associated with each said content addressable memory
cell;
c. a match output generator connected to the output of each cam cell; and
d. an enabling means having its first input connected to the valid entry tag bit, its
second input connected to a match control signal and its output connected to
the corresponding match output generator such that said match output
generator is enabled only if said valid entry tag bit indicates a valid entry.
2. A low power content addressable memory system as claimed in claim 1, wherein said
cam cell comprising:
a. a transistorized circuit for data storage; and
b. a connecting means coupled to the output of said transistorized circuit for
generating a match or mismatch status output.
3. A low power content addressable memory system as claimed in claim 1 and 2,
wherein said match output generator comprising:
a a match line connected to first terminal of said connecting means;
b. a first charging means connected to second terminal of said connecting means;
and
c. a second charging means connected to said match line for controlling charge
sharing between said match control signal and match line.
4. A low power content addressable memory system as claimed in claim 1, wherein said
enabling means comprising:
a. a first logic gate connected to said match control signal at its first input and to
the valid entry tag bit;
b. at least two logic inverters cascaded to each other and receiving a signal from
said match output generator for generating a match or mismatch status; and

. c. a second logic gate connected to the valid entry tag bit at its first input and connected to the output of said logic inverters for generating match or mismatch output.
5. A low power content addressable memory system as claimed in claim 4, wherein said first and second logic gate is a logic and gate.
6. A low power content addressable memory system as claimed in claim 2, wherein said connecting means is a transistor.
7. A low power content addressable memory system as claimed in claim 3, wherein said first charging means is a transistor.
8. A low power content addressable memory system as claimed in claim 3, wherein said second charging means comprising:
a. a first transistor coupled to said match line at its input and connected to a
higher voltage supply at its control terminal; and
b. a second transistor coupled at its input to a higher voltage supply and coupled
to the output of said first transistor and receiving the output from said enabling
means at its control terminal.
9. A method of providing low power content addressable memory system comprising
steps of:
a connecting a plurality of equal sized cam cell groups to form an array of content addressable memory cells;
b. connecting a match output generator to the output of each cam cell; and
c. providing a match control signal at the first input of an enabling means and
providing a valid tag bit at the second input of said enabling means for
generating the output corresponding to match output generator, the output
being derived on setting of the valid bit.
10. A low power content addressable memory substantially as herein described with reference to and as illustrated by the accompanying drawings.