Description:TECHNICAL FIELD
[0001] The present disclosure relates, in general, to packet networks, and more specifically, relates to a method and apparatus for precision time protocol slave synchronization in nanosecond order.

BACKGROUND
[0002] An example of such a system is recited in a Patent US9270395B2 titled "Method for robust precision time protocol (PTP) synchronization with default 1588V2 profile". The methods relate to reducing sync time in a PTP network include receiving, by a first PTP slave port of a first network device, timing messages from a second PTP master port of a second network device. The methods include maintaining a PTP master clock based on timing information included in the timing messages received from the second network device via the first PTP port. However, in this existing system, phase offsets calculated at the slave are filtered out using different methods and phase offset adjustments on the slave clock are also done via a different method.
[0003] Another example is recited in a patent CN104883235A titled “Clock time synchronization precision improving method based on PTP protocol. The patent proposes an invention that belongs to the technical field of time synchronization. To solve the problem that the time deviation of a slave clock in a PTP domain leads to the synchronous time of a downstream slave clock of the slave clock deviates, the invention provides a clock time synchronization precision-improving method based on a PTP protocol. However, in the system, phase offsets calculated at the slave are filtered out using different methods and phase offset adjustments on the slave clock are also done via a different method.
[0004] The various causes of the resultant bad clock at slave have been explained above, of which are most critical are phase offset and network delay. Therefore, it is desired to overcome the drawbacks, shortcomings, and limitations associated with existing solutions, and develop a clock servo module and clock synthesizer modules that are implemented to tackle the phase offset and network delay issues.
OBJECTS OF THE PRESENT DISCLOSURE
[0005] An object of the present disclosure relates, in general, to packet networks, and more specifically, relates to a method and apparatus for precision time protocol slave synchronization in nanosecond order.
[0006] Another object of the present disclosure is to provide an apparatus having a clock servo module and clock synthesizer modules that are implemented to tackle the phase offset and network delay issues.
[0007] Yet another object of the present disclosure is to provide an apparatus that adjusts the slave clock in PTP protocol to achieve nanosecond accuracy, up to 200 nanoseconds, at the slave clock

SUMMARY
[0008] The present disclosure relates in general, to packet networks, and more specifically, relates to a method and apparatus for precision time protocol slave synchronization in nanosecond order. The main objective of the present disclosure is to overcome the drawback, limitations, and shortcomings of the existing structure and solution, by providing hardware-based clock servo and synthesis modules that are implemented to tackle the phase offset and network delay issues.
[0009] The present disclosure relates to PTP slave clock synchronization as the ultimate convergence point in any PTP clock distribution domain. PTP slave synchronization is still in the fuzzy domain, as it involves physical characteristics of the clock like frequency and phase drift and complex network dynamics in terms of network congestion, packet switching and network latency asymmetry. Slave clock methods that involve clock servo and clock synthesizers need to adjust themselves issues mentioned above.
[0010] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent components.

BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The following drawings form part of the present specification and are included to further illustrate aspects of the present disclosure. The disclosure may be better understood by reference to the drawings in combination with the detailed description of the specific embodiments presented herein.
[0012] FIG. 1 illustrates an exemplary schematic view of PTP slave implementation, in accordance with an embodiment of the present disclosure.
[0013] FIG. 2 illustrates an exemplary schematic view of standard test set up, in accordance with an embodiment of the present disclosure.
[0014] FIG. 3 illustrates an exemplary schematic view of accuracy causes, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0015] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. If the specification states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[0016] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0017] The present disclosure relates, in general, to packet networks, and more specifically, relates to a method and apparatus for precision time protocol slave synchronization in nanosecond order.
[0018] The advantages achieved by the apparatus of the present disclosure can be clear from the embodiments provided herein. The apparatus has clock servo module and clock synthesizer modules that are implemented to tackle the phase offset and network delay issues. The apparatus adjusts the slave clock in the PTP protocol to achieve nanosecond accuracy, up to 200 nanoseconds, at the slave clock. The description of terms and features related to the present disclosure shall be clear from the embodiments that are illustrated and described; however, the invention is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents of the embodiments are possible within the scope of the present disclosure. Additionally, the invention can include other embodiments that are within the scope of the claims but are not described in detail with respect to the following description.
[0019] FIG. 1 illustrates an exemplary schematic view of PTP slave implementation, in accordance with an embodiment of the present disclosure.
[0020] Referring to FIG. 1, the integrated system 100 is disclosed, the system 100 can include field programmable gate arrays (FPGA) 102 with a SOC and a Rubidium oscillator 104, clock synthesizer module 106, time stamp unit 108, cyclic redundancy check (CRC) calculator 110, ethernet port 112, processor 114, time conversion unit 116, nanosecond counter generator 118, second counter (120-1, 120-2) and ethernet engine 122.
[0021] The oscillator 104 generates PTP packets of the first predefined frequency which are converted to the second predefined frequency. The first predefined frequency is converted to the second predefined frequency using the phase linked loop (PLL) of the FPGA 102, where the first predefined frequency is 10MHz and the second predefined frequency is 250MHZ. The clock synthesizer module 106 is configured in the FPGA and coupled to the oscillator to derive the PTP packets of the second predefined frequency to calculate the difference in the timing for a period of time and sends the corrected value to the oscillator. The clock synthesizer module 106 generates a pulse per second (PPS) that measures the slave accuracy with the PTP master.
[0022] The rubidium oscillator 104 generates 10MHz which is then converted to 250MHZ using the PLL of the FPGA 102. The code takes 250MHz as input and it keeps track of the 250MHz clock. The clock synthesizer module 106 then calculates the difference in the timing for a period of time and then it sends the corrected value to the oscillator 104 through the universal asynchronous receiver-transmitter (UART) port and the oscillator changes its frequency as per the correction and then this is repeated till the clock starts producing the correct frequency. The clock correction then keeps track of the frequency variation of the oscillator 104 due to temperature, vibration and ageing of the oscillator 104. This is how the frequency of the clock synthesizer is corrected for higher accuracy.
[0023] When the PTP Ethernet packet arrives, the arriving timestamps are performed at FPGA 102 by the time synthesizer module 106. The packet is then stored and processed by the SOC where time is extracted from the packets. While sending the delay request packet, the packet is then sent to the FPGA 102, where the time synthesizer module timestamps the packet before the packet is sent out of the hardware.
[0024] The clock synthesizer module 106 receives the timestamps from PTP packets T1, T2, T3 and T4 and then it’s calculating the time difference between the PTP master and the slave, the clock synthesizer then corrects the slave time with this time difference. In this way, the clock synthesizer module 106 does the time correction. The phase offset corrections are sent to the hardware that comprises the seconds counter (120-1, 120-2) and nanoseconds counter 118.
[0025] The PTP protocol makes the slave clock always trail behind the master clock, wherein the sync packet time stamp observable is copied to the slave seconds counter and network latency calculated between the master and slave clock is copied into the nanoseconds counter 118. The time stamp observable is transferred from the hardware to processor 114, wherein the time observables are stored in memory and the calculation of the delay and phase offset is performed in processor 114.
[0026] The apparatus 100 filters the phase offsets by cross-validating the time of arrival to be calculated within the same second and abnormal deviations from the median value, as calculated for every fixed number of phase offset observations
[0027] The clock synthesizer module 106 receives the time stamps T1,T2,T3,T4, and calculates the time difference between the master and client and then these corrections are then used to correct the client’s time and follow the time stamping with respect to the new corrected time.
[0028] Moreover, the clock synthesizer 106 also generates a 1PPS pulse. This 1 PPS pulse can be used to measure the slave accuracy with the PTP master or the GNSS 1PPS time. The implementation is done in such a way that the shift in 1PPS is not greater than a fixed value in order to save the system from larger fluctuations in time, the remaining and additional corrections are done slowly in subsequent 1PPS pulses. Further, the apparatus clock servo module and the clock synthesizer modules are implemented to tackle the phase offset and network delay issues.
[0029] FIG. 2 illustrates an exemplary schematic view of the standard test set-up 200, in accordance with an embodiment of the present disclosure.
[0030] System 100 includes a clock servo module and clock synthesizer modules that are
implemented to tackle the phase offset and network delay issues.
[0031] Clock Servo Algorithm
• Phase offset calculations are relooked at, and the phase offset, i.e., not obtained within the same second is eliminated.
• Abnormal phase offset corrections are omitted and all phase corrections are applied in nanoseconds, as calibrated to Rubidium Frequency.
• Slave and master clocks are calibrated, before applying phase corrections, making sure the slave is always behind the master.
• One-step mode implementation, significantly improved Phase Offset.
[0032] Clock Synthesizer Algorithm
• Linux to VHDL communication (exchange of Time Observables) are white box tested and found out error “Phase Offset needs to be calibrated to Rubidium Oscillator Frequency”
• Provisions to Write “Network delay” in nanoseconds were also provided.
• Final Phase difference between the master clock and slave clock is seen on CRO.
[0033] FIG. 3 illustrates an exemplary schematic view of accuracy causes 300, in accordance with an embodiment of the present disclosure. The bad accuracy at the receiver clock is depicted in FIG.3 and the root cause for the accuracy is network delay and phase offset.
[0034] Thus, the present invention overcomes the drawbacks, shortcomings, and limitations associated with existing solutions, and provides the apparatus 100 with having a clock servo module and clock synthesizer modules that are implemented to tackle the phase offset and network delay issues. The apparatus 100 adjusts the slave clock in PTP protocol to achieve nanosecond accuracy, up to 200 nanoseconds, at the slave clock
[0035] It will be apparent to those skilled in the art that the apparatus 100 of the disclosure may be provided using some or all of the mentioned features and components without departing from the scope of the present disclosure. While various embodiments of the present disclosure have been illustrated and described herein, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

ADVANTAGES OF THE PRESENT INVENTION
[0036] The present invention provides an apparatus with having clock servo module and clock synthesizer modules that are implemented to tackle the phase offset and network delay issues.
[0037] The present invention provides an apparatus that adjusts the slave clock in PTP protocol to achieve nanosecond accuracy, up to 200 nanoseconds, at the slave clock.
, Claims:1. An apparatus (100) of precision time protocol (PTP) master-slave Internet Protocol Version 4/Internet Protocol Version 6 (IPv4/IPv6) and PTP unaware network environment, on custom hardware, the apparatus comprising:
an oscillator (104) that generates PTP packets of first predefined frequency which is converted to second predefined frequency; and
a clock synthesizer module (106) configured in a field programmable gate array (FPGA) (102) and coupled to the oscillator (104) to derive the PTP packets of the second predefined frequency to calculate the difference in the timing for a period of time and sends the corrected value to the oscillator, wherein the clock synthesizer module generates pulse per second (PPS) that measures the slave accuracy with PTP master.
2. The apparatus as claimed in claim 1, wherein the first predefined frequency is converted to the second predefined frequency using the phase linked loop (PLL) of the FPGA, wherein the first predefined frequency is 10MHz and the second predefined frequency is 250MHZ.
3. The apparatus as claimed in claim 1, wherein the oscillator frequency is corrected via universal asynchronous receiver-transmitter (UART) by continuously observing the oscillator and the time received in the PTP packet over the period of time and correcting the oscillator frequency at regular intervals to maintain the accuracy.
4. The apparatus as claimed in claim 1, wherein the clock correction keeps track of the frequency variation of the oscillator due to temperature, vibration and ageing of the oscillator.
5. The apparatus as claimed in claim 1, wherein the clock synthesizer module (106) receives the timestamps from the PTP packets and calculates the time difference between the PTP master and the slave, wherein the clock synthesizer module corrects the slave time with the time difference.
6. The apparatus as claimed in claim 1, wherein the phase offset corrections are sent to the hardware that comprises the seconds counter (120-1, 120-2) and nanoseconds counter (118).
7. The apparatus as claimed in claim 1, wherein the PTP protocol makes the slave clock always trail behind the master clock, wherein the sync packet time stamp observable is copied to the slave seconds counter and network latency calculated between the master and slave clock is copied into the nanoseconds counter.
8. The apparatus as claimed in claim 1, wherein the time stamp observable is transferred from the hardware to a processor, wherein the time observables are stored in memory and the calculation of the delay and phase offset is performed in the processor.
9. The apparatus as claimed in claim 1, wherein the apparatus (100) filters the phase offsets by cross-validating the time of arrival to be calculated within the same second and abnormal deviations from the median value, as calculated for every fixed number of phase offset observations.
10. The apparatus as claimed in claim 1, wherein the apparatus comprises a clock servo module and the clock synthesizer modules that are implemented to tackle the phase offset and network delay issues.