DESC:TECHNICAL FIELD
[0001] The present invention relates generally to an advanced time synchronization and distribution systems, more specifically involving the navigation satellite receivers dissipating time and position information.
BACKGROUND

[0002] Navigation Satellite System refers to a constellation of satellites providing signals from space that transmit positioning and timing data to navigation receivers. These receivers use the navigation algorithms like triangulation and trilateration, to determine its position and time accurately. All such receivers have built-in clock module, that needs to be synchronized with satellite clock. The accuracy of receiver position determination is inversely proportional to time error between receiver clock and satellite clock. This time, which is procured by receiver clock can be stabilized with some additional time error, with the help of clock modules like “Rubidium Oscillator”. Such clock modules can be used as reference and same time can be distributed to other clients.
[0003] Assembled interconnection of hardware components, mentioned in above paragraph to distribute the time is called as the Time Server Hardware. Time Server uses NTP or PTP protocols to distributed the time to clients across network. NTP is designed for millisecond order distribution and PTP protocol with hardware time stamping feature ensures nano second order distribution. PTP protocol further used two profiles namely E2E and P2P. E2E profile only accounts for network latency at Time server node and Client Node. However, P2P profile does accounts and compensate for next hop delays, transient delays and resident delays, provided intermediate nodes are PTP aware.
[0004] Open AMP framework is multicore programming support system on the FPGA SoC architectures. It facilitates the communication between the cores via ring buffers and messaging API. In such framework, there is a master core and slave core. Master core takes control of all the peripherals in the processing system and act as a pivot for control flow of all communications between cores. Linux kernel is ported on the master core and corresponding peripherals attached and configured in device tree blob.
[0005] US9357516B2 discloses the transfer of synchronization in hybrid global navigation satellite packet network system. It proposes a combination of the elements including, GNSS receiver, switching part, operative part and controller. Controller component determines the time reference, after calculating the time difference between original GNSS signal and imported signal, using already predetermined averages. This patent is a multi-constellation solution to Timing synchronization problem. However, in this patent all constellations are decoded by same GNSS receiver unit. Moreover, multi core architecture is not utilized to achieve patent objective, the patent proposed relies totally on multi core processing provisions.
[0006] US9203600B1 discloses generating the globally coherent time stamps. It proposes a way improve time synchronization error introduced because of the transmission delays of the time distribution protocols. True time interval related to plurality of time references is determined. This method includes receiving an initial local stamp, receiving reference timestamps transmitted, receiving a time of-arrival local stamp, determining transmission delays associated with the time references, and calculating, using a processor, time offset intervals corresponding to the references. Multi core architecture is not utilized to achieve patent objective, the patent proposed relies totally on multi core processing provisions.
[0007] US959607bB1 discloses a picosecond clock synchronization technique for communication and navigation platform equipment. The system here comprises of a synchronizing sensor and a measured sensor which may be compared to the reference sensor. The reference sensor and measured sensor may generate a clock signal having a particular frequency and a time mark signal. The system include a precision time/frequency estimator (PTFE) coupled to the sensors and configured to determine an output. Multicore architecture is not utilized to achieve patent objective, the patent proposed relies totally on multicore processing provisions.
[0008] There is still a need of a technical solution which solves the above defined problems and provide a method and an apparatus to achieve nano second order time synchronization, mixing multi constellation satellite systems distributed over two different receiver units via Open AMP frame work.

SUMMARY
[0009] This summary is provided to introduce concepts related to generally to an advanced time synchronization and distribution systems. The invention more specifically involves the navigation satellite receivers dissipating time and position information.
[0010] In an embodiment of the present invention, a method for time synchronization in nanoseconds order by a multicore satellite receiver apparatus is disclosed. The method includes implementing a plurality of functionalities of a time reference server by a Core-0 of an FPGA based SoC. The plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed. Further, this method includes implementing a plurality of functionalities of a bare-metal based IRNSS receiver module by a Core-1 of the FPGA based SoC. This method includes achieving communication between the Core-0 and Core-1 by an Open Asymmetric Multi-Processing (OpenAMP), wherein the OpenAMP includes an Inter Process Communication (IPC).
[0011] In another embodiment, the method includes calibrating a received time from the multicore satellite receiver by a rubidium oscillator. Further, the received time information is filled up by a nano second register in to the PTP packet which is done in the FPGA for maintaining nano second order accuracy and for achieving a hardware time stamping capability.

[0012] In another embodiment, the method includes millisecond order distribution by the Network Time Protocol and nanosecond order distribution by the Precision Time Protocol based on the hardware time stamping.
[0013] In another embodiment, the method includes utilizing a RPMsg component for communication between the Core-0 and Core-1 by the IPC.
[0014] In another embodiment, the plurality of functionalities of the time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.
[0015] In another embodiment, the method includes permitting a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like by the time reference server.
[0016] In another embodiment, the method includes receiving input as a pulse per second (1PPS) signal and NMEA from a GNSS receiver module and the IRNSS receiver module by the time reference server.
[0017] In another embodiment, the method includes selecting the 1 PPS signal from the IRNSS receiver module or the GNSS receiver module based on the constellation mode by a 1 PPS MUX module.
[0018] In an embodiment of the present invention, a multicore satellite receiver apparatus for time synchronization in nanoseconds order is disclosed. It further discloses an FPGA based SoC including a plurality of cores such as Core-0 and Core-1. The Core-0 is configured to implement a plurality of functionalities of a time reference server, wherein a plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed. Further, the Core-1 is configured to implement a plurality of functionalities of a bare-metal based IRNSS receiver module. Further, an Open Asymmetric Multi-Processing (OpenAMP) is configured to achieve communication between the Core-0 and Core-1, wherein the OpenAMP includes an Inter Process Communication (IPC).
[0019] In another embodiment, the apparatus includes a rubidium oscillator which is configured to calibrate a received time from the multicore satellite receiver. The apparatus further includes a nano second register which is configured to fill up the received time information in to the PTP packet which is done in the FPGA to maintain nano second order accuracy and to achieve a hardware time stamping capability.
[0020] In another embodiment, the apparatus includes the Network Time Protocol which is configured to distribute millisecond order and the Precision Time Protocol which is configured to distribute nanosecond order based on the hardware time stamping.
[0021] In another embodiment, the IPC is configured to utilize a RPMsg component for communication between the Core-0 and Core-1.
[0022] In another embodiment, the plurality of functionalities of a time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.
[0023] In another embodiment, the time reference server is further configured to permit a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like.
[0024] In another embodiment, the apparatus further includes a GNSS receiver module wherein the time reference server receives input as a pulse per second (1PPS) signal and NMEA from the GNSS receiver module and the IRNSS receiver module.
[0025] In another embodiment, the apparatus further includes a 1 PPS MUX module which is configured to select the 1 PPS signal from the IRNSS receiver module or the GNSS receiver module based on the constellation mode.

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0026] The detailed description is described with reference to the accompanying figures.
[0027] Figure 1 illustrates a G3I time server functional block diagram, in accordance with an exemplary embodiment of the present invention.
[0028] Figure 2 illustrates a FPGA-SoC PS-PL 1PPS NTP-RTC synchronization, in accordance with an exemplary embodiment of the present invention.
[0029] Figure 3 illustrates hardware time stamping capability as implemented in the architecture mentioned in Figure 1, in accordance with an exemplary embodiment of the present invention.
[0030] Figure 4 illustrates a flowchart of a method that allows the hardware time stamping, in accordance with an exemplary embodiment of the present invention.
[0031] Figure 5 illustrates a flowchart of a method for transferring of PPS signal from FPGA to SOC on Core-0, for NTP server, in accordance with an exemplary embodiment of the present invention.
[0032] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the present invention. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
[0033] The various embodiments of the present disclosure describe about a method and an apparatus for time synchronization in nanoseconds order by multicore satellite receiver architecture.
[0034] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details. One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0035] However, the apparatuses and methods are not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the presently invention and are meant to avoid obscuring of the present invention.
[0036] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0037] The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0038] It should be noted that the description merely illustrates the principles of the present invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described herein, embody the principles of the present invention. Furthermore, all examples recited herein are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the invention and the concepts contributed by the inventor to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.
[0039] In an embodiment of the present invention, a method for time synchronization in nanoseconds order by a multicore satellite receiver apparatus is disclosed. The method includes implementing a plurality of functionalities of a time reference server by a Core-0 of an FPGA based SoC. The plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed. Further, this method includes implementing a plurality of functionalities of a bare-metal based IRNSS receiver module by a Core-1 of the FPGA based SoC. This method includes achieving communication between the Core-0 and Core-1 by an Open Asymmetric Multi-Processing (OpenAMP), wherein the OpenAMP includes an Inter Process Communication (IPC).
[0040] In another embodiment, the method includes calibrating a received time from the multicore satellite receiver by a rubidium oscillator. Further, the received time information is filled up by a nano second register in to the PTP packet which is done in the FPGA for maintaining nano second order accuracy and for achieving a hardware time stamping capability.

[0041] In another embodiment, the method includes millisecond order distribution by the Network Time Protocol and nanosecond order distribution by the Precision Time Protocol based on the hardware time stamping.
[0042] In another embodiment, the method includes utilizing a RPMsg component for communication between the Core-0 and Core-1 by the IPC.
[0043] In another embodiment, the plurality of functionalities of the time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.
[0044] In another embodiment, the method includes permitting a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like by the time reference server.
[0045] In another embodiment, the method includes receiving input as a pulse per second (1PPS) signal and NMEA from a GNSS receiver module and the IRNSS receiver module by the time reference server.
[0046] In another embodiment, the method includes selecting the 1 PPS signal from the IRNSS receiver module or the GNSS receiver module based on the constellation mode by a 1 PPS MUX module.
[0047] In an embodiment of the present invention, a multicore satellite receiver apparatus for time synchronization in nanoseconds order is disclosed. It further discloses an FPGA based SoC including a plurality of cores such as Core-0 and Core-1. The Core-0 is configured to implement a plurality of functionalities of a time reference server, wherein a plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed. Further, the Core-1 is configured to implement a plurality of functionalities of a bare-metal based IRNSS receiver module. Further, an Open Asymmetric Multi-Processing (OpenAMP) is configured to achieve communication between the Core-0 and Core-1, wherein the OpenAMP includes an Inter Process Communication (IPC).
[0048] In another embodiment, the apparatus includes a rubidium oscillator which is configured to calibrate a received time from the multicore satellite receiver. The apparatus further includes a nano second register which is configured to fill up the received time information in to the PTP packet which is done in the FPGA to maintain nano second order accuracy and to achieve a hardware time stamping capability.
[0049] In another embodiment, the apparatus includes the Network Time Protocol which is configured to distribute millisecond order and the Precision Time Protocol which is configured to distribute nanosecond order based on the hardware time stamping.
[0050] In another embodiment, the IPC is configured to utilize a RPMsg component for communication between the Core-0 and Core-1.
[0051] In another embodiment, the plurality of functionalities of a time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.
[0052] In another embodiment, the time reference server is further configured to permit a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like.
[0053] In another embodiment, the apparatus further includes a GNSS receiver module wherein the time reference server receives input as a pulse per second (1PPS) signal and NMEA from the GNSS receiver module and the IRNSS receiver module.
[0054] In another embodiment, the apparatus further includes a 1 PPS MUX module which is configured to select the 1 PPS signal from the IRNSS receiver module or the GNSS receiver module based on the constellation mode.
[0055] Figure 1 illustrates a G3I time server functional block diagram, according to an exemplary implementation of the present disclosure. GNSS/IRNSS based NTP/PTP Time Reference Server is developed on FPGA based SoC consists of two identical ARM cores viz. Core-0 & Core-1 (102 & 103). One of the core, Core-0 (102) will be used to implement the Time Reference Server functionalities, in which Linux based NTP & PTP synchronization protocols will be executed. The other core, Core-1 (103) will be used to implement the bare-metal based IRNSS receiver module (105) functionalities. The communication between the two cores will be achieved through inter process communication in which a RPMsg component will be utilized. In order to work Linux based Time Reference Server and Bare-metal based IRNSS Receiver simultaneously, the Open asymmetric Multi-Processing (OpenAMP) (101) based framework is proposed. The OpenAMP (101) is a framework, providing the software components needed to enable the development of software applications for asymmetric multi-processing (AMP) systems.
[0056] The Core-0 (102) of processor will be used to implement the GNSS signal processing, PTP & NTP functions. The other Core-1 (103) will be used to implement the bare-metal based IRNSS receiver functionalities. The G3I Time Reference Server receives input as a pulse per second (1PPS) signal and NMEA sentence from the GNSS receiver module (104) and the IRNSS receiver module (105). The communication between the cores will be achieved through inter process communication in which the RPMsg component is utilized. The NMEA data/other receiver parameters can be sent/receive between cores through the RPMsg component.
[0057] The G3I Time server requires 1 PPS and ToD as input. Based on the user input (constellation mode), 1 PPS MUX module (106) selects 1 PPS signal from either IRNSS receiver module (105) or GNSS receiver module (104). 1 PSS accuracy with respect to GNSS will be 50ns. Similarly based on the constellation mode, the G3I time reference server takes ToD from IRNSS receiver module (105) or GNSS receiver module (104).
[0058] The G3I Time Server supports both Network Time Protocol (NTP) and Precision Time Protocol (PTPv2 IEEE 1588-2008). TRS has multiple Gigabit Ethernet ports for time dissemination over the network using time synchronization protocols. The Network Time Protocol provides accuracy of 2ms where the Precision Time Protocol (PTP) provides client accuracy of 200?s. In absence of GNSS/IRNSS Sources, TRS enters into holdover mode and provides time accuracy of microsecond order using CLK-Source (Rubidium/OCXO /TCXO). Linux NTP Services (NTP Daemon) is used to implement the NTP protocol. It supports more than 5000 clients. Standard IEEE Precision Time Protocol (PTPv2) has been developed and implemented to provide the accuracy of sub nano-seconds. PTP Time Stamp module (108) is implemented in the FPGA to provide the PTP Hardware Time Stamping feature. The following features are included in the PTPv2 protocol stack. The PTPv2 will support more than 500c clients.
- E2E PTP Grand Master
- P2P PTP Grand Master
- Hardware Time Stamping
[0059] The following software modules are in the Core-0 (Linux):
- NTP Time Server (Core-0 of ARM + FPGA)
- PTP Time Server (Core-0 of ARM + FPGA)
- Clock Disciplining Algorithm (Core-0 of ARM + FPGA)
- NMEA Processing module (Core-0 of ARM+FPGA)
- 1PPS Processing module (Core-0 of ARM+FPGA)
- Nano Second Counter Module(Core-0 of ARM+FPGA)
[0060] The following software modules are in the Core-1 (Bare-metal)
- PVT Algorithm (Core-1 of SoC+ FPGA)
- Baseband Processing (Core-1 of SoC+ FPGA)
[0061] Figure 2 illustrates a FPGA-SoC PS-PL 1PPS NTP-RTC synchronization, according to an exemplary implementation of the present disclosure. Linux kernel is installed on SoC. NTP server is installed on Linux to provide NTP services over Ethernet which is connected on PS side. NMEA data and 1 PPS is given from GNSS receiver (204). Following steps are followed for time and PPS synchronization.
- GNSS receiver (204) will provide 1 PPS out and NMEA data out (Serial Port).
- 1 PPS will be given as input to SoC via GPIO.
- NMEA serial data will be given as input to SoC Via PL Serial port.
- NTP server (201) will be running on Linux (SoC).
- NTP server (201) uses 1PPS signal to synchronize RTC via NMEA driver (203).
- NTP packets (202) will be sent out from PS side Ethernet interface.
[0062] Figure 3 illustrates hardware time stamping capability as implemented in the architecture mentioned in Figure 1, in accordance with an exemplary embodiment of the present invention. In a Time server board, while in operation to produce a PTP packet. During execution, a mechanism in hardware that maintains the nano seconds and fill up in PTP packet. The method of hardware counter in the FPGA, for maintaining the seconds counter and nano seconds counter. The method of updating seconds counter and resetting nanosecond counter, in synchronization with 1PPS signal generated from rubidium oscillator. The method of Time stamping the PTP packet, received from SOC in FPGA, to achieve both Hardware Time stamping and Satellite Clock synchronization.
[0063] Figure 4 illustrates a flowchart of a method that allows the hardware time stamping, in accordance with an exemplary embodiment of the present invention.
[0064] At step 402, selecting a stable 1 PPS signal from GNSS Receiver module and Rubidium oscillator received in to FPGA.
[0065] At step 404, generating counts by Nanosecond counter from 10MHz of Rubidium oscillator and stable 1PPS and giving nanosecond value to Time-stamp unit.
[0066] At step 406, sending value by seconds counter to Arm Core and Time stamp unit.
[0067] At step 408, taking time (second and nanosecond) by Time Stamp unit and appending to exiting PTP Ethernet packet and saving the time of incoming packet.
[0068] Figure 5 illustrates a flowchart of a method for transferring of PPS signal from FPGA to SOC on Core-0, for NTP server, in accordance with an exemplary embodiment of the present invention.
[0069] At step 502, receiving 1 PPS signal in to FPGA from GNSS Receiver module.
[0070] At step 504, routing 1 PPS to SOC Via GPIO pins.
[0071] At step 506, identifying 1PPS as interrupt in Linux Kernel by NMEA driver.
[0072] At step 508, receiving 1 PPS by NTP server via NMEA driver to synchronize RTC.
[0073] In one of the exemplary implementation, a hardware architecture specimen that allows the mixing of constellations distributed over two different cores of same processor is disclosed. In a Time server board, while in operation the interconnection of SATELLITE1 and SATELLITE2 basebands. During operation, a mechanism to communicate between SATELLITE1 core and SATELLITE2 core via a Middleware layer. Further, a method retrieving the Baseband parameters on the Bare-metal core(running SATELLITE2 baseband) of the SOC. The method of interconnecting the SATELLITE1 and SATELLITE2 basebands chain via Ring buffers and Open AMP middleware interface. The method of selecting one constellation depending on the visibility of the satellite.
[0074] In another exemplary implementation, a method that allows transfer of PPS signal from FPGA to SOC on core0, for NTP server is disclosed. In a Time server board, while in operation to synchronize the RTC clock in SOC. During execution, a mechanism facilitated in hardware via GPIO pins, to synchronize GPS clock and RTC clock. A method of capturing the 1PPS digital signal from the satellite receiver module in FPGA and transferring it to SOC via GPIO pins. A method of configuring Linux kernel to interpret 1PPS signal as interrupt, as received as GPIO out in Linux. A method of synchronizing GPS-PPS with RTC clock in SOC via NTP server configuration.
[0075] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:
1. A method for time synchronization in nanoseconds order by a multicore satellite receiver apparatus, said method comprising:
implementing, by a Core-0 (102) of an FPGA based SoC, a plurality of functionalities of a time reference server, wherein a plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed;
implementing, by a Core-1 (103) of the FPGA based SoC, a plurality of functionalities of a bare-metal based IRNSS receiver module (105);
achieving, by an Open Asymmetric Multi-Processing (OpenAMP) (101), communication between the Core-0 (102) and Core-1 (103), wherein the OpenAMP (101) includes an Inter Process Communication (IPC).

2. The method as claimed in claim 1, said method further comprises:
calibrating, by a rubidium oscillator (107), a received time from the multicore satellite receiver;
filling up, by a nano second register, the received time information in to the PTP packet which is done in the FPGA for maintaining nano second order accuracy and for achieving a hardware time stamping capability.

3. The method as claimed in claim 1, said method further comprises millisecond order distribution by the Network Time Protocol and nanosecond order distribution by the Precision Time Protocol based on the hardware time stamping.

4. The method as claimed in claim 1, said method further comprises utilizing, by the IPC, a RPMsg component for communication between the Core-0 (102) and Core-1 (103).

5. The method as claimed in claim 1, wherein the plurality of functionalities of the time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.

6. The method as claimed in claim 1, said method further comprises permitting, by the time reference server, a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like.

7. The method as claimed in claim 1, said method further includes receiving, by the time reference server, input as a pulse per second (1PPS) signal and NMEA from a GNSS receiver module (104) and the IRNSS receiver module (105).

8. The method as claimed in claim 1 and claim 7, said method further comprises selecting, by a 1 PPS MUX module (106), the 1 PPS signal from the IRNSS receiver module (105) or the GNSS receiver module (104) based on the constellation mode.

9. A multicore satellite receiver apparatus for time synchronization in nanoseconds order, said apparatus comprising:
an FPGA based SoC including a plurality of cores such as Core-0 (102) and Core-1 (103);
the Core-0 (102) is configured to implement a plurality of functionalities of a time reference server, wherein a plurality of a Network Time Protocol (NTP) and a Precision Time Protocol (PTP) synchronization protocols are executed;
the Core-1 (103) is configured to implement a plurality of functionalities of a bare-metal based IRNSS receiver module (105);
an Open Asymmetric Multi-Processing (OpenAMP) (101) configured to achieve communication between the Core-0 (102) and Core-1 (103), wherein the OpenAMP (101) includes an Inter Process Communication (IPC).

10. The apparatus as claimed in claim 9, said apparatus further comprises:
a rubidium oscillator (107) configured to calibrate a received time from the multicore satellite receiver;
a nano second register configured to fill up the received time information in to the PTP packet which is done in the FPGA to maintain nano second order accuracy and to achieve a hardware time stamping capability.

11. The apparatus as claimed in claim 9, said apparatus further comprises:
the Network Time Protocol is configured to distribute millisecond order; and
the Precision Time Protocol is configured to distribute nanosecond order based on the hardware time stamping.

12. The apparatus as claimed in claim 9, wherein the IPC is configured to utilize a RPMsg component for communication between the Core-0 (102) and Core-1 (103).

13. The apparatus as claimed in claim 9, wherein the plurality of functionalities of a time reference server includes Global Navigation Satellite System (GNSS) signal processing, Precision Time Protocol (PTP) functions, Network Time Protocol (NTP) functions and the like.

14. The apparatus as claimed in claim 9, wherein the time reference server is further configured to permit a user to choose a constellation mode such as GPS, GLONASS, GALLILEO (G3I), IRNSS, hybrid mode and the like.

15. The apparatus as claimed in claim 9, said apparatus further includes a GNSS receiver module (104) wherein the time reference server receives input as a pulse per second (1PPS) signal and NMEA from the GNSS receiver module (104) and the IRNSS receiver module (105).

16. The apparatus as claimed in claim 9 and claim 15, said apparatus further includes a 1 PPS MUX module (106) which is configured to select the 1 PPS signal from the IRNSS receiver module (105) or the GNSS receiver module (104) based on the constellation mode.