Description:The present application claims priority to U.S. Non-Provisional Patent Application No. 17/484,252 filed on 24 September 2021 and titled “METHOD AND APPARATUS TO AUTHENTICATE A MEMORY MODULE” the entire disclosure of which is hereby incorporated by reference.
FIELD
This disclosure relates to memory modules and in particular to authentication of memory modules.
BACKGROUND
A memory module is a printed circuit board on which memory integrated circuits (“chips”) are mounted to another printed circuit board, such as a motherboard, via a connector (also referred to as a “socket”). The connector is installed on the motherboard and a memory module is inserted into the connector. The connector enables interconnection between a memory module and a circuit on the motherboard. A dual in-line memory module (DIMM) has separate electrical contacts on each side of the memory module.
In addition to memory integrated circuits, the memory module can include a serial presence detect (SPD) integrated circuit (“chip”). The SPD integrated circuit stores information about the memory module including the type of memory integrated chips on the memory module, manufacturer, serial number and timing parameters to be used by a memory controller to access the memory integrated chips. The information stored in the SPD integrated circuit can be read by a Built In Operating System (BIOS) during power up of a system to configure a memory controller to use the memory integrated circuits on the DIMM.

BRIEF DESCRIPTION OF THE DRAWINGS
Features of embodiments of the claimed subject matter will become apparent as the following detailed description proceeds, and upon reference to the drawings, in which like numerals depict like parts, and in which:
, Claims:1. A memory module comprising:
a plurality of memory devices; and
a sideband bus device hub comprising a non-volatile memory, the non-volatile memory to store attributes for the plurality of memory devices and the memory module, serial numbers for the plurality of memory devices and a memory module attribute number, the memory module attribute number generated based on the attributes for the plurality of memory devices and the memory module and the serial numbers for the plurality of memory devices stored in a portion of the non-volatile memory.

2. The memory module of Claim 1, wherein the memory module attribute number is generated using an cryptographic hash function.

3. The memory module of Claim 2, wherein the cryptographic hash function is signed using a private key that is provisioned during manufacture of the memory module.

4. The memory module of Claim 1, wherein the memory module is a Dual Inline Memory Module (DIMM).

5. The memory module of Claim 1, wherein the sideband bus device hub comprises a serial bus to communicate with a Baseband Management Controller (BMC) coupled to the memory module.

6. The memory module of Claim 5, wherein the serial bus is an I3C serial bus.

7. The memory module of Claim 1 further comprising:
a host memory bus, the memory module to return the attributes for the plurality of memory devices and the memory module over the host memory bus in response to a request received from a host coupled to the host memory bus.

8. The memory module of Claim 1, further comprising:
a serial bus, the memory module to return the attributes for the plurality of memory devices and the memory module over the serial bus in response to a request received from a Baseband Management Controller (BMC) coupled to the serial bus.

9. The memory module of Claim 1, wherein the memory module attribute number is generated prior to use of the memory module in a system.

10. The memory module of Claim 9, wherein the memory module attribute number is 384-bits.

11. A system comprising:
a memory module comprising:
a plurality of memory devices; and
a sideband bus device hub comprising a non-volatile memory, the non-volatile memory to store attributes for the plurality of memory devices and the memory module, serial numbers for the plurality of memory devices and a memory module attribute number, the memory module attribute number generated based on the attributes for the plurality of memory devices and the memory module and the serial numbers for the plurality of memory devices stored in a portion of the non-volatile memory; and
a display communicatively coupled to a processor to display data stored in the plurality of memory devices.

12. The system of Claim 11, wherein the memory module attribute number is generated using an cryptographic hash function.

13. The system of Claim 12, wherein the cryptographic hash function is signed using a private key that is provisioned during manufacture of the memory module.

14. The memory module of Claim 11, wherein the memory module is a Dual Inline Memory Module (DIMM).

15. The system of Claim 14, wherein the sideband bus device hub comprises a serial bus to communicate with a Baseband Management Controller (BMC) coupled to the memory module.

16. The system of Claim 15, wherein the serial bus is an I3C serial bus.

17. The system of Claim 11, further comprising:
a host memory bus, the memory module to return the attributes for the plurality of memory devices and the memory module over the host memory bus in response to a request received from a host coupled to the host memory bus.

18. The system of Claim 11, further comprising:
a serial bus, the memory module to return the attributes for the plurality of memory devices and the memory module over the serial bus in response to a request received from a Baseband Management Controller (BMC) coupled to the serial bus.

19. A method comprising:
storing, in a non-volatile memory in a sideband bus device hub, attributes for a plurality of memory devices and a memory module, serial numbers for the plurality of memory devices and a memory module attribute number, the memory module attribute number generated based on the attributes for the plurality of memory devices and the memory module and the serial numbers for the plurality of memory devices stored in a portion of the non-volatile memory.

20. The method of Claim 19, further comprising:
returning the attributes for the plurality of memory devices and the memory module over a serial bus in response to a request received from a Baseband Management Controller (BMC) coupled to the serial bus.