DESC:FIELD OF INVENTION
[001] The present invention relates generally to a method and an apparatus to minimize an error rate in LED based communication. The invention, more particularly, relates to a method and an apparatus to minimize error rate in LED based communication using spatial diversity.

BACKGROUND
[002] In indoor communication environment, very high data rate can be achieved with Line of Sight link. But wide coverage area and mobility are the main concerns with Line of Sight links in such scenarios. Power distribution at receiver using commercial off the self-Light Emitting Diode (LED) transmitter is usually not uniform within coverage area of LED, so photo diode present inside Field of View of LED may not receive adequate power level to detect the transmitted data. Also, multipath signal mitigation becomes challenging in indoor environment with reflective surfaces. Therefore, to ensure high data rate and link availability at all times, multiple receivers with smaller active areas (for high speed data reception) would be the preferred alternative for robust communication.
[003] US8045864B2 discloses a method to process incoming signal using dividing a symbol duration at transmitter end to achieve a divided duration, said division being done according to an equal time interval to set the divided duration to a plurality of sequential time slots, the symbol duration being a time required to transmit one of a symbol and a bit. and determining a gain value of each photodiode of said plurality of photo-detectors during a time slot of a symbol duration, in consideration of an area of each photo-detector on the photo-detector array during the time slot and the time slot position within the symbol duration; multiplying a gain value of each photo-detector of said plurality of photo-detectors by an output value of a corresponding photo-detector; and summing up output values of each of the photo-detectors by which the gain value has been multiplied and calculating a total of output values of the time slot.
[004] US5784432A discloses a photo detector array which is used but not for data communication claims a method and apparatus for x-ray measurement of certain properties of a solid material. coherently transmitting visible light originating from the scintillation of diffracted x-radiation from the solid material gathered along a substantially one dimensional linear arc, to a two-dimensional photo-sensor array. The two-dimensional photo detector array, with its many closely packed light sensitive pixels, is employed to process the information contained in the diffracted radiation and present the information in the form of a conventional x-ray diffraction spectrum.
[005] CN101232327A discloses a realization proposal of a visible light space division multi-access multi-channel system. A visible light at a sending end sends multiple channels of coded light signals, a light receiver forms the space separated image spots on a planar photo detector by an imaging optical system thereof, the different receivers select their own outputs according to the different positions of image spots and the different response signals of the image elements which are covered by the image spots, thus realizing the tracking of light spots during the space diversity and the movement.
[006] An IEEE 802.15.7 standard for short range-Optical wireless communications (2018 revision) discloses a PHY frame format for different data transmission modes i.e. single, packed and burst modes. For shorter data communication, single mode of data transmission is used. In Frame structure, PHY Service Data Unit field (PSDU) carries the data of the PHY frame and it has variable size of maximum 65536 bytes. The channel coherence time should be greater than time required to transmit complete frame with maximum frame size at given position of receiver to receive complete frame correctly. The maximum bit rate supported in LED based communication is inversely proportional to Root Mean Square delay spread of the channel.
[007] Therefore, there is still a need of a technical solution which solves the above defined problems and provide a method and an apparatus to minimize the error rate in LED based communication.

SUMMARY
[008] This summary is provided to introduce concepts related to a method and an apparatus to minimize an error rate in LED based communication. This summary is neither intended to identify essential features of the present invention nor is it intended for use in determining or limiting the scope of the present invention.
[009] In an embodiment of the present invention, a method for minimizing error rate in led based communication is provided. The method includes framing a data as per IEEE 802.15.7 standard for short range-Optical wireless communications (2018 revision) by a transmitter. Further, it includes inserting a sync field of known 4 bytes in a payload part of a frame by a signal processing hardware unit. This frame modulates a LED intensity at a physical layer at transmitter. The method further includes sensing the LED intensity variation at a receiver by a photo-detector array. This photo-detector array includes a plurality of photo-detectors. Further, the method includes transmitting a data output to its respective trans-impedance amplifier by each of the photo-detectors in the array. Further, transmitting the data output to their respective Analog to Digital Converter (ADC) channel by the trans-impedance amplifiers. Further, detecting the frame by comparing data outputs from the ADCs with the value of the Preamble and Once the frame is detected, verifying the synchronization and chosen least erroneous photo detector path by comparing the input data from corresponding ADC with the value of sync field every 4096 bytes of the payload bytes. Finally, FPGA outputs are verified by the data checker.
[0010] In another embodiment of the present invention, an apparatus for minimizing error rate in led based communication is provided. The apparatus includes a transmitter system forming PHY Frame as per IEEE 802.15.7 standard for short range-Optical wireless communications (2018 revision). The system includes a signal processing hardware unit at transmitter section to form the PHY frame and insert a sync field in a payload part of a frame at regular intervals. The frame is configured to modulate a LED intensity at a physical layer of the transmitter system. Further, a photo-detector array is configured to sense the LED intensity variation at a receiver. Each of the photo-detectors in the array is configured to transmit a data output to its respective trans-impedance amplifier. These trans-impedance amplifiers are configured to transmit the data output to their respective Analog to Digital Converter (ADC) channel. Further, the system includes a Field Programmable Gate Array (FPGA) which is configured to receive the data output from the corresponding ADC channel selected by bit comparator and data checker which is configured to verify the data output from Field Programmable Gate Array (FPGA).

BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
[0011] The detailed description is described with reference to the accompanying figures.
[0012] Figure 1 illustrates a PHY frame format as defined conventionally in IEEE 802.15.7 standard, in accordance with an embodiment of the present invention.
[0013] Figure 2 illustrates the various positions in the PSDU area of which in payload portion, sync field is inserted at regular intervals, in accordance with an embodiment of the present invention.
[0014] Figure 3 illustrates a logic implementation in FPGA for comparison of the received data from analog to digital converters chain with predefined preamble and sync field format, in accordance with an embodiment of the present invention.
[0015] Figure 4 illustrates three data modes of data transmission as per IEEE 802.15.7, in accordance with an embodiment of the present invention.
[0016] Figure 5 illustrates a block diagram of a system for minimizing error rate in led based communication, in accordance with an embodiment of the present invention.
[0017] Figure 6 illustrates a flowchart of another embodiment of a method for minimizing error rate in led based communication, in accordance with an embodiment of the present invention.
[0018] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present invention. Similarly, it will be appreciated that any flow chart, flow diagram, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

DETAILED DESCRIPTION
[0019] The various embodiments of the present invention describe about a method and an apparatus to minimize an error rate in LED based communication using spatial diversity.
[0020] In the following description, for purpose of explanation, specific details are set forth in order to provide an understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these details.
[0021] One skilled in the art will recognize that embodiments of the present invention, some of which are described below, may be incorporated into a number of systems.
[0022] However, the apparatus is not limited to the specific embodiments described herein. Further, structures and devices shown in the figures are illustrative of exemplary embodiments of the present invention and are meant to avoid obscuring of the present invention.
[0023] Furthermore, connections between components and/or modules within the figures are not intended to be limited to direct connections. Rather, these components and modules may be modified, re-formatted or otherwise changed by intermediary components and modules.
[0024] The appearances of the phrase “in an embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
[0025] In an embodiment of the present invention, an apparatus provides a sync field that has been inserted at every 4096 bytes, which helps in periodic selection of a photo diode to be considered among photo diode array at receiver, in a payload portion of an optical wireless communication frame format. In this application, it is assumed that a channel coherence time is greater than the time required to transmit minimum 6158 bytes ( 4096 bytes of payload bytes + maximum 2048 bytes of preamble+14 PHY (Physical layer) frame header bytes including Header check sequence (HCS) and optional fields) to the mobile receiver in an indoor environment. But, this position of the sync field is scalable depending on channel condition, throughput requirement and the like.
[0026] In another embodiment of the present invention, the method involves that during the frame detection stage, a preamble as per standard (IEEE 802.15.7) is used to compare with outputs of a plurality of analog to digital converters passed through a trans-impedance amplifier and a photo diode array. The matched output with the preamble is selected to be "received data" and respective photo diode is selected for receiving the rest of the frame till the first sync field position. The sync field position and the value is known to the receiver and hence, comparison of the received digital data outputs with the plurality of the analog to digital converters passed through amplifier chain and the photo diode array is carried out in the FPGA with the sync field bytes. Using majority voting method, the photo diode with least erroneous data output is chosen during frame reception as a part of periodic verification of photo diode for receiving the frame. The photo diode array with identical photo diodes with small size of active areas are used for high speed data communication and rejecting noise from surrounding ambient light sources.
[0027] In another embodiment, the frame detection stage further includes comparing the data outputs from the ADCs with a preamble of the frame in the FPGA. Further, a bit comparator selects a final output based on the comparison. The final output is the received data and the FPGA selects a corresponding path for obtaining the received data. The corresponding path includes the photo-detector, the trans-impedance amplifier and the ADC channel. Further, the FPGA verifies the frame length, wherein if the frame length is pending then waiting till the sync field is arrived and comparing, by a Field Programmable Gate Array (FPGA), the digital outputs from the ADCs with the known value of the sync field.
[0028] In another embodiment, each of the photo-detectors in the photo-detector array operates independently wherein the transmitted signal received at the same time by the each of the photo-detectors in the array are processed independently.
[0029] In another embodiment, the processing includes providing the converted outputs received from the photo-detectors to an amplification circuitry and the analog to digital converters before sending to the FPGA for comparison with pre-defined preamble for frame detection and selecting the photo-detector based on the matched output of analog to digital converter with the preamble in the bit comparator.
[0030] In another embodiment, the data in the wireless personal area network (WPAN) is framed as per the IEEE 802.15.7 frame format.
[0031] In another embodiment, the predetermined size of the sync field includes 4 bytes for every 4096 bytes in the payload part of the frame.
[0032] In another embodiment, the photo-detector array including the plurality of photo-detectors have a plurality of smaller active areas, which are arranged horizontally.
[0033] In another embodiment, the plurality of photo-detectors is a plurality of photodiodes.
[0034] In another embodiment, the size of the photo-detector array is scalable depending on the field of view, mounting position and power specifications of the LED source, receiver size constraints, distance between the LED source and the receiver and the like.
[0035] Figure 1 illustrates a PHY frame format as defined conventionally in IEEE 802.15.7 standard, in accordance with an embodiment of the present invention. As per IEEE 802.15.7, the preamble size varies from 8 bytes to 2048 bytes as shown in figure 1 and its value is "AA" in hex format repeating as per preamble size defined.
[0036] Figure 2 illustrates the various positions in the PSDU area of which in payload portion, sync field is inserted at regular intervals, in accordance with an exemplary embodiment of the present invention. The sync field (203, 205) insertion in a payload portion of a PHY (Physical layer) frame. The frequency of inserting the sync field depends on the throughput requirements and channel conditions.
[0037] Figure 3 illustrates a logic implementation in FPGA for comparison of the received data from analog to digital converters chain with predefined preamble and sync field format, in accordance with an exemplary embodiment of the present invention.
[0038] The digital outputs from the plurality of analog to digital converters are compared in FPGA using a 312 bit comparator with known bytes of preamble and the sync field, to choose the photo diode 315 with matched output and least erroneous signal using majority voting, respectively. In LED based communication, the data modulates the intensity of the LED which is sensed by a photo diode 315 at a receiver for data recovery. In indoor environment with commercial off-the-self LED transmitter, the photo diode array structure with small size of active areas at receiving end increases the reliability of link availability at all times for high speed data communication. The smaller active areas of the photo diode 315 helps for high speed data reception and avoids noise from ambient noise sources mitigating multi-path induced inter symbol interference. The plurality of photo diodes 315 of array operate independently, thus providing inputs to trans-impedance amplifier chain 314 which in turn is connected to independent plurality of analog to digital converters 313.
[0039] Considering the preamble size of 8 bytes, whichever analog to digital converters 313 data output matches with "AAAAAAAA", that analog to digital converter 313, corresponding photo diode 315 and trans-impedance amplifier 314 is selected for that frame till the sync field arrives. At every sync field, a bit comparator 312 in the FPGA is configured to verify again whether the selected path (corresponding photo diode, TIA and ADC) is still the least erroneous by comparing the received data outputs with the pre-defined sync field of 4 bytes and periodically selects least erroneous signal path.
[0040] Figure 4 illustrates three data modes of data transmission as per IEEE 802.15.7, in accordance with an embodiment of the present invention.
[0041] Among the three data modes of data transmission as per IEEE 802.15.7, the single mode 400 of data transmission mode is used for short data communication and the other two modes namely packed mode 406 and burst mode 407 are used when higher MAC efficiency is required. The sync field insertion for packed mode 406 and burst mode 407 is always efficient compared with single data mode as payload size of packed mode 406 and burst mode 407 is always greater than the single data mode 400. The overhead due to the sync field in larger payload size doesn't impact much as compared with the smaller payload size i.e. overhead insertion due to sync field will not affect much for packed mode 406 as well as for burst mode 407 compared with single data mode 400.when channel coherence time is less, rather than sending multiple frames with smaller payload size, Sync field can be inserted at appropriate intervals in single data mode. Comparison of overhead due to sync field with multiple frames with smaller payloads for single data mode is described below. The minimum inter frame space for single data mode 400, SIFS is 120 optical clocks while 22 bytes are header byte size considering minimum preamble size of 8 bytes for every frame.
Payload bytes between sync fields, N Overhead due to sync field of 4 bytes Multiple frames with payload size of N
Preamble Size of 8 bytes Preamble Size of 2048 bytes
4096 64 bytes (16 spaces for sync field) 142*15=2130 bytes
2182*15=32730 bytes
16384 16 bytes 142*3=426 bytes 2182*3=6546 bytes
32768 4 bytes 142 bytes 2182 bytes
Table 1: comparison of overhead due to sync field with multiple frames with divided payloads for single data mode
[0042] Table 1 shows that when channel coherence time is smaller than time required to transmit one full PHY frame with 65536 payload bytes, the sync field insertion at any equally spaced intervals in payload area is always efficient than sending multiple frames with smaller payload size. The array size of photo diodes is scalable depending on the position and orientation of the receiver, the power specifications and the field of view of the LED used.
[0043] Figure 5 illustrates a block diagram of a system for minimizing error rate in led based communication, in accordance with an embodiment of the present invention. In this block diagram, apparatus for minimizing error rate in led based communication is provided. The apparatus includes a transmitter (502) which includes a signal processing hardware unit (506) which is configured to form the PHY frame as per IEEE 802.15.7 standard and insert a sync field (203, 205) in a payload part of a frame. The frame is configured to modulate a LED intensity at a physical layer of the transmitter. Further, a photo-detector array (514) is configured to sense the LED intensity variation at a receiver (512). Each of the photo-detectors (514) in the array is configured to transmit a data output to its respective trans-impedance amplifier (516). These trans-impedance amplifiers (516) are configured to transmit the data output to their respective Analog to Digital Converter (ADC) channel (518). Further, the system includes a Field Programmable Gate Array (FPGA)(520) to compare the data outputs of all ADC channels with predefined preamble (during frame detection)/sync field (during frame reception i.e. after successful frame detection) and selects appropriate ADC output after comparison as received data. data checker (522) is configured to verify the data output from the Field Programmable Gate Array (FPGA).
[0044] Further, a bit comparator inside FPGA (520) is configured to select appropriate ADC channel output based on the comparison. This output is the received data. Further, the FPGA (520) is configured to receive this data and verify the frame length. Here, if the frame length is pending then waiting till the sync field is arrived. Further, the Field Programmable Gate Array (FPGA) (520) is configured to compare the digital outputs from the ADCs (518) with the known value of the sync field.
[0045] Figure 6 illustrates a flowchart of another embodiment of a method for minimizing error rate in led based communication, in accordance with an embodiment of the present invention.
[0046] At step 602, at a transmitter, data is framed as per IEEE 802.15.7 frame format.
[0047] At step 604, inserting a sync field (203, 205) of 4 bytes every 4096 bytes in a payload part of a frame by a signal processing hardware unit (506) at a transmitter (502).
[0048] At step 606, the PHY frame (also called physical protocol data unit) modulates LED intensity.
[0049] At step 608, the intensity variation is sensed by the photo-detector array (514) at the receiver (512).
[0050] At step 610, every photo-detector in the array sends its output version to its own trans-impedance amplifier (516).
[0051] At step 612, the output of the trans-impedance amplifier (516) is sent to their respective ADC channel.
[0052] At step 614, checking whether the frame detection stage has reached.
[0053] At step 616, digital outputs from ADCs are compared with known value of preamble in FPGA.
[0054] At step 618, least erroneous matched output of ADC is chosen as received digital data using bit comparator implemented in FPGA.
[0055] At step 620, corresponding path (i.e. Photo detector, TIA and ADC channel) is chosen to get receive data.
[0056] At step 622, checking whether the frame is over. If yes, then the frame ends. If not then at step 624, waiting till the sync field arrives.
[0057] At step 626, checking whether the sync field has arrived. If not then waiting till the sync field arrives. If yes, then at step 628, digital outputs from ADCs are compared with the known value of sync field in FPGA.
[0058] In an exemplary implementation, the method includes receiving light signal from a single LED source using array of identical photo diodes having smaller active areas placed horizontally.
[0059] In another exemplary implementation, each of the photo diodes 315 in photo diode array operates independently i.e. transmitted signal received at same time by multiple photo diodes 315 in array is processed independently.
[0060] In another exemplary implementation, the array size of the photo diodes is scalable depending on the field of view, mounting position and power specifications of the LED source, receiver size constraints, distance between LED source and receiver etc.
[0061] In another exemplary implementation, the method of processing includes that the converted outputs from all the photo diodes 315 are fed to a trans-impedance amplifier 314 and a plurality of analog to digital converters 313, before passing it to FPGA for comparison with pre-defined preamble for frame detection. The method further includes that the selection of the photo diode 315 is decided based on the matched output of the analog to digital converter with preamble in bit comparator 312.
[0062] In another exemplary implementation, a method includes sync field insertion after every fixed positions inside payload portion of PHY frames, which is compared with the received digital data outputs from the analog to digital converters 313 at respective sync field positions and least erroneous signal is selected to be "received data" during the frame reception process thus periodically verifying or selecting photo diode 315 from the array to maintain error rate minimum in received frame.
[0063] In another exemplary implementation, a photodiode array structure with identical photo diodes with small size of active areas at receiver is used for high speed data communication. The smaller field of view at receiver reduces noise due to ambient light sources and the reliability of the frame detection as well as the reception is assured using spatial diversity at the receiver. The preamble of the PHY frame is compared with the incoming data from the photo diodes for frame detection. The sync fields equally spaced between payload bytes reassures periodically verification or selection of appropriate photo diode using bit comparator implemented in FPGA.
[0064] In another exemplary implementation, the frame detection at receiver is carried out using comparison of outputs from the photo diode array after passing through trans-impedance amplifier and analog to digital converter chain with frame preamble in Field Programmable Gate Array (FPGA). The photo diode with data output matching with preamble is chosen as "receiver " to receive frame thereafter. To ease the complete frame reception correctly in mobile receiver, its proposed to insert some known bytes at every fixed position in payload portion of the PHY Frame. Hence, the sync field insertion in payload helps to periodically select the least erroneous photo diode during the frame receiving process which increases the probability of receiving complete frames with as less error rate as possible.
[0065] The foregoing description of the invention has been set merely to illustrate the invention and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the spirit and substance of the invention may occur to person skilled in the art, the invention should be construed to include everything within the scope of the invention.
,CLAIMS:
1. A method for minimizing error rate in led based communication, said method comprising:
forming, by a signal processing hardware unit (506) at a transmitter (502), a PHY data frame as per IEEE 802.15.7;
inserting, by a signal processing hardware unit (506) at a transmitter (502), a sync field (203, 205) in a payload part of a frame, wherein the frame modulates a LED intensity at a physical layer of the transmitter;
sensing, by a photo-detector array (514), the LED intensity variation at a receiver (512), wherein the photo-detector array (514) includes a plurality of photo-detectors (514);
transmitting, by each of the photo-detectors in the array (514), a data output to its respective trans-impedance amplifier (516);
transmitting, by the trans-impedance amplifiers (516), the data output to their respective Analog to Digital Converter (ADC) channel (518);
comparing, by a Field Programmable Gate Array (FPGA) (520), the data outputs from the ADCs (518) with the value of the sync field/ preamble, and
verifying, by a data checker (522), the data output from the FPGA (520) for measuring the error rate.

2. The method as claimed in claim 1, wherein the step of the detecting the frame further comprises:
comparing, by the FPGA (520), the data outputs from the ADCs (518) with a preamble of the frame in the FPGA (520);
selecting, by a bit comparator (520), a final output based on the comparison, wherein the final output is the received data;
selecting, by the FPGA (520), a corresponding path for obtaining the received data, and
verifying, by the FPGA (520), the frame length, wherein if the frame length is pending then waiting till the sync field is arrived and comparing, by a Field Programmable Gate Array (FPGA) (520), the digital outputs from the ADCs (518) with the known value of the sync field.

3. The method as claimed in claim 1, wherein each of the photo-detectors in the photo-detector array (514) is operating independently wherein the transmitted signal received at the same time by the each of the photo-detectors in the array (514) are processed independently.

4. The method as claimed in any one of claims 1–3, wherein the processing comprises:
transmitting PHY frame, by the transmitter(502), receiving the same from the photo-detectors (514) to an amplification circuitry and the analog to digital converters, comparison with pre-defined preamble for frame detection before sending to the FPGA (520) and
selecting, by the FPGA (520), the photo-detector (514) based on the matched output of analog to digital converter (518) with the preamble in the bit comparator (520).

5. The method as claimed in claim 1, wherein the data is framed as per the IEEE 802.15.7 frame format.

6. The method as claimed in claim 1, wherein the predetermined size of the sync field includes 4 bytes for every 4096 bytes in the payload part of the frame.

7. The method as claimed in claim 2, wherein the corresponding path includes the photo-detector (514), the trans-impedance amplifier (516) and the ADC channel (518).

8. The method as claimed in claim 1, wherein the photo-detector array (514) including the plurality of photo-detectors have a plurality of smaller active areas, which are arranged horizontally.

9. The method as claimed in claim 1, wherein said plurality of photo-detectors (514) is a plurality of photodiodes (315).

10. The method as claimed in claim 1, the size of the photo-detector array (514) is scalable depending on the field of view, mounting position and power specifications of the LED source, receiver size constraints, distance between the LED source and the receiver (514) and the like.

11. An apparatus for minimizing error rate in led based communication, said apparatus comprising:
a transmitter (502) comprising signal processing hardware unit (506) is configured to form a PHY frame as per IEEE 802.15.7 format and insert a sync field (203, 205) in a payload part of a frame, wherein the frame is configured to modulate a LED intensity at a physical layer of the transmitter;
a photo-detector array (514) configured to sense the LED intensity variation at a receiver (512);
each of the photo-detectors in the array (514) configured to transmit a data output to its respective trans-impedance amplifier (516), wherein the trans-impedance amplifiers (516) are configured to transmit the data output to their respective Analog to Digital Converter (ADC) channel (518);
a Field Programmable Gate Array (FPGA) (520) configured to compare the data outputs from the ADCs (518) with the value of the preamble, and
a data checker (522) is configured to verify the data output from the FPGA (520) for measuring the error rate.

12. The apparatus as claimed in claim 11, wherein the receiver (512) further comprises:
the bit comparator inside FPGA (520) configured to compare the data outputs from the ADCs (518) with a sync field of the frame in the FPGA (520);
a bit comparator inside FPGA(520) configured to select a final output based on the comparison, wherein the final output is the received data;
the FPGA (520) configured to:
select a corresponding path for obtaining the received data;
verify the frame length, wherein if the frame length is pending then waiting till the sync field is arrived, and
compare the digital outputs from the ADCs (518) with the known value of the sync field.