Claims:We claim:
1. A method of optimizing distribution of data packets in a High Performance Computing (HPC) switch (107), the method comprising:
receiving, by the HPC switch (107), a plurality of data packets from one or more controllers communicatively connected to the HPC switch (107), through a plurality of interconnected Queue Pair (QP) lanes (115) configured in the HPC switch (107);
assigning, by the HPC switch (107), a destination Virtual Lane (VL) from a plurality of interconnected VLs (117) configured in the HPC switch (107) for each of the plurality of data packets based on service level information associated with each of the plurality of data packets;
generating, by the HPC switch (107), a plurality of clusters of one or more ports (119), configured in the HPC switch (107), coupled with each of the plurality of interconnected VLs (117) based on latency determined dynamically for each of the one or more ports (119);
determining, by the HPC switch (107), a first group of the plurality of data packets to be transmitted through the one or more ports (119) belonging to a primary cluster of the plurality of clusters and a second group of the plurality of data packets to be transmitted through the one or more ports (119) belonging to one or more secondary clusters of the plurality of clusters based on the destination VL assigned for each of the plurality of data packets; and
transmitting, by the HPC switch (107), the first group of the plurality of data packets through the one or more ports (119) belonging to the primary cluster and transmitting an acknowledgement key-packet associated with the second group of the plurality of data packets through the one or more ports (119) belonging to the one or more secondary clusters, based on the determination, to the one or more other controllers communicatively connected to the HPC switch (107) for optimizing the distribution of the plurality of data packets in the HPC switch (107).

2. The method as claimed in claim 1, wherein the latency of each of the one or more ports (119) is determined using a performance value computed for each of the one or more ports (119).

3. The method as claimed in claim 2, wherein the performance value is computed based on number of data packets received and transmitted by each of the plurality of interconnected QP lanes (115) for each of the one or more ports (119).

4. The method as claimed in claim 3 wherein the performance value for each of the one or more ports (119) is recomputed at predefined time intervals, to generate a plurality of new clusters of the one or more ports (119) for transmitting at least one of the second group of the plurality of data packets stored in a Direct Memory Access (DMA) (121) and a plurality of new data packets received by the HPC switch (107), to one or more other controllers (103).

5. The method as claimed in claim 1 further comprising reassigning the second group of the plurality of data packets to another destination VL based on a performance value recomputed for each of the one or more ports (119), at predefined time intervals.

6. The method as claimed in claim 1, wherein the primary cluster among the plurality of clusters comprises the one or more ports (119) having ultra-low latency when compared with a predefined latency threshold, and each of the one or more secondary clusters of the plurality of clusters comprise the one or more ports (119) having high latency when compared with the predefined latency threshold.

7. The method as claimed in claim 1, wherein the acknowledgement key-packet is generated, by the HPC switch (107), for each of the plurality of data packets, wherein the acknowledgement key-packet comprises at least a key value indicating destination of each of the plurality of data packets.

8. The method as claimed in claim 7, wherein the acknowledgement key-packet comprises a size less than size of the corresponding plurality of data packets.

9. The method as claimed in claim 1 further comprising storing, by the HPC switch (107), the second group of the plurality of data packets for which the acknowledgement key-packet is transmitted, in a Direct Memory Access (DMA) (121) configured in the HPC switch (107).

10. A High Performance Computing (HPC) switch for optimizing distribution of data packets, the HPC switch (107) comprising:
a processor (109); and
a memory (113) communicatively coupled to the processor (109), wherein the memory (113) stores processor-executable instructions, which, on execution, causes the processor (109) to:
receive a plurality of data packets from one or more controllers communicatively connected to the HPC switch (107), through a plurality of interconnected Queue Pair (QP) lanes (115) configured in the HPC switch (107);
assign a destination Virtual Lane (VL) from a plurality of interconnected VLs (117) configured in the HPC switch (107) for each of the plurality of data packets based on service level information associated with each of the plurality of data packets;
generate a plurality of clusters of one or more ports (119), configured in the HPC switch (107), coupled with each of the plurality of interconnected VLs (117) based on latency determined dynamically for each of the one or more ports (119);
determine a first group of the plurality of data packets to be transmitted through the one or more ports (119) belonging to a primary cluster of the plurality of clusters and a second group of the plurality of data packets to be transmitted through one or more ports (119) belonging to one or more secondary clusters of the plurality of clusters based on the destination VL assigned for each of the plurality of data packets; and
transmit the first group of the plurality of data packets through the one or more ports (119) belonging to the primary cluster and transmitting an acknowledgement key-packet associated with the second group of the plurality of data packets through the one or more ports (119) belonging to the one or more secondary clusters, based on the determination, to the one or more other controllers communicatively connected to the HPC switch (107) for optimizing the distribution of the plurality of data packets in the HPC switch (107).

11. The HPC switch (107) as claimed in claim 10 wherein the processor (109) determines the latency of each of the one or more ports (119) using a performance value computed for each of the one or more ports (119).

12. The HPC switch (107) as claimed in claim 11, wherein the processor (109) computes the performance value based on number of data packets received and transmitted by each of the plurality of interconnected QP lanes (115) for each of the one or more ports (119).

13. The HPC switch (107) as claimed in claim 12, wherein the processor (109) is further configured to recompute the performance value for each of the one or more ports (119) at predefined time intervals, to generate a plurality of new clusters of the one or more ports (119) for transmitting at least one of, the second group of the plurality of data packets stored in a Direct Memory Access (DMA) (121) and a plurality of new data packets received by the HPC switch (107), to one or more other controllers (103).

14. The HPC switch (107) as claimed in claim 10, wherein the processor is further configured to reassign the second group of the plurality of data packets to another destination VL based on a performance value recomputed for each of the one or more ports (119), at predefined time intervals.

15. The HPC switch (107) as claimed in claim 10, wherein the primary cluster among the plurality of clusters comprises the one or more ports (119) having ultra-low latency when compared with a predefined latency threshold, and each of the one or more secondary clusters of the plurality of clusters comprise the one or more ports (119) having high latency when compared with the predefined latency threshold.

16. The HPC switch (107) as claimed in claim 10, wherein the processor (109) generates the acknowledgement key-packet for each of the plurality of data packets, wherein the acknowledgement key-packet comprises at least a key value indicating destination of each of the plurality of data packets.

17. The HPC switch (107) as claimed in claim 16, wherein size of the acknowledgement key-packet is less than size of the corresponding plurality of data packets.

18. The HPC switch (107) as claimed in claim 10, wherein the processor (109) is further configured to store the second group of the plurality of data packets for which the acknowledgement key-packet is transmitted, in a Direct Memory Access (DMA) (121) configured in the HPC switch (107).
Dated this 28th day of March, 2018

SWETHA S N
IN/PA-2123
OF K & S PARTNERS
AGENT FOR THE APPLICANT
, Description:TECHNICAL FIELD
The present subject matter relates generally to networking environment, and more particularly, but not exclusively to a method and a High Performance Computing (HPC) switch for optimizing distribution of data packets.