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Method And System For Bitmap Analysis For High Speed Testing Of Memories

Abstract: The invention provides a Bit Map Analysis System (BMAS) for high-speed memory testing. The solution provided throught this strategy is a worty using inside the embedded memories irrespective of whether they are asynchronous or synchronous, static or dynamic, volatile or non-volatile as reduces the amount of data transaction between the BIST and the tester. The tester clock cycle reduces drastically, resulting in reduced diagnostic process time.

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Patent Information

Application #
Filing Date
31 March 2005
Publication Number
02/2007
Publication Type
INA
Invention Field
ELECTRONICS
Status
Email
Parent Application

Applicants

STMICROELECTRONICS PVT. LTD.,
PLOT NO.2,3&18, SECTOR 16A, INSTITUTIONAL AREA, NOIDA-201 3001, UTTAR PRADESS, INDIA.

Inventors

1. PRASHANT DUBEY
411-B, SHIPRA SUN CITY, INDIRAPURAM, GHAZIABAD, U.P., INDIA

Specification

Documents