Field of the Invention:
This present invention relates to driving of Plasma Display Panel (PDP) and particularly relates to a method and a system for driving an Alternating current (AC) Plasma display panel (hereinafter referred to as ACPDP ) which leads to improvement in addressing for establishing the stable wall charge and reduction of address voltage.
Background of the Invention:
Plasma Display Panel (PDP) is a flat panel display device which is most suitable flat display device for a large size. Generally a PDP fluoresces by an ultraviolet light with a wavelength of 147 nm generated during a discharge of inert gas mixtures (He + Xe, Ne+Xe, He+Xe+Ne) to thereby display a picture including characters and graphics. The display in PDP introduces the digital method of converting image or graphics into millions of pixels which are formed at the intersection of three electrodes namely sustain electrodes, scan electrodes formed on an front plate and address electrodes or data electrodes formed on back plate. A PDP having three electrodes driven by an AC voltage is called AC surface discharge type PDP. The AC surface discharge type PDP has advantages of wide viewing angle, large screen area, high brightness and contrast, and excellent image quality which can now exceed the quality of Color Picture Tubes (CPTs) available in the market.
The PDP electrode has an mxn matrix configuration shown in the FIG. 13. The AC PDP has
address electrodes Al Am in the column direction and Scan electrodes Yl Yn and
Sustain Electrodes X1 Xn in the row direction. Each discharge cell of an AC PDP is formed
at the junction of three electrodes namely scan electrode Y and sustain electrode X formed on a front substrate and address electrode A formed on a back substrate.
Each line of the surface discharge type AC PDP having three electrodes is driven with one frame time by dividing the time into a number of subfields. Each subfield consists of a reset period, an address period and sustain period.
One example of a frame structure for driving AC PDP in Address Display Separated Method is illustrated in FIG.l. Figure 1 shows the display time period of one frame divided into 8 subfields capable of expressing 256(2"8=256) gray levels using 8bit video data corresponding to 8 subfields. One frame time period works out to be 16.67ms corresponding to a frame repetition rate of 60 Hz.
Every subfield is divided into a reset period, address period and sustain period. Reset period is required for initializing an entire screen, means the states of respective on and off pixels from the previous subfield are converted to the off state with a well-established wall voltage to help
smoothly addressing the pixels, In addition this period creates sufficient priming to ensure that there is a discharge during the address phase, an address period is required for selective address discharge and cells that are turned on and the cells that are turned off are selected and wall charges are accumulated on the cells that are turned on (that is addressed cell) and finally the sustain period is required for creating sustain discharge at the selective cells by application of sustain pulses thereby causing a surface discharge between X and Y electrodes resulting actual luminance or brightness.
The reset period erases the majority of wall charges accumulated on the dielectric surface during the previous subfield and produces a near-neutral, initial surface condition before the address period. This condition occurs as a result of a continuous weak discharge caused by the ramp waveform. The remaining wall charges on the dielectric surface are required to assist the address discharge.
The reset period is divided into ramp up and ramp down phase. During the ramp up phase, the positive going ramp voltage waveform is applied to create weak discharge at each pixel site. This discharge causes accumulation of wall charges of positive (+) polarity on the address electrode A and the wall charges of negative (-) polarity on the scan electrode Y. A small amount of wall charge of positive polarity (+) accumulates on the sustain electrode X because the sustain electrode is maintained at the ground voltage.
During the ramp down phase, the negative going ramp voltage waveform is applied to the scan electrode to also create a weak discharge at each pixel site. The positive (+) wall charges on the Sustain Electrode (X) are eliminated by the discharge between the sustain electrode X and the scan electrode Y. During this falling ramp period the negative (-) wall charges accumulated on the Scan electrode Y are in part transferred to the sustain electrode X. The ramp down portion of the reset pulse causes weak erase discharge at each discharge cell to erase the excess wall charges from the electrodes Y, X and A, so that the remaining wall charges are uniformly distributed and are capable of producing a stable address discharge during the address phase.
The slopes of the ramp voltages are adjusted to ensure that the plasma in each pixel remains in the positive resistance region so as to provide constant voltage drop across the discharged gas, resulting in a predictable wall voltage state.
During the reset period, the ramp up waveform goes up to the high DC voltage ,V reset level from sustain level V sus and during ramp down phase, the ramp down waveform goes down from sustain level V sus to the negative biased voltage (-V y) or to the scan reference voltage V scan level. PDP driving circuit includes one main part of waveform designing i.e. ramp waveforms within reset period maintaining priming particles and wall voltage. Rising and falling Ramp during reset period includes two controllable electronic switches (e.g. MOSFET ) in which external capacitor are connected between Drain and Gate of switch and constant
voltage are applied to the Drain, constant current flows through gate to drain to control the ramp waveform within Linear operative region of switch. Accordingly output waveform having ramp is applied to panel capacitor to maintain slow discharge and forming stable wall voltage.
In address period, negative scanning pulse is sequentially applied to the scan electrode Y and at the same time, positive data pulse is applied to the address electrode A in synchronization with the scanning pulse. The voltage difference between the scan pulse and the data pulse is added to the wall voltage generated in initialization period (i.e. reset period) to produce address discharge within the cells supplied with the data pulse. The scan voltage waveform applied within the scanning period helps to isolate the one row electrode selected by data pulse from another row electrode. For proper addressing the selective discharge is required to select the correct row electrode during address period.
In the sustain period, the sustaining pulse is alternately applied to the scan electrode Y and the sustain electrode X. then the wall voltage within the cells selected by the address discharge is added to the sustain voltage waveform to cause the sustain discharge in only ON cells which constitute the display discharge giving the main light output between the scan electrode and the sustain electrode. No discharge is occurred within the cells which are in the OFF state.
Finally after the sustain discharge has completed, the above process is repeated for the next subfield until the last subfield after which the next row is scanned. In this fashion the complete PDP matrix is addressed and an image is displayed.
The basic problem faced in the prior art due to conventional waveform is the addressing of digital pixels in the panel. The current driving waveform includes the ADS (address display separated) method in driving the AC PDP. In this method, the addressing of pixels in the PDP is held before the display period by means of which the light output is obtained by sustain discharge within the desired selected pixels by the proper addressing. But in conventional waveform proper addressing of cells is not held due to mal discharge occurred between Scan and Sustain electrodes during reset period resulting self erasing light without applying address or data pulse to address electrode. Proper addressing is necessary before the light emission from the selected cells. To achieve the proper addressing, the design of ramp down phase is crucial. In the conventional waveform the ramp down phase is large so that the wall charge formation at each of the discharge cells are not properly stable so unstable low wall voltage produced within the ramp down phase prevents the proper addressing of desired cells. Due to improper addressing low unstable wall voltage generated within the ramp down period, leads to high address voltage requirement to fire the panel and also to sustain the picture.
In US Patent no. RE37, 444E an apparatus and method for driving a display panel is described in which write operation of the display data by a light emission is executed by carrying out a selective write discharge utilizing a memory function, are adapted to execute a write discharge to
all cells and helps to create erase discharge for all cells before selective write discharge. In US Patent no. 7,098, 603 B2 a methods and apparatus for driving a plasma display panel in which a discharge cells are formed to a crossing point of three electrodes X sustain, Y scan and address electrodes includes maintaining the Y scan electrodes lines at a reference level during the reset period and the sustain period ; and addressing the Y scan electrode lines by biasing the Y scan electrode to a first level and simultaneously applying a scan signal to the reference level to Y electrode lines during address period. None of the prior art teachings are able to reduce the address voltage to a lower level.
Object of the invention:
It has been already proposed that the conventional waveform used for driving PDPs is characterized by some great disadvantages of insufficient stability, uniformity, improper addressing of cells, unstable wall charge formation at each of the discharge cells and high address voltage required to fire the panel and an object of the invention is to provide an method and apparatus for driving ACPDP which can overcome the above mentioned disadvantages of conventional driving in ACPDP in which address margin is sufficiently maintained.
The principle object of the invention is to provide a method and a system for driving an alternating current Plasma display panel (ACPDP), where a Dual Slope Ramp Down or Dual Ramp is introduced at Ramp down phase during reset period by applying a driving signal having two successive pulses forming two ramp down slopes, controlled slopes of two ramps down phases and clamped voltage levels of two ramps down resulting in accumulation of large amount of stable wall charge formation on the dielectric surface of the electrodes and large predictable wall voltages which leads to proper addressing and display in the ACPDP
In addition, present invention is to provide a method and a system for driving ACPDP, where a ramp down operation is performed by driving signals having two ramp down pulses for creating a plurality of two discharges, wherein widths and period of pulses and time interval between two pulses i.e. stabilization period are controllable, so that controlled wall charge formation in the discharge cells and uniform distribution of wall charge on ACPDP can be obtained.
Yet another objective of the present invention is to provide a method of driving an Alternating Current Plasma Display Panel (ACPDP) including a plurality of discharge cells each of which has a scan electrode, sustain electrode and address electrode by applying driving signals to said electrodes in which in order to display image information divided into a number of subfields each of which consists of reset period, address period and sustain period comprising the steps of: applying drive signals having two short ramp down pulses during ramp down phase ,addressing the said discharge cells by applying a data pulse voltage with in range of 20 to 25V according to present invention for making stable selective discharge during address period.
Preferably, magnitude of wall charge or wall voltage is controlled by controlling stabilization period between two ramp down pulses and also controlling the clamped voltage levels of two ramp down slopes in the driving waveform.
Preferably, stable high wall charge formation or high wall voltage is generated during ramp down phase by giving dual ramp down waveform to PDP in which voltage rate of change or ramp rate (dv/dt) should be controlled to reach optimized condition of addressing in the panel resulting low address voltage applied to address electrode through low voltage, low cost address driver circuit.
Preferably, two weak discharges occur due to two ramp down pulses applied to scan electrode during ramp down phase of reset period to erase wall charges accumulated on the scan electrode in excess during previous period and builds new wall charges on the scan electrode associated with sustain and address electrode greatly and to assist the proper addressing of cells in the panel smoothly.
STATEMENT OF THE INVENTION:
Accordingly the invention provides a method of driving an Alternating Current Plasma Display panel (ACPDP) having three electrodes including a discharge cells at the intersection point of the three electrodes, Address, Scan and Sustain electrode by applying driving signals to electrodes and in order to display information on AC PDP. One frame of image information is divided into a number of subfields and each subfield has reset period, address period and sustain period comprising the steps of Applying driving signals during a ramp up phase and two successive pulses to said scan electrode during a ramp down phase of the reset period resulting in a dual slope ramp down waveform; Addressing the discharge cells by applying address pulses to said address electrode to enable selective discharge of said discharge cells during the address period; Controlling slopes and clamped voltage levels of said two successive ramp down leads to accumulation of large amount of stable wall charges on the dielectric surface of the said electrodes generating a stable high wall voltage. Controlling stabilization period between said two successive ramp down leads to controlled wall charge formation in the discharge cells and uniform distribution of wall charge on said electrodes; Varying said slopes of dual ramp down waveform maintaining flexibility between negative biased voltage level and scan voltage level. Controlling Voltage rates of change for ramp up 1.5 V/us to 2.3 V/us , more preferably within range of 1.6 V/us to 1.9 V/us and for said two successive ramp down phase within range of 2.6 V/us to 4.6 V/us and 0.8 V/us to 1.5 V/us respectively.
Applying highly reduced X shelf voltage to said sustain electrode leads to production of weak discharge during reset period, generating said stable high wall voltage to reduce highly address voltage applied to said address electrode during address period to enable the stable selective address discharge on said discharge cells, which leads to proper addressing and display in the ACPDP and Applying sustain voltage to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in the ACPDP.
The Present invention also provide a system for driving an Alternating Current plasma display panel (ACPDP) comprising a driving circuit having two switches 1st ramp down switch and 2nd ramp down switch , resistances, variable resistances and capacitances for forming dual slope ramp down; means for controlling the driving voltage pulses to sustain, scan and address electrodes; means for applying driving signals during a ramp up phase and two successive pulses to said scan electrode during a ramp down phase of the reset period resulting in a dual slope ramp down waveform; means for Addressing the discharge cells by applying address pulses to said address electrode to enable selective discharge of said discharge cells during the address period; means for applying sustain voltage to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in the ACPDP for Controlling slopes and clamped voltage levels of said two successive ramp down leads to accumulation of large amount of stable wall charges on the dielectric surface of the said electrodes generating stable high wall voltage and reducing highly address voltage applied to said address electrode during address period to enable the stable selective address discharge on said discharge cells, which leads to proper addressing and display in the ACPDP; for selectively Controlling stabilization period between said two successive ramp down leads to controlled wall charge formation in the discharge cells and uniform distribution of wall charge on said electrodes; for selectively Varying said slopes of dual ramp down waveform maintaining flexibility between negative biased voltage level and scan voltage level; for selectively Controlling Voltage rates of change for ramp up 1.5 V/us to 2.3 V/us , more preferably within range of 1.6 V/us to 1.9 V/us and for said two successive ramp down phase within range of 2.6 V/us to 4.6 V/us and 0.8 V/us to 1.5 V/us respectively and for selectively applying highly reduced X shelf voltage to said sustain electrode leads to production of weak discharge during reset period.
Brief descriptions of the Drawings:
Fig.l illustrates the single frame structure, corresponding number of subfields (SF1-SF8), three division periods and Sustain distributions of corresponding subfield used in the PDP driving.

Fig.2 illustrates the conventional driving waveform applied to three electrodes, Y scan, X sustain and A address used in the PDP.
Fig.3 illustrates a waveform showing Dual Slope or Double Ramp Down instead of single Ramp Down period and second ramp down clamped to ground potential and Xshelf Voltage level starts at the first ramp down slope in driving an AC PDP in accordance with the preferred embodiment of the present invention.
Fig.4 illustrates a driving waveform showing Dual Slope or Double Ramp Down instead of single Ramp Down period and second ramp down clamped to some negative potential from ground level and X shelf Voltage starts at the First ramp down in driving an AC PDP in accordance with second preferred embodiment of the present invention.
Fig.5 illustrates a waveform showing Dual Slope or Double Ramp Down instead of single Ramp Down period and second ramp down clamped to ground potential and Xshelf Voltage level starts at the Second ramp down slope in driving an AC PDP in accordance with the third preferred embodiment of the present invention.
Fig.6 illustrates a driving waveform showing Dual Slope or Double Ramp Down instead of single Ramp Down period and second ramp down clamped to some negative potential from ground level and X shelf Voltage starts at the Second ramp down in driving an AC PDP in accordance with fourth preferred embodiment of the present invention.
Fig.7 illustrates a driving waveform showing Dual Slope or Double Ramp Down instead of single Ramp Down period and first ramp down clamped to some positive potential from ground level and X shelf Voltage starts at the first ramp down in driving an AC PDP in accordance with fifth preferred embodiment of the present invention.
Fig.8 illustrates a new driving waveform with two Ramp down signal pulses by which double ramps are formed.
Fig.9 illustrates a new driving waveform with single Ramp down signal having two pulses by which double ramps are formed.
Fig. 10 illustrates a System for driving an AC PDP having a scan amplifier operation unit in accordance with the present invention.
Fig. 11 illustrates outline of driving Circuit for Dual slope Ramp Waveform at hardware level design.
Fig. 12 illustrates outline of driving Circuit for Dual slope Ramp Waveform at hardware level design in another way having single ramp down switch.
Fig. 13 illustrates the System for driving with electrode arrangements in horizontal and vertical direction of a surface discharge type an AC PDP and discharge cell formation at the crossing point of three electrodes.
Detailed descriptions of the invention with reference to the drawings:
In the following description, the object of this invention is described in according to the accompanying drawings. This invention is capable of modification of various obvious drawbacks of the conventional AC PDP in reference to the following drawings and descriptions.
The New Driving Method of surface discharge type AC PDP according to the present invention will be described in Fig.3, Fig.4, Fig.5, Fig.6 and Fig.7 illustrate the new waveform diagram showing double ramp or dual slope within single ramp down period in driving AC PDP in accordance with the present invention.
The resolution of SDPDP (standard definition PDP) is illustrated as an example which is 852x480 where 852x3=2556 vertical lines i.e. the address lines(Red, Green and Blue) coming from address driver, 480 horizontal lines coming from scan and sustain driver respectively .
Figure. 1 illustrates the frame structure as well as subfield methods used in the AC PDP. This subfield method uses a number of subfields divided from 1 frame (16.67ms) for displaying image. This figure illustrates one frame is divided into 8 subfields SF1-SF8 for 8 bit data. All subfields have assigned luminance level based on the binary code 1(2°), 2(2'), 4(22), 8(23), 16(24), 32(25), 64(26), 128(27) in the sustain period for 8bit video data.
Figure 2 illustrates the conventional driving waveform of surface discharge type AC PDP. In this figure, the driving voltage waveforms are applied to the corresponding three electrodes Y scan, X sustain and A address. The driving scheme includes number of subfields and each subfield introduces three periods such as reset period, address period and sustain period. During one subfield three driving waveforms are applied simultaneously to three electrodes. During the reset period, the scan waveform (Y scan) introduces ramp up and ramp down stage, the ground voltage is maintained to the sustain electrode(X sustain) at 0 volt during ramp up phase and for
address electrode (A address) ground voltage is maintained at 0 volt during Reset period. Before starting of ramp down phase the "X shelf Voltage (V x shelf)" which is equal to sustain voltage or less than sustain voltage is applied to the sustain electrode (X sustain) during whole address period. During address period, the negative scan pulse is applied to the scan electrode for scanning the address lines and simultaneously the positive address pulse of address voltage (e.g. 70V) is applied to the address electrode for selecting the particular line. During the Sustain period, the alternating sustaining pulses are applied to the scan and sustain electrode for creating sustain discharge of selected cells resulting actual luminance i.e. Display Luminance means brightness.
In the reset period, reset pulse of ramp up waveform is provided to the scan electrode Y during ramp up phase that rises from scan base voltage level ,Vsus(e.g. 200V) to predetermined reset voltage level ,V reset(e.g. 220V). The reset pulse of ramp up waveform causes priming discharge during ramp up phase at the discharge cells in the entire screen. The ramp up discharge serves to build the wall charges on the dielectric surface of three electrodes.
The reset pulse of ramp down waveform is provided to the scan electrode Y during ramp down period that goes down from scan base voltage level ,Vsus( e.g. 200V) to negative bias voltage level, -V y( e.g. -80V).The reset pulse of ramp down waveform causes ramp down discharge which is weak erasure discharge at each of the discharge cell to erase a portion of the excessive wall charges from the electrode Y, X and A respectively and simultaneously serve to build surface conditions having uniform wall charges for stable address discharge which leads to proper selection of cells for addressing.
The pulse of X shelf voltage waveform is applied to the Sustain electrode X starting from earlier ramp down period to the end of address period that rises from ground potential (0V) to the sustain voltage or less than sustain voltage say V xshelf (e.g. 185V).This voltage waveform introduces the sharp transition that controls the strong light emission during the reset period. In the address period, the negative pulse of scanning voltage waveform Vscan (e.g. 80V) is applied to the scan electrodes Y and simultaneously the positive pulse of address voltage V add (e.g.70V) is applied to the address electrodes A .The resultant voltage is added to the wall voltage generated after ramp down discharge leads to stable address discharge for selecting the cells.
In sustain period, the alternating pulses of sustain voltage waveform are applied to the scan Y and sustain X electrode. The sustain voltage V sus (e.g.200V) is added to the wall voltage produced during address period enough to create the strong sustain discharge i.e. surface discharge between the scan Y and sustain X electrode resulting main light output i.e.dispaly Luminance from the selected ON cells.
The conventional driving waveform of AC PDP of figure 3 has some drawbacks based on the performance of panel. High address voltage, V adds (e.g.70V) is applied to address electrode during address period through high cost TCP (Tape Carrier Packages) based address driver circuit. In these circuits high cost driver IC's are used for handling high address voltage and generates high frequency switching noise in the Data Driver board which leads to improper addressing of desired pixels in the panel. Wall voltage generated during long ramp down phase is low and unstable, so high address voltage (V add) is needed i.e. 70V for addressing. Figure 3 illustrates the new driving voltage waveform having Double ramp or Dual Slope Ramp Down phases instead of Single Ramp Down phase of reset period .The X shelf Voltage waveform is applied at the starting of first ramp down (12) clamped to ground potential (0V) and second ramp down (13) is clamped to negative scan biased voltage (e.g. -V y= -90 to -130V) in driving waveform in accordance with first embodiment of present invention. In present waveform the X shelf voltage, V Xshelf (e.g. 150V to185V) and also simultaneous change of Negative Bias Voltage, -Vy (e.g. -120V to -150V) are applied to the sustain and scan electrodes during reset and address period resulting of lower reset voltage, V reset (e.g. 155V to 180V) applied to scan electrode during ramp up phase in the full sustaining condition of panel. According to present invention Two Slopes of Dual ramp down phase Trdl(Time period of 1st ramp down)(for e.g.Trd1=50us) and Trd2(Time period of Second ramp down)(for e.g.Trd2=100us) in the driving waveform are introduced in such a way that first slope (12) is so fast and second slope (13) is so slow with respect to each other so that it maintains stabilization period (12a) of 5 to 14us between two slopes to meet optimized condition of panel resulting more stable wall charge accumulated on the electrodes producing more wall Voltage reducing address voltage. Varying slopes of dual ramp down waveform having a voltage difference (AVI) within range of +20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility. The address voltage V add is reduced from conventional applied voltage which is generally applied within range of 60V to 70V to 20V - 25V resulting in stable selective discharge during full firing condition in the panel.
Figure 4 illustrates the another aspect of New driving voltage waveform having Dual Slope Ramp Down phase instead of Single Ramp Down phase of reset period . The X shelf Voltage waveform is applied at the starting of first ramp down (14) clamped to some Negative potential (for e.g. AVB= -30V) from ground level and second ramp clown (14b) is clamped to negative scan biased voltage (for e.g. -V y= -90 to -130V) in driving waveform in accordance with present invention. According to present invention two Slopes of Dual ramp down phase Trdl(Time period of 1st ramp down)(for e.g.Trdl=50us) and Trd2(Time period of Second ramp down)(for e.g.Trd2=100us) in the driving waveform are introduced in such a way that first slope (14) is so fast and second slope (14b) is so slow with respect to each other so that it maintains stabilization period (14a) of 5 to 14us between two slopes to meet optimized condition of panel resulting more stable wall charge accumulated on the electrodes producing more wall Voltage reducing address voltage. Varying slopes of dual ramp down waveform having a voltage
difference (AVI) within range of+20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility. The address voltage V add is reduced from conventional applied voltage 60V to 70V is applied within range of 20V - 25V resulting in stable selective discharge during full firing condition in the panel.
Figure 5 illustrates the third aspect of New driving voltage waveform having Dual Slope Ramp Down phase instead of Single Ramp Down phase of reset period. The X shelf Voltage waveform is applied at the starting of Second ramp down clamped to negative scan biased voltage (e.g. -V y= -90 to -130V) and first ramp down is clamped to ground potential (0V) in driving waveform in accordance with present invention. According to present invention two Slopes of Dual ramp down phase Trdl(Time period of 1st ramp down)(for e.g.Trdl=50us) and Trd2(Time period of Second ramp down)(for e.g.Trd2=100us) in the driving waveform are introduced in such a way that first slope (15) is so fast and second slope (17) is so slow with respect to each other so that it maintains stabilization period (16) of 5 to 14us between two slopes to meet optimized condition of panel resulting more stable wall charge accumulated on the electrodes producing more wall Voltage reducing address voltage. Varying slopes of dual ramp down waveform having a voltage difference (AVI) within range of+20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility. The address voltage V add is reduced from conventional applied voltage which is generally applied within range of 60V to 70V to 20V - 25V resulting in stable selective discharge during full firing condition in the panel.
Figure 6 illustrates the fourth aspect of new driving voltage waveform having Dual Slope Ramp Down phase instead of Single Ramp Down phase of reset period. The X shelf Voltage waveform is applied at the starting of Second ramp down clamped to negative scan biased voltage (e.g. -V y= -90 to -130V) and first ramp down is clamped to some Negative potential (e.g. AVB= -30V) from ground level in driving waveform in accordance with present invention. According to present invention two Slopes of Dual ramp down phase Trdl(Time period of 1st ramp down)(for e.g.Trdl=50us) and Trd2(Time period of Second ramp down)(for e.g.Trd2=100us) in the driving waveform are introduced in such a way that first slope (18) is so fast and second slope (20) is so slow with respect to each other so that it maintains stabilization period (19) of 5 to 14us between two slopes to meet optimized condition of panel resulting more stable wall charge accumulated on the electrodes producing more wall Voltage reducing address voltage. Varying slopes of dual ramp down waveform having a voltage difference (AVI) within range of+20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility. The address voltage V add is reduced from conventional applied voltage which is generally applied within range of 60V to 70V to 20V - 25V resulting in stable selective discharge during full firing condition in the panel.
Figure 7 illustrates fifth aspect of New driving voltage waveform having Dual Slope Ramp Down phase instead of Single Ramp Down phase of reset period. The X shelf Voltage waveform is applied at the starting of first ramp down (16a) clamped to some positive voltage from ground level (e.g. AV=50V) and second ramp down (22) is clamped to negative scan biased voltage (e.g. -V y= -90 to -130V) in driving waveform in accordance with present invention. According to present invention two Slopes of Dual ramp down phase Trdl(Time period of 1st ramp down)(for e.g.Trdl=50us) and Trd2(Time period of Second ramp down)(for e.g.Trd2=100us) in the driving waveform are introduced in such a way that first slope (21) is so fast and second slope (22) is so slow with respect to each other so that it maintains stabilization period (21a) of 5 to 14us between two slopes to meet optimized condition of panel resulting more stable wall charge accumulated on the electrodes producing more wall Voltage reducing address voltage. Varying slopes of dual ramp down waveform having a voltage difference (AVI) within range of +20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility .The address voltage V add is reduced from conventional applied voltage which is generally applied within range of 60V to 70V to 20V - 25V resulting in stable selective discharge during full firing condition in the panel. It also reduces the black luminance resulting in increase of dark room contrast at great extent by setting stabilization period (16b) after first ramp down period is 5 to 14us and after that second ramp down starts.
Figure 8 illustrates a method for generating the new driving waveform having two ramp down signals Y ramp downl and Y ramp down 2 forming Dual slope ramp down phase instead of single ramp down phase. The pulse width of (Trdl) 50us is given for first ramp down and pulse width of (Trd2) 86 to 95us is given for second ramp down and the stabilization period between two ramp downs (e.g. AT) is 5 to 14us.
Figure 9 illustrates a method for generating new driving waveform with single ramp down signal i.e. Y ramp downl having two pulses of first ramp down pulse width (Trdl) is 50us and second ramp down pulse width (Trd2) is 86 to 95us by which dual ramp is formed and the stabilization period between two pulses (e.g. AT) is 5 to 14us.
Figure 10 is a system for driving illustrating a scan amplifier operation unit (22H) consisting of sustaining circuit (22G) for making sustaining waveform and it is passed through two switches (Metal Oxide Semiconductor Field Effect Transistor, MOSFET or Insulated Gate Bipolar Transistor, IGBT) ,Pass Bot (22A) and Pass Top (22C). The ramp up waveform of reset voltage V reset is superimposed on the output waveform of sustaining unit (22G) with help of ramp up switch (22B) and first ramp down waveform is made to clamp at GND, - AVB or AV at the output waveform with help of first ramp down switch (22E) and second ramp down waveform is made to clamp at -Vy at the output waveform with help of second ramp down switch (22F). The composite output waveform of scan amplifier unit is applied to panel capacitor (22D).
Figure 11 illustrates the Electronic circuit diagram of Dual slope Ramp down waveform by which dual ramp down is formed. The circuit comprising two switches (MOSFET) lsl ramp down switch and 2nd ramp down switch with passive components such as resistance(R),variable resistance(VR) and capacitance(C) by which dual slope ramp down is formed. Here ramp waveform is formed by connecting the external capacitor between Gate and Drain of MOSFET Switch which operates in the linear region where constant current flows from gate to drain of MOSFET and constant voltage is applied to drain of the MOSFET switch. The ramp rate is controlled by varying the variable resistors (VR1 & VR2) Tuned with interconnected capacitors (Cl & C2) between gate and drain of MOSFET. For turning On and Off in controlled manner ramp down signals (1st ramp dn signal & 2nd ramp dn signal) are applied to 1st ramp down switch and 2nd ramp dn switch respectively through individual gate opto driver for making dual or double ramp, 1st ramp down switch forms 1st ramp down waveform at V sustain level to ground (0V) or some positive (e.g. AV= 30 to 50V) or negative voltage (e.g. Vyl= -30V) level with respect to ground, maintaining ramp rate of 50us by controlling variable resistor(VRl) with external capacitor (Cl) and 2nd ramp down switch forms 2nd ramp down waveform at first ramp down clamped level to negative scan biased level (e.g. -V y= 90V to 130V) and ramp rate is maintained at 86 to 95us by controlling variable resistor(VR2) with external capacitor (C2). Here output from drain of the MOSFET switch is connected to panel capacitor (Cp).
Figure 12 shows another circuit diagram of double ramp or dual slope ramp down phase. The circuit comprising single switch Ramp down switch having same passive components resistors (R), variable resistor (VR), and capacitors (C). The ramp waveform is formed by connecting the external capacitor (C4 & C3) between gate and drain of ramp down MOSFET switch operating in the linear region where constant current flows from gate to drain and constant voltage is applied across drain of the MOSFET switch. In present circuit instead of two switches, single switch is used to make dual ramp down by connecting extra components like Zener Diode (D4) with shunted capacitor (C4) between gate and drain of MOSFET switch. For turning On and Off the MOSFET switch, Dual pulse ramp down (1st pulse width =50us and 2nd pulse width= Time period of Second ramp down Trd2 +address period) signal is applied to the gate of the MOSFET switch through gate Opto driver. The OFF time interval between two pulses of ramp down signal i.e. stabilization period according to present invention is 5 to 14us. According to operation of circuit when the ramp down switch is turned on by first ramp down pulse, Zener diode breaks down to its break down voltage and constant current flows from gate to drain through Capacitors (C4 & C3) for making first ramp down clamped to Zener break down voltage level and ramp rate 50us is achieved by adjusting series capacitor (C3 & C4) with variable resistor VR3.The clamped level will be maintained during whole stabilization period (i.e. 5 to14us).
During second ramp down pulse Zener diode is forward biased to flow constant current from gate to drain through capacitor (C3) to make second ramp down clamped to negative scan biased voltage (e.g. -V y= 90 to 130V) and ramp rate 86us to 95us is achieved by adjusting capacitor C3 with variable resistor VR3. Here by using Zener diode first ramp down is clamped to some
positive voltage from ground level. Output from drain of the MOSFET switch is connected to panel capacitor (Cp).
Ramp rate of ramp up phase is 1.5 V/us to 2.3 V/us and more preferably within range of 1.6 V/us to 1.9 V/us and ramp rate of lst ramp down phase within range of 2.6 V/us to 4.6 V/us and ramp rate of 2nd ramp down phase within range of 0.8 V/us to 1.5 V/us according to present invention. Figure 13 illustrates the system for driving an AC PDP in present invention .The discharge cell (23) is formed at the crossing point of three electrodes Scan Y, Sustain X and Address A is called sub pixel; one digital pixel i.e. color picture element consists of three sub pixels . The system for driving an AC PDP comprising power supply, video section and three drivers Scan, Sustain and Address driver integrated with logic timing controller. First the video section provides the digital bits to the logic controller board which generates all control signals for Scan, Sustain and Address drivers and driving sequentially Scan, Sustain and Address electrodes. The system for driving the display panel comprises driving means for supplying a plurality of driving voltage pulses and control means which controls a sequence of supplying a plurality of driving voltage pulses.
The address driver supplies the data signal voltage or address voltage of 20V to 25V to address electrodes Al to Am resulting in stable selective discharge during address period after gamma correction and image processing under control of timing controller. According to present invention, due to reduction of address Voltage to 20-25V , the complexity of address driver circuit is reduced to great extent resulting low switching noise and driver circuit comprising of low voltage or low power CMOS driver which reduces the total cost as compared to conventional address driver circuit.
The Logic controller board supplies the timing and control signals to scan amplifier board (24) comprising four parts scan voltage control circuit, ramp up circuit, First ramp down and Second ramp down circuit. The composite output of scan amplifier has been gone to scan driver board where the scan voltage waveform of pulse width 1.5us and amplitude 120V is superimposed on the output waveform of scan amplifier board through a high voltage scan driver 1C. As elaborately, the Scan module (scan amplifier plus scan driver) applies a ramp up signal waveform which is rising up to a reset voltage V reset (e.g. 160 to!90V), first ramp down waveform is falling down to voltage range (e.g. +50V to -30V) and Second ramp down waveform falling until negative scan biased voltage -Vy (e.g. -90 to -130V) during reset period. The said waveform is applied to the scan electrodes Yl to Yn under control of timing controller to initialize the entire screen. Controlling Voltage rates of change for ramp up phase 1.6 V/us to 1.9 V/us and Voltage rates of change for first ramp down phase within range of 2.6 V/us to 4.6 V/us and second ramp down phase within range of 0.8 V/us to 1.5 V/us and maintaining stabilization period at 5 to 14 us between two successive ramp down phases according to present invention. Varying slopes of dual ramp down waveform having a voltage difference (AVI) within range of +20V to +50V between negative biased voltage level and scan voltage level for maintaining flexibility. Further the scan module sequentially applies the scanning pulse of scan
voltage (e.g. 120V) to scan electrodes falling from ground voltage (0V) to negative scan voltage level -Vy during the address period to select the scan line. Again the scan driver supplies simultaneously the sustain pulses of sustain voltage level V Sus (e.g. 180V - 200V) to scan electrodes Y1 to Yn to provide the brightness during the sustain period.
The sustain Driver applies a pulse of X shelf voltage(e.g. V xshelf=105V to 160V) waveform at the starting of first ramp down phase of reset period and still continues to the whole address period to Sustain electrodes X1 to Xn under control of timing controller. Also the X shelf Voltage (e.g. V xshelf=105V to 160V) waveform can be applied at the starting of second ramp down phase and still continues to whole address period to Sustain electrodes X1 to Xn under control of timing controller. Further the sustain driver simultaneously applies the sustain pulses of sustain voltage level V Sus (e.g. 180 to 200V) to Sustain electrodes X1 to Xn and operates alternatively with the scan driver for creating sustain discharge within the cell resulting actual luminance or brightness..
In the above new driving waveform of present invention, dual slope ramp down phase of first slope is made so faster and second slope is made so slower to each other resulting in reduction of address voltage to 20V to 25V as compare to conventional applied address voltage of 60V to 70V within the address period at full firing condition of panel. The address voltage V address (V breakdown - V wall) decreases as V wall increases due to large amount of opposite wall charges accumulated on the scan and address electrodes by weak erasure discharge within two ramp down phases (1st and 2nd ramp down). The V breakdown is the inert gas break down voltage between Y scan and A address for facing discharge. The increase in wall voltage leads to decrease in address voltage. The reduction of address voltage V add to 20 to 25V results in reduction of high voltage switching noise in the data driver circuit and use of cheap low voltage address driver or CMOS driver for driving data pulse in the circuit.
Although the invention has been described with reference to specific embodiments, this description is not meant to be construed in limiting sense .Various modifications of the disclosed embodiments, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the present invention as defined.

We claim:
1. A method of driving an Alternating Current Plasma Display panel (ACPDP) having three electrodes including a discharge cells at the intersection point of the three electrodes, Address, Scan and Sustain electrode by applying driving signals to said electrodes and in order to display information on the AC PDP, one frame of image information is divided into a number of subfields and each subfield has reset period, address period and sustain period, comprising the steps of:
Applying driving signals during a ramp up phase and two successive pulses to said scan electrode during a ramp down phase of the reset period resulting in a dual slope ramp down waveform;
Addressing the discharge cells by applying address pulses to said address electrode to enable selective discharge of said discharge cells during the address period;
Controlling slopes and clamped voltage levels of said two successive ramp down leads to accumulation of large amount of stable wall charges on the dielectric surface of the said electrodes generating a stable high wall voltage ;
Controlling stabilization period between said two successive ramp down leads to controlled wall charge formation in the discharge cells and uniform distribution of wall charge on said electrodes;
Varying said slopes of dual ramp down waveform maintaining flexibility between negative biased voltage level and scan voltage level;
Controlling Voltage rates of change for ramp up 1.5 V/us to 2.3 V/us , more preferably within range of 1.6 V/us to 1.9 V/us and for said two successive ramp down phase within range of 2.6 V/us to 4.6 V/us and 0.8 V/us to 1.5 V/us respectively;
Applying highly reduced X shelf voltage to said sustain electrode leads to production of weak discharge during reset period;
Generating said stable high wall voltage to reduce highly address voltage applied to said address electrode during address period to enable the stable selective address discharge on said discharge cells, which leads to proper addressing and display in the ACPDP

Applying sustain voltage to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in the ACPDP.
2. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein, said clamped voltage for a first ramp down is applied with in range of+50V to -50 V and for a second ramp down with in range of-90 V to -150 V, more preferably within the range of- 100V to -135V to said scan electrode resulting in controlled discharge during reset period.
3. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein, said stabilization period between said two successive ramp down is maintained within range of 5us to 14us.
4. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein, said flexible slopes of dual ramp down is maintaining a voltage difference with in range of + 20V to +50V between said negative biased voltage level and scan voltage level.
5. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein, said Xshelf voltage waveform is applied at the starting point of said first ramp down within range of 105V to 150V to said sustain electrode.
6. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein, said Xshelf voltage can be applied at the starting point of said second ramp down within range of 105V to 150V to said sustain electrode.
7. A method of driving an Alternating Current Plasma Display panel (ACPDP) as claimed in claim 1, wherein said address voltage is applied within a range of 20V to 25V to said address electrode during said address period resulting in stable selective address discharge
8. A System for driving Alternating Current plasma display panel (ACPDP) comprising:
a driving circuit having two switches 1st ramp down switch and 2nd ramp down switch resistances, variable resistances and capacitances for forming dual slope ramp down , means for controlling the driving voltage pulses to sustain, scan and address electrodes

means for applying driving signals during a ramp up phase and two successive pulses to said scan electrode during a ramp down phase of the reset period resulting in a dual slope ramp down
waveform;
means for Addressing the discharge cells by applying address pulses to said address electrode to enable selective discharge of said discharge cells during the address period;
means for applying sustain voltage to both said scan and sustain electrodes alternately during sustain period creating sustain discharge in said selected cells leads to formation of display luminance in the ACPDP;
wherein,
Controlling slopes and clamped voltage levels of said two successive ramp down leads to accumulation of large amount of stable wall charges on the dielectric surface of the said electrodes generating stable high wall voltage and reducing highly address voltage applied to said address electrode during address period to enable the stable selective address discharge on said discharge cells, which leads to proper addressing and display in the ACPDP;
selectively Controlling stabilization period between said two successive ramp down leads to controlled wall charge formation in the discharge cells and uniform distribution of wall charge on said electrodes;
Selectively Varying said slopes of dual ramp down waveform maintaining flexibility between negative biased voltage level and scan voltage level;
Selectively Controlling Voltage rates of change for ramp up 1.5 V/us to 2.3 V/us , more preferably within range of 1.6 V/us to 1.9 V/us and for said two successive ramp down phase within range of 2.6 V/us to 4.6 V/us and 0.8 V/us to 1.5 V/us respectively;
Selectively applying highly reduced X shelf voltage to said sustain electrode leads to production of weak discharge during reset period.
9. The system as claimed in claim 8, wherein, said clamped voltage for a first ramp down is applied with in range of + 50V to -50 V and for a second ramp down with in range of-90 V to
150 V, more preferably within the range of- 100V to -135V to said scan electrode resulting in controlled discharge during reset period.
10. The System as claimed in claim 8, wherein, said stabilization period between said two successive ramp down is maintained within range of 5us to 14us.
11. The System as claimed in claim 8, wherein, said flexible slopes of dual ramp down is maintaining a voltage difference with in range of+20V to +50V between said negative biased voltage level and scan voltage level.
12. The System as claimed in claim 8, wherein, said Xshelf voltage waveform is applied at the starting point of said first ramp down within range of 105V to 150V to said sustain electrode.
13. The System as claimed in claim 8, wherein, said Xshelf voltage can be applied at the starting point of said second ramp down within range of 105V to 150V to said sustain electrode.
14. The System as claimed in claim 8, wherein, said address voltage is applied within a range of 20V to 25V to said address electrode during said address period resulting in stable selective address discharge
15. The System as claimed in claim 8, wherein, said driving circuit having one switch, Zener diode, resistances, variable resistances and capacitances for forming dual slope ramp down
16. A method of driving an Alternating Current Plasma Display panel (ACPDP) substantially herein described with reference to the accompanying drawings.
17. A System for driving an Alternating Current Plasma Display panel (ACPDP) substantially herein described with reference to the accompanying drawings.