[001] This disclosure relates generally to digital or software product development (DSPD), and more particularly to method and system for evaluating stages in a DSPD cycle through quality gates.
Background
[002] Digital or software product development (DSPD) may be organized as a sequence of development workflows or phases. With the phenomenal growth of information technology (IT), several development models such as, waterfall, spiral, iterative, agile, and the like are developed. At present, among all models, an agile methodology is the most popular model that is used widely. The digital product development models may have common activities of analysis, design, development, testing, and deployment.
[003] Several techniques are available in the market which may evaluate activities that may be involved in DSPD. However, in such conventional techniques, if the output/deliverable of one phase/stage in DSPD cycle includes a fault, then the entire process may carry out the fault till the end. As a result, cost and time requirement for eliminating risk is more.
[004] Therefore, there is a need for improved methods and systems for evaluating stages in a digital or software development cycle through quality gates which may provide early identification of the risks resulting in higher quality and lower cost of product development.
SUMMARY
[005] In an embodiment, a method for evaluating stages in a digital or software product development (DSPD) cycle through quality gates is disclosed. In one example, the method may include receiving a plurality of predefined quality parameters corresponding to each of a set of quality gates. Each of the plurality of predefined quality parameters may include a set of predefined values, and each of the set of quality gates corresponds to each of a plurality of stages of the DSPD cycle. For each of the set of quality gates and for each of the plurality of corresponding stages, the method may further include, sending input data to an associated quality gate upon completing a corresponding stage of the DSPD cycle. The input data may include an end product of the corresponding stage. The method may further include activating the associated quality gate upon receiving the input data of the corresponding stage. The method may further include evaluating the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results.
[006] In another embodiment, a system for evaluating stages in a DSPD cycle through quality gates is disclosed. In one example, the system may include a DSPD evaluation device comprising a processor and a computer-readable medium communicatively coupled to the processor, wherein the computer-readable medium stores processor-executable instructions, which, on execution, may cause the processor to receive a plurality of predefined quality parameters corresponding to each of a set of quality gates. Each of the plurality of predefined quality parameters may include a set of predefined values, wherein each of the set of quality gates corresponds to each of a plurality of stages of the DSPD cycle. For each of the set of quality gates and for each of the plurality of corresponding stages, the processor-executable instructions, on execution, may further cause the processor to send input data to an associated quality gate upon completing a corresponding stage of the DSPD cycle. The input data may include an end product of the corresponding stage. The processor-executable instructions, on execution, may further cause the processor to activate the associated quality gate upon receiving the input data of the corresponding stage. The processor-executable instructions, on execution, may further cause the processor to evaluate the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results.
[007] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[008] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, serve to explain the disclosed principles.
[009] FIG. 1 is a block diagram of an exemplary system for evaluating stages in a digital or software product development (DSPD) cycle through quality gates, in accordance with some embodiments of the present disclosure.
[010] FIG. 2 is a functional block diagram of an exemplary system for evaluating stages in a DSPD cycle through a quality gate, in accordance with some embodiments of the present disclosure.
[011] FIG. 3 illustrates evaluation of stages in a DSPD cycle through quality gates, in accordance with some embodiments of the present disclosure.
[012] FIG. 4 illustrates an exemplary process for evaluating stages in a DSPD cycle through quality gates, in accordance with some embodiments of the present disclosure.
[013] FIG. 5 illustrates a detailed exemplary control logic for evaluating stages of a DSPD cycle through quality gates, in accordance with some embodiments of the present disclosure.
[014] FIG. 6 illustrates an exemplary user interface depicting a set of predefined values for each of the plurality of predefined quality parameters, in accordance with some embodiments of the present disclosure.
[015] FIG. 7 illustrates an exemplary user interface depicting evaluation results, in accordance with some embodiments of the present disclosure.
[016] FIG. 8 illustrates an exemplary table depicting a plurality of DSPD stages in a DSPD cycle, in accordance with some embodiments of the present disclosure.
[017] FIG. 9 is a table showing quality gate scores corresponding to audits of a DSPD cycle, in accordance with some embodiments of the present disclosure.
[018] FIG. 10 is a graphical representation of quality gate audit score trend, in accordance with some embodiments of the present disclosure.
[019] FIG. 11 is a block diagram of an exemplary computer system for implementing embodiments consistent with the present disclosure.

DETAILED DESCRIPTION
[020] Exemplary embodiments are described with reference to the accompanying drawings. Wherever convenient, the same reference numbers are used throughout the drawings to refer to the same or like parts. While examples and features of disclosed principles are described herein, modifications, adaptations, and other implementations are possible without departing from the spirit and scope of the disclosed embodiments. It is intended that the following detailed description be considered as exemplary only, with the true scope and spirit being indicated by the following claims. Additional illustrative embodiments are listed below.
[021] As used herein, the term “Quality Gate” may be a defined checkpoint to ensure things are working as per defined practices, and no risk is identified till now. More particularly, the quality gate may be a technique to confirm that DSPD (Digital or Software Product Development) measures software development stages by breaking stages into multiple quality parameters. Using quality gate technique, different customizable boundaries for each quality entryway are set to assess each of the stages. The number of quality gates and their boundaries may be customized according to the DSPD model, Risk included, and Quality Focus.
[022] Referring now to FIG. 1, an exemplary system 100 for evaluating stages in a DSPD cycle through quality gates is illustrated, in accordance with some embodiments of the present disclosure. The system 100 may implement a DSPD evaluation device 102, in accordance with some embodiments of the present disclosure. The DSPD evaluation device 102 may evaluate stages in a DSPD cycle through quality gates in applications (such as, software development applications, web applications, etc.) by early identification of the issues resulting in higher quality and lower cost of product development. It should be noted that, in some embodiments, the DSPD evaluation device 102 may evaluate the corresponding stage of the DSPD cycle by identifying at least one of risks, faults, and vulnerabilities for the corresponding stage.
[023] As will be described in greater detail in conjunction with FIGS. 2 – 10, the DSPD device may receive a plurality of predefined quality parameters corresponding to each of a set of quality gates. The plurality of predefined quality parameters may include a set of predefined values. For each of the set of quality gates and for each of the plurality of corresponding stages, the DSPD evaluation device 102 may further send input data to an associated quality gate upon completing a corresponding stage of the DSPD cycle. The input data may include an end product of the corresponding stage. For each of the set of quality gates and for each of the plurality of corresponding stages, the DSPD evaluation device 102 may further activate the associated quality gate upon receiving the input data of the corresponding stage. For each of the set of quality gates and for each of the plurality of corresponding stages, the DSPD evaluation device 102 may further evaluate the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results.
[024] In some embodiments, the DSPD evaluation device 102 may include one or more processors 104 and a computer-readable medium 106 (for example, a memory). The computer-readable medium 106 may include a plurality of requirements corresponding to a plurality of applications. Further, the computer-readable storage medium 106 may store instructions that, when executed by the one or more processors 104, cause the one or more processors 104 to identify common requirements from applications, in accordance with aspects of the present disclosure. The computer-readable storage medium 106 may also store various data (for example, the predefined quality parameters data, set of evaluation results, set of vulnerabilities, and the like) that may be captured, processed, and/or required by the system 100.
[025] The system 100 may further include a display 108. The system 100 may interact with a user via a user interface 110 accessible via the display 108. The system 100 may also include one or more external devices 112. In some embodiments, the DSPD evaluation device 102 may interact with the one or more external devices 112 over a communication network 114 for sending or receiving various data. The external devices 112 may include, but may not be limited to, a remote server, a digital device, or another computing system.
[026] Referring now to FIG. 2, a functional block diagram of an exemplary system 200 for evaluating stages in a DSPD cycle through a quality gate 202 is illustrated, in accordance with some embodiments of the present disclosure. The system 200 may include a DSPD evaluation device 204. In an embodiment, the DSPD evaluation device 204 is analogous to the DSPD evaluation device 102 of the system 100. The DSPD evaluation device 204 includes a quality gate activation module 206, a DSPD stage evaluation module 208, and an evaluation report generation module 210.
[027] The quality gate activation module 206 receives a plurality of predefined quality parameters corresponding to the quality gate 202. Each of the plurality of predefined quality parameters includes a set of predefined values. Further, the quality gate 202 corresponds to one of a plurality of stages of the DSPD cycle. Further, the quality gate activation module 206 sends the input data 212 to the quality gate 202 upon completing a corresponding stage of the DSPD cycle. The input data 212 may include an end product of the corresponding stage. Further, the quality gate activation module 206 activates the quality gate 202 upon receiving the input data 212 of the corresponding stage.
[028] Upon activating the quality gate 202, the DSPD stage evaluation module 208 evaluates the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results. The DSPD stage evaluation module 208 determines one of the set of predefined values for each of the plurality of predefined quality parameters based on the input data received. In some embodiments, the DSPD stage evaluation module 208 identifies at least one of risks, faults, and vulnerabilities for the corresponding stage. In such embodiments, the evaluation results may include the at least one of risks, faults, and vulnerabilities identified for the corresponding stage. In some embodiments, the DSPD stage evaluation module 208 validates compliance of the corresponding stage with respect to one or more of predefined quality standards. In such embodiments, the evaluation results may include compliance details of the corresponding stage.
[029] The quality gate 202 may be a step towards development of a Definition of Ready (DoR) and Definition of Done (DoD) as practiced in agile methodologies. The quality gate 202 may provide a measurable and trackable parameter to ascertain the DoD and DoR. Further, the DSPD stage evaluation module 208 sends the evaluation results to the evaluation report generation module 210. The evaluation report generation module 210 generates an evaluation report based on the evaluation results for the corresponding stage of the DSPD cycle. The evaluation report may include a spreadsheet or a tracking tool where the evaluation results may be visualized, analyzed, and compared.
[030] It should be noted that all such aforementioned modules 202 – 210 may be represented as a single module or a combination of different modules. Further, as will be appreciated by those skilled in the art, each of the modules 202 – 210 may reside, in whole or in parts, on one device or multiple devices in communication with each other. In some embodiments, each of the modules 202 – 210 may be implemented as dedicated hardware circuit comprising custom application-specific integrated circuit (ASIC) or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. Each of the modules 202 – 210 may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), programmable array logic, programmable logic device, and so forth. Alternatively, each of the modules 202 – 210 may be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, include one or more physical or logical blocks of computer instructions, which may, for instance, be organized as an object, procedure, function, or other construct. Nevertheless, the executables of an identified module or component need not be physically located together, but may include disparate instructions stored in different locations which, when joined logically together, include the module and achieve the stated purpose of the module. Indeed, a module of executable code could be a single instruction, or many instructions, and may even be distributed over several different code segments, among different applications, and across several memory devices.
[031] As will be appreciated by one skilled in the art, a variety of processes may be employed for evaluating stages in a DSPD cycle through quality gates. For example, the exemplary system 100 and the associated DSPD evaluation device 204 may evaluate stages in a DSPD cycle by the processes discussed herein. In particular, as will be appreciated by those of ordinary skill in the art, control logic and/or automated routines for performing the techniques and steps described herein may be implemented by the system 100 and the associated DSPD evaluation device 204 either by hardware, software, or combinations of hardware and software. For example, suitable code may be accessed and executed by the one or more processors on the system 100 and the associated DSPD evaluation device 204 to perform some or all of the techniques described herein. Similarly, Application Specific Integrated Circuits (ASICs) configured to perform some or all of the processes described herein may be included in the one or more processors on the system 100.
[032] Referring now to FIG. 3, evaluation of stages in a DSPD cycle through quality gates is illustrated, in accordance with some embodiments. As mentioned above, the DSPD evaluation device 102 of the system 100 may receive a plurality of predefined quality parameters corresponding to each of a set of quality gates. Further, the DSPD evaluation device 102 sends input data as a start point 302 to an associated quality gate 304A upon completing a corresponding stage of the DSPD cycle. The input data may include an end product of the corresponding stage.
[033] Further, the DSPD evaluation device 102 may activate the associated quality gate 304A upon receiving the input data of the corresponding stage. Upon activating the associated quality gate 304A, the DSPD evaluation device 102 may further evaluate the corresponding stage via the activated quality gate 304A based on the plurality of predefined quality parameters to obtain evaluation results.
[034] In one embodiment, each of a set of quality gates corresponding to each of a plurality of stages of the DSPD cycle may be defined through an agile methodology. By way of an example, the quality gates may be a step towards development of a DoR and DoD as practiced in agile methodologies. Each quality gate may provide a measurable and trackable parameter to ascertain the DoD and DoR. This is further explained in detail in conjunction with FIG. 4.
[035] Further, the DSPD evaluation device 102 may generate evaluation results as deliverables 306. The evaluation results may include at least one of risks, faults, and vulnerabilities identified for the corresponding stage. Further, the deliverables 306 from the quality gate 304A may be used as an input for a next quality gate 304B. A system (such as, the system 100) for evaluating stages of a DSPD cycle may include ‘N’ number of quality gates (304A – 304N) in a set of quality gates. In an embodiment, each of the set of quality gates 304A – 304N may sequentially perform evaluation of the stages of the DSPD cycle, i.e., an output of a first quality gate may be used as an input of a second quality gate.
[036] By way of an example, each of the set of quality gates corresponding to each of a plurality of stages of the DSPD cycle may include a defined input and an output. In an embodiment, the input may be items that are required to start a defined quality gate, and output may be deliverables of the defined quality gate. It should be noted that the output/deliverables of one quality gate may be an input or start point of the succeeding quality gate, as depicted at step 304B-304N. It may also be noted that each set of the quality gates may be in synchronization to one another. It may further be noted that the evaluation of a subsequent stage may begin only when evaluation of a preceding stage is completed. In other words, a next quality gate (for example, QG 304B) is activated once previous quality gate (for example, QG 304A) completes evaluating the corresponding stage.
[037] In an alternate embodiment, the quality gate activation module 206 may activate each of the set of quality gates 304A – 304N to evaluate each of the plurality of stages of the DSPD cycle in parallel. Further, a final output of a quality gate may be captured in a spreadsheet or tracking tool, where identified risks may be analyzed and compared.
[038] Referring now to FIG. 4, an exemplary process 400 for evaluating stages in a DSPD cycle through quality gates is illustrated, in accordance with some embodiments. The process 400 may be implemented by the DSPD evaluation device 102 of the system 100. The process 400 includes receiving a plurality of predefined quality parameters corresponding to each of a set of quality gates, at step 402. It may be noted that each of the plurality of predefined quality parameters may include a set of predefined values. Each of the set of quality gates may correspond to each of a plurality of stages of the DSPD cycle.
[039] Further, for each of the set of quality gates and for each of the plurality of corresponding stages, the process 400 includes sending input data to an associated quality gate (such as, the quality gate 304A) upon completing a corresponding stage of the DSPD cycle, at step 404. The input data may include an end product of the corresponding stage. Further, for each of the set of quality gates and for each of the plurality of corresponding stages, the process 400 includes activating the associated quality gate upon receiving the input data of the corresponding stage, at step 406. Further, for each of the set of quality gates and for each of the plurality of corresponding stages, the process 400 includes evaluating the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results, at step 408.
[040] Further, the step 408 of the process 400 includes determining one of the set of predefined values for each of the plurality of predefined quality parameters based on the input data received, at step 410. In some embodiments, the step 408 includes identifying at least one of risks, faults, and vulnerabilities for the corresponding stage, at step 412. In such embodiments, the evaluation results may include at least one of risks, faults, and vulnerabilities identified for the corresponding stage.
[041] In some embodiments , the step 408 of the process 400 includes validating compliance of the corresponding stage with respect to one or more of predefined quality standards, at step 414. In such embodiments, the evaluation results may include compliance details of the corresponding stage.
[042] Further, the process 400 may include generating an evaluation report based on the evaluation results for each of the plurality of stages of the DSPD cycle, at step 416. For example, a final output of quality gate may be captured in a spreadsheet or tracking tool, where identified risks may be analyzed and compared for software development. By way of an example, the quality gate activation module 206 may receive input data from a stage of a DSPD cycle corresponding to quality gate 202. Further, the quality gate activation module 206 may activate the quality gate 202 to perform evaluation of the stage based on the plurality of predefined quality parameters. Further, the activated quality gate 202 may receive the input data from the quality gate activation module 206 and perform evaluation of the stage based on the plurality of predefined quality parameters through the DSPD stage evaluation module 208 to obtain evaluation results. Further, the DSPD stage evaluation module 208 may send the evaluation results to the evaluation report generation module 210. Further, the evaluation report generation module 210 may generate an evaluation report 214.
[043] Referring now to FIG. 5, a detailed exemplary control logic 500 for evaluating stages of a DSPD cycle through quality gates is depicted via a flow chart, in accordance with some embodiments. For evaluating different stages in a DSPD cycle, initially the DSPD cycle may be split into a plurality of stages. In an embodiment, the plurality of stages may be an analysis stage 502, a development stage 504, a testing stage 506, and a deployment stage 508. Each of the plurality of stages may be further divided into a plurality of sub-stages. For example, the analysis stage 502 may be divided into a sub-stage (for example, an analysis sub-stage 502A). The development stage 504 may be divided into a plurality of sub-stages (for example, a development sub-stage 504A, a code quality sub-stage 504B, an integration sub-stage 504C, and a test bench readiness sub-stage 504D). The testing stage 506 may be divided into a sub-stage (for example, a testing sub-stage 506A). The deployment stage 508 may be divided into a sub-stage (for example, a deploy sub-stage 508A).
[044] Further, each of the plurality of sub-stages corresponding to the plurality of stages may include a set of quality gates. As an example, the sub-stage analysis 502 may include a quality gate QG 510. The development sub-stage 504A may include a quality gate QG 512. The code quality sub-stage 504B may include a quality gate QG 514. The integration sub-stage 504C may include a quality gate QG 516. The test bench readiness sub-stage 504D may include a quality gate QG 518. Further, the testing sub-stage 506A may include a quality gate QG 520, and the deploy sub-stage 508A may include a quality gate QG 522.
[045] Further, each of a set of quality gates corresponding to each of a plurality of stages of the DSPD cycle may include a plurality of predefined quality parameters. In an exemplary embodiment, the quality gate QG 510 may include the plurality of parameters (for example, deliverable identification 510A, approval of set of deliverables 510B, prioritization of set of deliverables 510C, and documentation 510D). The quality gate QG 512 may include the plurality of parameters (for example, coding 512A, static code analysis 512B, and unit test scripts 512C). Further, the quality gate QG 514 may include the plurality of parameters (for example, code completion 514A and unit test scripts execution 514B). It may be noted that the evaluation of the corresponding stage of the DSPD cycle may be performed based on the plurality of predefined parameters corresponding to each of the set of quality gates.
[046] In an embodiment, the quality gate QG 510 may be configured to evaluate the analysis stage 502. The quality gates (for example, QG 512 – QG 518) may be configured to evaluate the development stage 504. The quality gate QG 520 may be configured to evaluate the testing stage 506, and the quality gate QG 522 may be configured to evaluate the deployment stage 508. It may be noted that the evaluation of next stage may began only when the evaluation of previous stage gets completed. Further, each of the plurality of predefined quality parameters may include a set of predefined values. This is further explained in detail in conjunction with FIG. 6.
[047] In an embodiment, evaluating the corresponding stage of the DSPD cycle may include identifying at least one of risks, faults, and vulnerabilities for the corresponding stage.
[048] In one embodiment, evaluation results may be obtained for each of the evaluated stage. The evaluation results may include the at least one of risks, faults, and vulnerabilities identified for the corresponding stage. It may be noted that the DSPD stages may inherent risks from their previous quality gate(s).
[049] Upon evaluating the corresponding stage of the DSPD cycle, the DSPD evaluation device 102 may further generate an evaluation report based on the evaluation results for each of the plurality of stages of the DSPD cycle.
[050] Referring now to FIG. 7, an exemplary User Interface (UI) 700 depicting a set of predefined values for each of the plurality of predefined quality parameters is illustrated, in accordance with some embodiments of the present disclosure. As mentioned earlier, each of the plurality of predefined quality parameters may include a set of predefined values. By way of an example, the set of predefined values may include ‘compliant’, ‘partial compliant’, ‘non-compliant’, and ‘NA’.
[051] In one embodiment, the DSPD evaluation device 102 may evaluate the corresponding stage of the DSPD cycle by determining one of the set of predefined values for each of the plurality of predefined quality parameters. In another embodiment, the DSPD evaluation device 102 may evaluate the corresponding stage of the DSPD cycle by validating compliance of the corresponding stage with respect to one or more of predefined quality standards. It may be noted that the compliance details of the corresponding stage may be in the form of evaluation results. It may be noted that the evaluation may be performed development per cycle-wise. Each development cycle may be evaluated, and an output may be recorded.
[052] Referring now to FIG. 8 an exemplary UI 800 depicting evaluation results is illustrated, in accordance with some embodiments of the present disclosure. With reference to FIG. 7, upon evaluating the corresponding stage of the DSPD cycle, the DSPD evaluation device 102 of the system 100 may obtain the evaluation results. In one embodiment, the evaluation results may include the at least one of risks, faults, and vulnerabilities identified for the corresponding stage.
[053] As an example, the exemplary user interface 700 may depict a set of predefined values (for example, partial compliant, compliant, and alike) for each of the plurality of predefined quality parameters (for example, optimized code, code review, unit test scrip creation, automated unit test cases, static code analysis, functional test case, and alike) and the corresponding evaluation results in the form of comments (for example, code is considered optimized when code review, unit test execution, and static code analysis are compliant, few unit test scripts are failed, and alike).
[054] Referring now to FIG. 8, an exemplary table 800 depicting a plurality of DSPD stages in a DSPD cycle, in accordance with some embodiments. The table 700 includes each of the plurality of DSPD stages may include a set of quality gates. Each of the set of quality gates may corresponds to each of a plurality of stages of the DSPD cycle. Further, each of the set of quality gates may include a plurality of checklist. For example, the corresponding quality gate for ‘analysis’ stage of the DSPD cycle may be ‘QG1’, the corresponding quality gate for ‘development’ stage of the DSPD cycle may be ‘QG2’, and so on. Further, the table 800 includes a corresponding checklist for each of the plurality of DSPD stages.
[055] In an embodiment, the present techniques may primarily centered around framework plan, improvement, and documentation, with no organized technique to confirm if things are moving in the right direction, with appropriate quality controls. The above-mentioned quality gates may be able to highlight the exact areas of improvement. Further, the techniques may be adopted by any applied DSPD model or cycle, and quality gates may also be flexible. Absence of characterized and organized assessment techniques which may be adaptable and fits in all DSPD models or cycles. Further, the techniques may be useful for small to mid-sized enterprise teams. For more mature teams, the quality gates may be incorporated as part of the CI/CD pipeline and project management tools.
[056] As will be also appreciated, the above-described techniques may take the form of computer or controller implemented processes and apparatuses for practicing those processes. The disclosure can also be embodied in the form of computer program code containing instructions embodied in tangible media, such as floppy diskettes, solid state drives, CD-ROMs, hard drives, or any other computer-readable storage medium, wherein, when the computer program code is loaded into and executed by a computer or controller, the computer becomes an apparatus for practicing the invention. The disclosure may also be embodied in the form of computer program code or signal, for example, whether stored in a storage medium, loaded into and/or executed by a computer or controller, or transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via electromagnetic radiation, wherein, when the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, the computer program code segments configure the microprocessor to create specific logic circuits.
[057] Referring now to FIG. 9, a table 900 showing quality gate audit scores 902 corresponding to audits of a DSPD cycle is illustrated, in accordance with some embodiments of the present disclosure. The table 900 may include an audit date 904 and a version 906 corresponding to each QualityGate audit score 902 for a digital or software product. For example, when QualityGate is implemented with risk areas of an , each QualityGate is evaluated by defined parameters and each parameter is given a numeric risk weightage. When a parameter value is in ‘Compliance’ (parameter is completely taken care of), a corresponding score assigned to the parameter is 1.5 points. When a parameter value is in ‘Partial Compliance’ (parameter is partially taken care of, some risk remains), a corresponding score assigned to the parameter is 0.75 points. When a parameter value is in ‘Non-Compliance’ (parameter is not taken care of or ignored, complete risk), a corresponding score assigned to the parameter is 0 points. Further, weightage provided to each QualityGate parameters aggregates to 100. Therefore, the QualityGate audit score 902 for an audit of a DSPD cycle may range from 0 to 100.
[058] The QualityGate audit score 902 for an audit of a DSPD cycle of performed on the audit date 904 of 01 February 2019 and a version 906 of ‘1.6’ is 53.7. The QualityGate audit score 902 for an audit of a DSPD cycle of performed on the audit date 904 of 26 November 2021 and a version 906 of ‘10.4’ is 97.86. Higher QualityGate audit score 902 for the version 906 of 10.4 compared to the version 906 of 1.6 indicates improvement in with new versions released. Therefore, quality gates may be used to evaluate stages in a DSPD cycle as well as individual releases of a digital or software product via the QualityGate audit scores 902. It may be noted that using the QualityGate audit scores 902 may result in improved quality as measured by customer issues and monitoring parameters.
[059] Referring now to FIG. 10, a graphical representation of quality gate audit score trend 1002 is illustrated, in accordance with some embodiments of the present disclosure. The quality gate audit score trend 1002 may be a line chart including value of an audit score 1004 (similar to the QualityGate audit score 902) for each of a plurality of versions of a digital or software product. The quality gate audit score trend 1002 implies that initially, risk was high (low audit score 1004) but QualityGate implementation improved quality of delivery and also improved consistency of the delivery. For example, the audit score 1004 for Release 1.6 may be about 50 and the audit score 1004 for Release 10.4 may be about 95.
[060] The disclosed methods and systems may be implemented on a conventional or a general-purpose computer system, such as a personal computer (PC) or server computer. Referring now to FIG. 11, an exemplary computing system 1100 that may be employed to implement processing functionality for various embodiments (e.g., as a SIMD device, client device, server device, one or more processors, or the like) is illustrated. Those skilled in the relevant art will also recognize how to implement the invention using other computer systems or architectures. The computing system 1100 may represent, for example, a user device such as a desktop, a laptop, a mobile phone, personal entertainment device, DVR, and so on, or any other type of special or general-purpose computing device as may be desirable or appropriate for a given application or environment. The computing system 1100 may include one or more processors, such as a processor 1102 that may be implemented using a general or special purpose processing engine such as, for example, a microprocessor, microcontroller or other control logic. In this example, the processor 1102 is connected to a bus 1104 or other communication medium. In some embodiments, the processor 1102 may be an Artificial Intelligence (AI) processor, which may be implemented as a Tensor Processing Unit (TPU), or a graphical processor unit, or a custom programmable solution Field-Programmable Gate Array (FPGA).
[061] The computing system 1100 may also include a memory 1106 (main memory), for example, Random Access Memory (RAM) or other dynamic memory, for storing information and instructions to be executed by the processor 1102. The memory 1106 also may be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 1102. The computing system 1100 may likewise include a read only memory (“ROM”) or other static storage device coupled to bus 1104 for storing static information and instructions for the processor 1102.
[062] The computing system 1100 may also include storage devices 1108, which may include, for example, a media drive 1110 and a removable storage interface. The media drive 1110 may include a drive or other mechanism to support fixed or removable storage media, such as a hard disk drive, a floppy disk drive, a magnetic tape drive, an SD card port, a USB port, a micro USB, an optical disk drive, a CD or DVD drive (R or RW), or other removable or fixed media drive. A storage media 1112 may include, for example, a hard disk, magnetic tape, flash drive, or other fixed or removable medium that is read by and written to by the media drive 1110. As these examples illustrate, the storage media 1112 may include a computer-readable storage medium having stored therein particular computer software or data.
[063] In alternative embodiments, the storage devices 1108 may include other similar instrumentalities for allowing computer programs or other instructions or data to be loaded into the computing system 1100. Such instrumentalities may include, for example, a removable storage unit 1114 and a storage unit interface 1116, such as a program cartridge and cartridge interface, a removable memory (for example, a flash memory or other removable memory module) and memory slot, and other removable storage units and interfaces that allow software and data to be transferred from the removable storage unit 1114 to the computing system 1100.
[064] The computing system 1100 may also include a communications interface 1118. The communications interface 1118 may be used to allow software and data to be transferred between the computing system 1100 and external devices. Examples of the communications interface 1118 may include a network interface (such as an Ethernet or other NIC card), a communications port (such as for example, a USB port, a micro USB port), Near field Communication (NFC), etc. Software and data transferred via the communications interface 1118 are in the form of signals which may be electronic, electromagnetic, optical, or other signals capable of being received by the communications interface 1118. These signals are provided to the communications interface 1118 via a channel 1120. The channel 1120 may carry signals and may be implemented using a wireless medium, wire or cable, fiber optics, or other communications medium. Some examples of the channel 1120 may include a phone line, a cellular phone link, an RF link, a Bluetooth link, a network interface, a local or wide area network, and other communications channels.
[065] The computing system 1100 may further include Input/Output (I/O) devices 1122. Examples may include, but are not limited to a display, keypad, microphone, audio speakers, vibrating motor, LED lights, etc. The I/O devices 1122 may receive input from a user and also display an output of the computation performed by the processor 1102. In this document, the terms “computer program product” and “computer-readable medium” may be used generally to refer to media such as, for example, the memory 1106, the storage devices 1108, the removable storage unit 1114, or signal(s) on the channel 1120. These and other forms of computer-readable media may be involved in providing one or more sequences of one or more instructions to the processor 1102 for execution. Such instructions, generally referred to as “computer program code” (which may be grouped in the form of computer programs or other groupings), when executed, enable the computing system 1100 to perform features or functions of embodiments of the present invention.
[066] In an embodiment where the elements are implemented using software, the software may be stored in a computer-readable medium and loaded into the computing system 1100 using, for example, the removable storage unit 1114, the media drive 1110 or the communications interface 1118. The control logic (in this example, software instructions or computer program code), when executed by the processor 1102, causes the processor 1102 to perform the functions of the invention as described herein.
[067] Thus, the disclosed method and system try to overcome the technical problem of identifying common requirements from applications. The method and system provide a significant reduction in application portfolio optimization assessment. Further, the method and system provide for cost and effort optimization in identifying commonalities and uniqueness across heterogeneous monolith applications. Further, the method and system accelerate time to market by generating intelligent insights and help in making informed decisions on transformation roadmap.
[068] As will be appreciated by those skilled in the art, the techniques described in the various embodiments discussed above are not routine, or conventional, or well understood in the art. The techniques discussed above provide for evaluating stages in a DSPD cycle through quality gates. Further, the techniques may provide for self-assessment to improve the quality practices of the team as part of the build cycle. The invention may provide a suggestive technique with fully customizable quality gates which may be used with incremental short term quality gates that evolve continuously or as a long-term goal with tracking of the score as a measure of the overall progress of the team. Further, the quality gate of the above-mentioned techniques may completely be institutionalized by an internal team, which may prevent time and cost of external audits with better quality outcomes by the team. In true spirit of the shift left approach, the quality gates may help in early identification of the issues resulting in higher quality and lower cost of product development. When the quality gates and their boundaries are highly characterized, just requirements to choose fitting values against them and no extra countable effort is required. Further, the scores from multiple may be compared to identify the areas of improvement which becomes a useful metric for sprint retrospectives and provides clear action areas of improvement. Further, the techniques provide quality gates that may be defined with distinctive assessment boundaries/elements. The verification parameters may be customized in similar fashion. Further, the evaluation cycle may be flexible; it may be recommended to use maximum gates as part of the CI/CD practices of the team and as a checkpoint may be used as Sprint Definition of Done regardless of the sprint duration of any length as per the agile implementation. Furthermore, the techniques focus and encourages automation of each phase/stage or within phases/stages.
[069] In light of the above mentioned advantages and the technical advancements provided by the disclosed method and system, the claimed steps as discussed above are not routine, conventional, or well understood in the art, as the claimed steps enable the following solutions to the existing problems in conventional technologies. Further, the claimed steps clearly bring an improvement in the functioning of the device itself as the claimed steps provide a technical solution to a technical problem.
[070] The specification has described method and system for evaluating stages in a DSPD cycle through quality gates. The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed. Alternatives (including equivalents, extensions, variations, deviations, etc., of those described herein) will be apparent to persons skilled in the relevant art(s) based on the teachings contained herein. Such alternatives fall within the scope and spirit of the disclosed embodiments.
[071] Furthermore, one or more computer-readable storage media may be utilized in implementing embodiments consistent with the present disclosure. A computer-readable storage medium refers to any type of physical memory on which information or data readable by a processor may be stored. Thus, a computer-readable storage medium may store instructions for execution by one or more processors, including instructions for causing the processor(s) to perform steps or stages consistent with the embodiments described herein. The term “computer-readable medium” should be understood to include tangible items and exclude carrier waves and transient signals, i.e., be non-transitory. Examples include random access memory (RAM), read-only memory (ROM), volatile memory, nonvolatile memory, hard drives, CD ROMs, DVDs, flash drives, disks, and any other known physical storage media.
[072] It is intended that the disclosure and examples be considered as exemplary only, with a true scope and spirit of disclosed embodiments being indicated by the following claims.

CLAIMS

1/We Claim

1. A method (400) for evaluating stages in a digital or software product development (DSPD) cycle through quality gates, the method (400) comprising:
receiving (402), by a DSPD evaluation device, a plurality of predefined quality parameters corresponding to each of a set of quality gates, wherein each of the plurality of predefined quality parameters comprises a set of predefined values, and wherein each of the set of quality gates corresponds to each of a plurality of stages of the DSPD cycle;
for each of the set of quality gates and for each of the plurality of corresponding stages,
sending (404), by the DSPD evaluation device, input data to an associated quality gate upon completing a corresponding stage of the DSPD cycle, wherein the input data comprises an end product of the corresponding stage;
activating (406), by the DSPD evaluation device, the associated quality gate upon receiving the input data of the corresponding stage; and
evaluating (408), by the DSPD evaluation device, the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results.

2. The method (400) of claim 1, wherein evaluating (408) the corresponding stage of the DSPD cycle comprises determining (410) one of the set of predefined values for each of the plurality of predefined quality parameters based on the input data received.

3. The method (400) of claim 1, wherein evaluating (408) the corresponding stage of the DSPD cycle comprises identifying (412) at least one of risks, faults, and vulnerabilities for the corresponding stage, and wherein the evaluation results comprise the at least one of risks, faults, and vulnerabilities identified for the corresponding stage.

4. The method (400) of claim 1, wherein evaluating (408) the corresponding stage of the DSPD cycle comprises validating (414) compliance of the corresponding stage with respect to one or more of predefined quality standards, and wherein the evaluation results comprise compliance details of the corresponding stage.

5. The method (400) of claim 1, further comprising, at least one of:
activating each of the set of quality gates to evaluate each of the plurality of stages of the DSPD cycle in parallel; and
activating a next quality gate for a next stage of the DSPD cycle upon successfully evaluating the corresponding stage by the quality gate.

6. The method (400) of claim 1, further comprising generating (416) an evaluation report (214) based on the evaluation results for each of the plurality of stages of the DSPD cycle.

7. A system (100) for evaluating stages in a DSPD cycle through quality gates, the system (100) comprising:
a processor (104); and
a memory communicatively coupled to the processor (104), wherein the memory stores processor-executable instructions, which, on execution, cause the processor (104) to:
receive (402) a plurality of predefined quality parameters corresponding to each of a set of quality gates, wherein each of the plurality of predefined quality parameters comprises a set of predefined values, and wherein each of the set of quality gates corresponds to each of a plurality of stages of the DSPD cycle;
for each of the set of quality gates and for each of the plurality of corresponding stages,
send (404) input data to an associated quality gate upon completing a corresponding stage of the DSPD cycle, wherein the input data comprises an end product of the corresponding stage;
activate (406) the associated quality gate upon receiving the input data of the corresponding stage; and
evaluate (408) the corresponding stage via the activated quality gate based on the plurality of predefined quality parameters to obtain evaluation results.

8. The system (100) of claim 7, wherein to evaluate (408) the corresponding stage of the DSPD cycle, the processor-executable instructions, on execution, cause the processor (104) to, at least one of:
determine (410) one of the set of predefined values for each of the plurality of predefined quality parameters based on the input data received;
identify (412) at least one of risks, faults, and vulnerabilities for the corresponding stage, and wherein the evaluation results comprise the at least one of risks, faults, and vulnerabilities identified for the corresponding stage; and
validate (414) compliance of the corresponding stage with respect to one or more of predefined quality standards, and wherein the evaluation results comprise compliance details of the corresponding stage.

9. The system (100) of claim 7, wherein the processor-executable instructions, on execution, further cause the processor (104) to, at least one of:
activate each of the set of quality gates to evaluate each of the plurality of stages of the DSPD cycle in parallel; and
activate a next quality gate for a next stage of the DSPD cycle upon successfully evaluating the corresponding stage by the quality gate.

10. The system (100) of claim 7, wherein the processor-executable instructions, on execution, further cause the processor (104) to generate an evaluation report (214) based on the evaluation results for each of the plurality of stages of the DSPD cycle.