A) TECHNICAL FIELD

[0001] The present invention generally relates to networking and particularly relates a method and system for transferringa plurality of clocksignalsfrom a line card to a central timing card in a multi-card synchronized system by optimizing the pins used.
B) BACKGROUND OF THE INVENTION

[0002] Many telecommunications switching systems might include plurality of I/O Cards (called line cards or network interface cards) for processing different data from network interfaces like El, DS1, STM-n, OC-n etc and send this processed data to traffic switch (Called Switch card) to switch data from one network interface to other. In such telecommunication systems the data from Line cards to switch card passes over a backplane which connects various cards in a system. Such telecommunication system is called network element. In a network there is plurality of such network elements. In networks like SONET/SDH, all these network elements need to work in locked mode traceable to PRC (Primary reference clock). For more information on network synchronization in SDH refer ITU-T standard G.813 and G.825. The synchronization from one network element to other is passed over various interfaces like El, DS1, STM-n, OC-n etc.

[0003] Each network interface card extracts synchronization clocks from various network interfaces and sends them to at least one system synchronizer. These clocks are typically of order of few KHz. The system synchronizer monitors subset of these clock and selects one among them based on user defined priority and quality of the clocks. Thus system synchronizer, synchronize the network element so that the entire outgoing interfaces from the said network element are in sync.

[0004] In a multi-card synchronized system, every line card hands over one or more recovered clocks (as network references) to the central timing cards. The handover of each recovered clock signal needs one pin on the line card and one pin on the central timing card. Considering a high density line card system, there is a pin count explosion on the system backplane, proportional to the number of reference clocks handed over from each line card. This pin explosion on the system backplane at the line card and the central timing card vicinities results in resource wastage, additional cost and increased design complexity.

[0005] Hence, there is a need for a method and system for handing over multiple clocks from a line card to a central timing card in an optimal manner. Also, there is a need for a method and system for simplifying the overall system architecture and enhancing the system level clocking. Further, there is a need for a method and system for optimizing the system backplane pin count to handle pin explosion conditions.

C) OBJECTIVES OF THE INVENTION

[0006] The primary objective of the present invention is to provide a method and system for handing over multiple recovered clocks from a line card to a central timing card through a single pin optimally.

[0007] Another objective of the present invention is to provide a method and system for dividing the line card signals to lower frequencies and then again combining at the receiving end.

[0008] Another objective of the present invention is to provide a method and system for optimizing the system backplane pin count to handle pin explosion conditions.

[0009] Another objective of the present invention is to provide a method and system for simplifying the overall system architecture and enhancing system level clocking.

[0010] Another objective of the present invention is to provide a method and system for reducing thecost and effective utilization of resources.

[0011] These and other objects and advantages of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings.

D) SUMMARY OF THE INVENTION

[0012] The various embodiments of the present invention disclose a method for providing handover of network recovered clocks in a multi-card synchronized system. The method comprises of dividing a plurality of recovered clocks on a line card into one or more rate converted recovered clocks, time-division multiplexing the rate converted recovered clocks into a single pin andde-multiplexing of the rate converted recovered clocks in the timing card using the high frequency timing card reference clock. The time division multiplexing and de-multiplexing of the rate converted recovered clocks are performed using a high frequency timing card reference clock.

[0013] According to an embodiment of the present invention, the plurality of recovered clocks is divided using a preset division factor, where the preset division factor is selected based on the recovered clock frequency and a preset low frequency clock rate.

[0014] According to an embodiment of the present invention, the method further comprises identification of the one or more rate converted recovered clocks by measuring a frequency of the clocks. Here a difference in the frequencies enables a correlation of the rate converted recovered clocks before multiplexing and after de-multiplexing.

[0015] Embodiments herein further disclose a system for providing handover of network recovered clocks. The system comprising, a plurality of line cards, a pin optimized backplane and a central timing card. The plurality of line cards comprises a module adapted to divide a plurality of recovered clocks into preset low frequency clock rates using predetermined division factors, a time division multiplexer for time division multiplexing the rate converted recovered clocks into a single pin anda module to hand over the time division multiplexed signal to the central timing on the pin optimized back plane.

[0016] According to an embodiment of the present invention, the central timing card comprises a time division de-multiplexer to de-multiplex the rate converted recovered clocks using a high frequency timing card reference clock.

[0017] According to an embodiment of the present invention, the central timing card comprises an active timing card and a standby timing card.

[0018] According to an embodiment of the present invention, the central timing card is adapted to provide a high frequency reference clock to the line cards.

[0019] According to an embodiment of the present invention, the system further comprises a low bandwidth system PLL on the central timing card to remove a jitter introduced on the rate converted recovered clocks by the time division multiplexer and de-multiplexer.

[0020] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating preferred embodiments and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments herein without departing from the spirit thereof, and the embodiments herein include all such modifications.

E) BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The other objects, features and advantages will occur to those skilled in the art from the following description of the preferred embodiment and the accompanying drawings in which:

[0022] FIG. 1 is a block diagram illustrating a multi line card, dual redundant synchronized system with optimized pin count, according to an embodiment of the present invention.

[0023] FIG. 2 is a flow chart illustrating a method for handing over multiple independent network recovered clocks on a single pin, according to an embodiment of the present invention.

[0024] FIG. 3 illustrates a method for multiplexing the input clock signals with reference to a reference signal, according to an exemplary embodiment of the present invention.

[0025] Although the specific features of the present invention are shown in some drawings and not in others. This is done for convenience only as each feature may be combined with any or all of the other features in accordance with the present invention.

F) DETAILED DESCRIPTION OF THE DRAWINGS

[0026] In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which the specific embodiments that may be practiced is shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and it is to be understood that the logical, mechanical and other changes may be made without departing from the scope of the embodiments. The following detailed description is therefore not to be taken in a limiting sense.

[0027] The various embodiments of the present invention disclose a method for providing handover of network recovered clocks in a multi-card synchronized system. The method comprises of dividing a plurality of recovered clocks on a line card into one or more rate converted recovered clocks, time-division multiplexing the rate converted recovered clocks into a single pin andde-multiplexing of the rate converted recovered clocks in the timing card using the high frequency timing card reference clock. The time division multiplexing and de-multiplexing of the rate converted recovered clocks are performed using a high frequency timing card reference clock.

[0028] The plurality of recovered clocks is divided using a preset division factor, where the preset division factor is selected based on the recovered clock frequency and a preset low frequency clock rate.

[0029] The method further comprises identification of the one or more rate converted recovered clocks by measuring a frequency of the clocks. Here a difference in the frequencies enables a correlation of the rate converted recovered clocks before multiplexing and after de-multiplexing.

[0030] Embodiments herein further disclose a system for providing handover of network recovered clocks. The system comprising, a plurality of line cards, a pin optimized backplane and a central timing card. The plurality of line cards comprises a module adapted to divide a plurality of recovered clocks into preset low frequency clock rates using predetermined division factors, a time division multiplexer for time division multiplexing the rate converted recovered clocks into a single pin anda module to hand over the time division multiplexed signal to the central timing card on the pin optimized back plane.

[0031] The central timing card comprises a time division de-multiplexer to de¬multiplex the rate converted recovered clocks using a high frequency timing card reference clock. The central timing card comprises an active timing card and a standby timing card and is adapted to provide a high frequency reference clock to the line cards.

[0032] The system further comprises a low bandwidth system PLL on the central timing card to remove a jitter introduced on the rate converted recovered clocks by the time division multiplexer and de-multiplexer.

[0033] FIG. 1 is a block diagram illustrating a multi line card, dual redundant synchronized system with optimized pin count, according to an embodiment of the present invention. The system comprises a plurality of line cards 101a, 101b, ..., lOln, a backplane 103 and a central timing card 104. The line card 101a, 101b, ..., 101c such as an Ethernet card is an telecom interface with multiple ports/pins/inputs. Each of the line cardslOla, 101b, ..., 101c is capable to recover the clock signal from the network. The backplane 102 is a medium through which the communication from the line card 101a, 101b, ..., 101c is transferred to central timing card 104. Specifically, the backplane 103 is a circuit board which assists in communication between the plurality of line cards 101a, 104b, ..., lOlnand the central timing card 104. The central timing card 104 comprises an active timing card 105, a standby timing card 106 and a plurality of time division de-multiplexers 107 to de-multiplex the rate converted recovered clocks using a high frequency timing card reference clock.The active timing card 105 keeps tracks of accurate time and frequency and assist in synchronization. The standby timing card 106 is a redundant time card for the active timing card 105.

[0034] All the signal such as recovered clock signals, which originate from the line cards 101a, 101b, ..., lOln passes through the backplane 103 and reaches to the central timing card 104. The central timing card 104 is also known as a control card. Each line cards 101 a, 101b, ..., lOln comprises a pair of time division multiplexers (TDM MUX) 102 .Each of the multiple recovered clocks on the line cards 101a, 101b, ..., lOln are divided down into a unique predetermined low frequency rate. All of the low frequency clocks (running at different rates) are Time Division Multiplexed (TDM) onto a single pin using the higher frequency timing card reference clock. The signals from the line cards 101a, 101b, ..., lOln are transferred to the active timing card 105 and the standby timing card 106 through the pair of multiplexers (MUX).Time Division Multiplexing (TDM) is a communication process that transmits two or more streaming digital signals over a common channel. In TDM, incoming signals are divided into equal fixed-length time slots. After multiplexing, these signals are transmitted over a shared medium and reassembled into their original format after de-multiplexing at the central timing card 104.

[0035] FIG. 2 is a flow chart illustrating a method for handing over multiple independent network recovered clocks by the line card to the central timing card on a single pin, according to an embodiment of the present invention. Each of the plurality of recovered clocks on the line card is divided down into one or more rate converted recovered clocks using an unique predetermined low frequency clock rate (201). The recovered clocks are divided using appropriate division factors, which in turn depend on the recovered clock frequency and the preset low frequency clock rate. All the rate converted recovered clocks (running at different rates) are time division multiplexed onto a single pin using the higher frequency timing card reference clock. The multiplexed signal is transmitted through the backplane to the central timing cards (202). Further the received multiplexed signal is de-multiplexed on the central timing card using the same reference clock to recover the rate converted clocks. The rate converted clocks recovered by de-multiplexing on the central timing card are similar to the Multiplexer input of plurality on the line cards (203). Any jitter in the recovered clock signal is cleared by Phase Locked Loop (PLL) (204). The Jitter is defined as the short-term variations of the significant instants of a digital signal from their ideal positions in time.

[0036] FIG. 3 illustrates a method for multiplexing the input clock signals with reference to a reference signal, according to an exemplary embodiment of the present invention. Consider a line card with four recovered clocks signals RecclkO, Recclkl, Rec_clk2 and Rec_clk3. The central timing card provides 38.88MHz reference clock to the line card. The line card divides down the Rec_clk0, Rec_clkl, Rec_clk2 and Rec_clk3 to 1kHz, 2kHz, 4kHz and 8kHz respectively using the appropriate division factors. These low frequency clocks are time division multiplexed using the 38.88MHz reference clock as shown in the FIG. 3. The muxing of the input clock signals is started arbitrarily.The same 38.88MHz clock is used on the central timing card to de-multiplex and recover the low frequency clocksignals. The de-multiplexing on the central timing card starts at an arbitrary clock edge (of 38.88MHz) and because of this the four recovered clocks are not in the same multiplexing sequence. For de-multiplexing, plurality of de-multiplexers (DEMUX) is used. The frequencies of thefour clocks are measured to identify them as 1kHz, 2kHz, 4kHz and 8kHz. The jitter introduced on these clocks by the current multiplexing and de-multiplexing mechanism is cleaned by the low bandwidth system phase-locked loop (PLL) on the timing card.The (PLL) is a control system which generates a signal having a fixed relation to the phase of a "reference" signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signals, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference clock bothin frequency and phase.

[0037] According to an embodiment of the present invention, the pin explosion issue is solved by optimizing the number of pins needed to handover the recovered clocks by multiplexing the entire pins onto a single pin. The reduction the number of pins in turn reduces the overall cost of the system. Further, the system requires the use of less number of components which in turn reduces the complexity. Also, the backplane pin count is optimized. The handover of 1588 recovered clock and 1PPS (in a multiplexed form) to the line card on a single pin is obtained.

[0038] According to an embodiment of the present invention, the methodology simplifies the overall system architecture, enhances system level clocking and optimizes the system backplane pin count. The embodiments also enable effective utilization of the resources.

[0039] According to an embodiment of the present invention, method and system disclosed herein is implemented through at least one of a software module, one or more hardware components or a combination of both. [0040] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.

CLAIMS

What is claimed is:

1. A method for providing handover of network recovered clocks in a multi-card synchronized system, the method comprises of:

dividing a plurality of recovered clocks on a line card into one or more rate

converted recovered clocks;

time-division multiplexing the rate converted recovered clocks into a single pin; and

de-multiplexing of the rate converted recovered clocks in the timing card using the

high frequency timing card reference clock;

wherein the time division multiplexing and de-multiplexing of the rate converted recovered clocks are performed using a high frequency timing card reference clock.

2. The method of claim 1, wherein the plurality of recovered clocks is divided using a preset division factor, where the preset division factor is selected based on the recovered clock frequency and a preset low frequency clock rate.

3. The method of claim 1, further comprising identification of the one or more rate converted recovered clocks by measuring a frequency of the clocks, where a difference in the frequencies enables a correlation of the rate converted recovered clocks before multiplexing and after de-multiplexing.

4. A system for providing handover of network recovered clocks, the system comprising:

a plurality of line cards;

a pin optimized backplane;

a central timing card;

wherein the plurality of line cards comprises:

a module adapted to divide a plurality of recovered clocks into preset low frequency clock rates using predetermined division factors;

a time division multiplexer for time division multiplexing the rate converted recovered clocks into a single pin; and

a module to hand over the time division multiplexed signal to the central timing on the pin optimized back plane.

5. The system of claim 4, wherein the central timing card comprises a time division de-multiplexer to de-multiplex the rate converted recovered clocks using a high frequency timing card reference clock.

6. The system of claim 4, wherein the central timing card comprises an active timing card and a standby timing card.

7. The system of claim 4, wherein the central timing card is adapted to provide a high frequency reference clock to the line cards.

8. The system of claim 4, further comprising a low bandwidth system PLL on the central timing card to remove a jitter introduced on the rate converted recovered clocks by the time division multiplexer and de-multiplexer.