METHOD AND SYSTEM FOR MEASURING MAXIMUM OPERATING FREQUENCY AND CORROSPONDING DUTY CYCLE FOR AN I/O CELL
Field of the Invention
The present invention relates to electronic circuits, and more specifically to a system and method for measuring a maximum operating frequency, and its corresponding duty cycle for an I/O cell inside a chip.
Background of the Invention
There are various parameters, such as operating frequencies, duty cycle, or potential drop measurements at different nodes inside an integrated circuit, which needs to be analyzed These parameters are required to understand special characteristics of the Integrated Circuits (ICs). A specific value of an operating frequency and a duty cycle of an on chip clock or signal often becomes significant in a VLSI, like DRAM circuits, analog to digital converter (ADC) circuits, which are sensitive to the operating frequency or duty cycle or where operations are synchronized with both transitions of the clock.
There exist many applications, where the speed of the I/O structures becomes a limiting factor inside a chip. In such cases identifying the true limits of the operating frequency of the I/O structures with respect to a specified duty cycle and an upper and a lower voltage threshold limit can help the core designer, as he/she exactly knows the limiting frequency of I/Os for applying critical signals like clock and observing the output values Identifying the true operating frequency in a computer system may prevent inconsistencies between the processor, software running on it, and the generation of operation-code exceptions.
The clock signal is a heart beat for all synchronous digital computing and communication circuits, some of which are sensitive to both edges of the clock. Dynamic and domino logic circuits require one phase of the clock cycle for pre-charge and the other to
evaluate, thus imposing a tight constraint on the operating frequency and the duty cycle of the clock to operate at maximum possible speed. In data communication circuits and systems the importance of clock-to-data correlation is magnified, and large variations in these parameters (operating frequency and duty cycle) of the clock cannot be tolerated. Similarly, in serializer / deserializer (SERDES) technology, when both edges of the serialization signal are used to serialize the data, a balanced duty cycle becomes very important to provide equal transmission time for each symbol.
In advanced deep submicron VLSI technologies, the clock is distributed to individual components through a large clock -distribution tree made up of clock buffers and interconnects of appropriate sizes to minimize skew and end-to-end delay. A noticeable degradation in duty cycle can be observed at the terminal ends of the signal distribution network, even for signals generated with a perfectly stable and accurate signal source. This is due to a slight mismatch in the drive strengths of pull-up and pull-down networks of the CMOS gates/buffers and non-uniformity in the distribution of wiring capacitance. A local duty cycle correction circuit is usually required to fix this problem.
At the tester level, operating frequency measurement can be done only for output I/Os, not for input 1/Os Hence an on chip system is required which would internally measure the operating frequency of an input I/O and generate the result in a digital format.
There exists various conventional techniques for frequency measurement inside a chip, but none of the techniques provide measurement of the true operating frequency, which satisfies a plurality of conditions, such as duty cycle values, upper voltage threshold and lower voltage threshold
Therefore, there arises a need for a testing methodology for measuring maximum operating frequency and corresponding duty cycle for an input, and output I/O cell. Moreover, the proposed methodology provides an on chip testing flexibility.
Summary of the Invention
It is an object of the present invention to provide a flexible methodology utilizing a simple and cost effective circuit for measuring a maximum operating frequency, and its corresponding duty cycle for an input I/O cell.
To achieve the aforementioned objectives, the present invention provides a circuit for on-chip measurement of maximum operating frequency of an input IUT, said frequency obeying a plurality of conditions at a maximum frequency, said circuit being synchronized with a central controller for a proper handshaking, said circuit comprising:
an input I/O (IUT) terminal for receiving an input voltage signal,
a count register connected to the central controller for storing a number of cycles for which a sample lest is performed,
a plurality of programmable loads for determining a maximum frequency
at a plurality of loads,
a programmable voltage threshold sensor calibrated at an upper threshold limit and a lower threshold limit for analyzing an output voltage signal from said IUT terminal for a desired threshold voltage level,
a ripple counter connected to said voltage threshold sensor for counting passed output voltage signals from said voltage sensor, the passed output voltage signals obeying the desired threshold voltage level,
a time to digital converter (TDC) receiving the output voltage signal from said IUT terminal for converting a width of said output voltage signal to a binary equivalent value; and
an accumulator connected to said TDC for adding a binary value of said output voltage signal for said number of cycles, the plurality of conditions comprising:
a signal transition at an IUT output for a low pulse crossing a specified lower voltage threshold limit;
a signal transition at an IUT output for a high pulse crossing a specified upper voltage threshold limit; and
a duty cycle at an I/O output remains within a specified limit.
Further the present invention provides a method for measuring a maximum operating frequency, and its corresponding duty cycle variation of an input I/O cell, said method comprising the steps of:
calibrating a time to digital converter (TDC) to formulate a binary' to time domain conversion (BTDC) formula;
calibrating a programmable voltage threshold sensor for an upper voltage threshold value and a lower voltage threshold value;
storing a sample test cycle number(N) through a count register,
applying N input cycles having a high pulse width (HPW) less than a low pulse width (LPW),
shifting out accumulator contents to measure a duty cycle,
shifting out ripple counter contents for checking, if said input cycles crosses an upper threshold voltage;
checking a ripple count value, and a duty cycle value;
decreasing the high pulse width (HPW), when the ripple counter value equals to said cycle numbers (N), and the duty cycle value is within a specification;
storing a last passed high pulse width value, when the ripple counter value not equals to said cycle number (N), and the duty cycle value is not within the specification;
applying N input cycles having a high pulse width (HPW) greater than a low pulse width (LPW),
shifting out accumulator contents to measure a duty cycle;
shifting out the ripple counter contents for checking, if said input cycles crosses a lower threshold voltage;
checking a ripple count value, and a duty cycle value;
decreasing the low pulse width (LPW), when the ripple counter value equals to said cycle numbers (N), and the duty cycle value is within a specification,
storing a last passed low pulse width value, when the ripple counter value not equals to said cycle number (N), and the duty cycle value is not within the specification; and
calculating a maximum frequency from said passed low pulse width value, and a passed high pulse width value.
Brief Description of Drawings
FIGURE 1 illustrates a schematic block diagram of a circuit for measuring a maximum operating frequency and its corresponding duty cycle in an Input I/O cell according to the present invention.
FIGURE 2 is a waveform diagram illustrating a timing diagram for a duty cycle measurement according to the present invention.
FIGURE 3 is a waveform diagram illustrating upper threshold voltage detection according to the present invention.
FIGURE 4 is a waveform diagram illustrating lower threshold voltage detection according to the present invention.
FIGURE 5A, 5B, and 5C illustrates a flow diagram of a method for measuring a maximum operating frequency, and its corresponding duty cycle variation of an input I/O cell according to the present invention.
Detailed Description of the Invention
The present invention provides a circuit for measuring a maximum operating frequency, and its corresponding duty cycle for an input I/O cell inside a chip circuit.
FIGURE 1 illustrates a schematic block diagram of a circuit 100 for measuring a maximum operating frequency and its corresponding duty cycle in an input I/O cell according to the present invention. The circuit 100 includes an IUT terminal 102, a count register 104, a programmable load 106, a programmable voltage threshold sensor 108, a ripple counter 110, a time-to-digital converter (TDC) 112, and an accumulator 114. All blocks in the circuit 100 may receive their control inputs either from a central controller 116, or directly from primary inputs (Pad).
An I/0's maximum operating frequency, is the highest frequency which satisfies all the following three conditions:
1 The signal transition at the output of the I/O for a low pulse crosses the specified lower
voltage threshold limits (usually 10% of supply voltage (vdd)).
2 The signal transition at the output of the I/O for a high pulse crosses the specified
upper voltage threshold limits (usually 90% of supply voltage).
3. The Duty Cycle at the output of the I/O remains within specified limits (usually a 40:60 or 60:40 duty cycle is the permissible limit for an input duty cycle of 50:50).
The maximum operating frequency is determined by applying 'N' number of cycles at an input of the IUT terminal 102 and determining whether in all those 'N' cycles each of the above condition is met or not. As seen from FIGURE 1, the count register 104 stores the number of cycles for which a test is to be run and a set of the programmable loads 106 are also present to determine a maximum frequency at various loads.

The programmable voltage threshold sensor 108 has been implemented to determine whether an output of the IUT terminal 102 reaches the desired voltage threshold levels. The voltage threshold sensor 108 is calibrated with its upper & lower thresholds frequency limits (say 10% & 90% of Vdd). In other embodiments different limits can be set for the upper and lower threshold limits depending on the tests. Thus, before the actual test starts, we calibrate the programmable voltage threshold sensor to a desired upper voltage threshold level and a lower voltage threshold level. The output of the voltage threshold sensor 108 is fed to the ripple counter 110. Thus if we apply 1000 input cycles and in all those 1000 cycles the output of the I/O crosses the specified threshold limits, then the ripple counter 110 will count up to 1000.
Now it is required to be seen whether over those 1000 cycles, the duty cycle remains within specified limits (40:60 or 60:40) Suppose, we apply an input frequency of 10 MHz (100ns) with a duty cycle of 50:50 at the input of the IUT terminal 102, then at the output, we might get a signal whose duty cycle is different from the input duty cycle. This implies that over a cycle a high pulse of 50ns at the input should come out through the output with a width greater than 40ns and less than 60ns. The output of the IUT terminal 102 is first fed to the TDC 112 The TDC circuit converts an input pulse into its binary equivalent value This binary value is then converted to a time-domain value using a Time Domain Conversion (BTDC) formula. This time-domain value is equal to the width of the Input pulse fed to the TDC. Although many implementations of Time to
digital converter are available and can be used....in present^invention, a....preferred
embodiment...of IDC. is .disclosed, .in.....the pending USpatent application. 20030117 8 68., the one implemented Digital converters for this application is derived from an already patented-applieation referred--to-US-Patent No. 200301 17868 titled as "Measurement of timing skew between two digital signals". The working details of this time to digital converter (TDC) can be found in above mentioned patent application. A binary value equivalent of a high pulse width time obtained from the TDC 112 is then added up in the accumulator 114, which adds all these binary values over a given number of input cycles.
Thus, if we apply 1000 input cycles, the TDC will convert the 1000 high pulse widths to a binary format, which would get added up in the accumulator 114. The final accumulator value will now represent a sum of high pulse width times over 1000 cycles. This binary value is then converted back to time format by using a Binary to Time Domain Conversion (BTDC) formula for the TDC 112. The details of BTDC formula can also be found in the above file4-mentip.ned...US Ppatent Aapplication 20030117868. This final value when divided by a number of applied cycles (1000) gives an average value of a high pulse width. Now if this value is greater than 40ns & less than 60ns, then it can be said that the signal at the output of the IUT terminal 102 satisfies the permissible duty cycle (40:60 / 60:40) requirements.
To make the measurement procedure synchronous with a system clock, the whole methodology has been divided into 2 iterations. The idea is that instead of applying an input signal with 50:50 Duty Cycle, 2 sets of input signals are applied in different iterations, one in which a high pulse width is much less than a low pulse width and vice-versa. In both the cases the input cycle is kept, such that it corresponds to 3 cycles of a system clock (equal to 1 machine cycle - MC). The waveform corresponding to the first iteration is illustrated in FIGURE 2 in which the input signal's high pulse width is much less than the low pulse width.
The test is performed over say 1000 (loaded in the count register 104) such input cycles. In this iteration it is checked whether the input pulse has crossed 90% of the voltage threshold limit in all the cycles. This would be verified if the ripples counter 110 stores a count of 1000. If the count is less than 1000, then it can be judged that in some input cycles, the high pulse width did not cross 90% of the voltage threshold limit. This is illustrated in FIGURE 3.
Apart from a voltage threshold, the high pulse width is also continuously measured for each input cycle. This high pulse width is converted to a binary format by the TDC 112 which is then accumulated in the accumulator 114 during each machine cycle. To enable
this operation, each machine cycle is made up of 3 system clock cycles (SCC) as illustrated in FIGURE 2. In SCC-1, an input pulse is applied and it is measured by the TDC 112 and converted into the binary data format. In SCC-2, the binary data format gets added to the accumulator 114 and finally in SCC-3, the TDC 112 is reset to measure a next pulse (which arrives in the next machine cycle). Thus at the end of 1000 cycles, an accumulator value is shifted out (say via TDO port of the 1EEE1149.1 JTAG logic). This binary value is converted into a real time value and then divided by 1000 to get an average pulse width during the 1000 input cycles.
Now a duty cycle can be calculated by taking up an example. Suppose that the applied pulse width was of 50ns and the average actual pulse width inside the core came out to be 40ns, then we can say that assuming that this applied pulse width was like a frequency of 100ns period & 50:50 duty cycles, then the average duty cycle obtained inside the chip is 40:60.
The above mentioned procedure is repeated in the second iteration with low pulse width much less than the high pulse width. This is illustrated in the FIGURE 4 At the end of this iteration, the contents of the ripple counter 110 needs to be checked If the counter 110 has counted correctly till 1000, then it verifies that in each input cycle, the low pulse has crossed the 10% voltage threshold limit, if not the count would have been less than 1000.
Also, in this case the duty cycle is calculated in similar fashion as compared to the previous iteration. The duty cycle values in both iterations would come out to be the same. i.e. continuing the previous example of an input cycle of 100ns with 50:50 duty cycle, the average measured pulse width in this case would come out to be 60ns Thus overall we can say that the average duty cycle in the chip is 40:60 for an input frequency having 50:50 duty cycles.
The measurement procedure is started by applying relaxed high pulse widths and low pulse widths (obtained from CAD simulations) respectively. Now this whole
measurement methodology is repeated by decreasing the high pulse width in the first iteration and the low pulse width in the second iteration till we obtain a result beyond which we start getting results which violate the required specifications (i.e. either the high pulse width doesn't go till 90%Vdd or the low pulse width doesn't go till 10% vdd or the duty cycle deteriorates below 40:60 mark). Let Thpw' be the Last High Pulse Width value that passed, and let Tlpw' be the Last Low Pulse Width value that passed. Now a maximum operating frequency of an IUT is given by:
Maximum Frequency = I/ [Worst of {Thpw; Tlpw}] * 2
The above mentioned circuitry could be easily extended for a maximum frequency measurement of output I/Os as well.
FIGURE 5A, 5B and 5C illustrates a flow diagram of a method for measuring a maximum operating frequency, and its corresponding duty cycle variation of an input I/O cell according to the present invention. At step 502, a time to digital converter (TDC) is calibrated and a binary to time domain conversion formula (BTDC) is formulated. At step 504, a programmable voltage threshold sensor is calibrated for a desired threshold value. At step 506, sample test cycle numbers are stored through a count register. At step 508, N input cycles having high pulse width (HPW) less than low pulse width (LPW) are applied. At step 510, accumulator contents are shifted out to measure a duty cycle, and also ripple counter contents are shifted out for checking if in all cycles, the input crosses the upper threshold voltage At step 512, a ripple count value and the duty cycle value are checked. At step 514, the high pulse width (HPW) is decreased, when the ripple counter value is N, and the duty cycle is within the specifications. At step 516, a last passed high pulse width value is stored, when the ripple counter value is not N, and the duty cycle is not within the specifications. At step 518, the input cycles having high pulse width (HPW) greater than the low pulse width (LPW) are applied. At step 520, accumulator contents are shifted out to measure a duty cycle, and also ripple counter contents are shifted out for checking if in all cycles, the input crosses the lower threshold voltage. At
step 522, a ripple count value and the duty cycle value are checked. At step 524, the low pulse width (LPW) is decreased, when the ripple counter value is N, and the duty cycle is within the specifications. At step 526, a last passed low pulse width value is stored, when the ripple counter value is not N, and the duty cycle is not within the specifications. At step 528, a maximum operating frequency is calculated using a formula as shown in flow diagram.
The technique presented in the present invention offers many advantages. First the proposed circuit can be implemented with a simple and cost effective circuit. Second the proposed circuit having flexibility for an extension for measuring a maximum operating frequency, and its corresponding duty cycle for an output I/O cell as well as input I/O cell. Thirdly, as the circuit operates synchronously with a system clock, hence the circuit can be easily embedded with any controller logic.

We claim:
1. A circuit for on-chip measurement of a maximum operating frequency of an input IUT, said frequency obeying a plurality of conditions at a maximum frequency, said circuit being synchronized with a central controller for a proper handshaking, said circuit comprising:
an input I/O (IUT) terminal for receiving an input voltage signal;
a count register connected to the central controller for storing a number of cycles for which a sample test is performed;
a plurality of programmable loads for determining a maximum frequency at a plurality of loads;
a programmable voltage threshold sensor calibrated at an upper threshold limit and a lower threshold limit for analyzing an output voltage signal from said IUT terminal for a desired threshold voltage level;
a ripple counter connected to said voltage threshold sensor for counting passed output voltage signals from said voltage sensor, the passed output voltage signals obeying the desired threshold voltage level,
a time to digital converter (TDC) receiving the output voltage signal from said IUT terminal for converting a width of said output voltage signal to a binary equivalent value; and
an accumulator connected to said TDC for adding a binary value of said output voltage signal for said number of cycles, said circuit utilizes a binary-to-time domain conversion (BTDC) formula for converting said binary value to a
time domain value, said time domain value is divided by said cycles to calculate an average high pulse width value.
2. The circuit as claimed in claim 1, wherein the plurality of conditions comprises:
a signal transition at an IUT output for a low pulse crossing a specified lower voltage threshold limit;
a signal transition at an IUT output for a high pulse crossing a specified upper voltage threshold limit; and
a duty cycle at an I/O output remains within a specified limit.
3. A method for measuring a maximum operating frequency, and its corresponding
duty cycle variation of an IUT, said method comprising the steps of:
calibrating a time to digital converter (TDC) to formulate a binary to time domain conversion (BTDC) formula;
calibrating a programmable voltage threshold sensor for an upper voltage threshold value and a lower voltage threshold value;
storing a sample test cycle number(N) through a count register;
applying N input cycles having a high pulse width (HPW) less than a low pulse width (LPW);
shifting out accumulator contents to measure a duty cycle;
shifting out ripple counter contents for checking, if said input cycles crosses an upper threshold voltage;
checking a ripple count value, and a duty cycle value;
decreasing said high pulse width (HPW), when the ripple counter value equals to said cycle numbers (N), and the duty cycle value is within a specification;
storing a last passed high pulse width value, when the ripple counter value not equals to said cycle number (N), and the duty cycle value is not within the specification;
applying N input cycles having a high pulse width (HPW) greater than a low pulse width (LPW);
shifting out the accumulator contents to measure a duty cycle;
shifting out the ripple counter contents for checking, if said input cycles crosses a-lower threshold voltage,
checking a ripple count value, and a duty cycle value;
decreasing said low pulse width (LPW), when the ripple counter value equals to said cycle numbers (N), and the duty cycle value is within a specification,
storing a last passed low pulse width value, when the ripple counter value not equals to said cycle number (N), and the duty cycle value is not within the specification; and
calculating said maximum frequency from said passed low pulse width value, and a passed high pulse width value.
4. The method as claimed in claim 3 further comprising providing a flexibility to
measure said maximum operating frequency, and its corresponding duty cycle
variation for an output I/O cell.
5. A circuit for on-chip measurement of a maximum operating frequency of an input
IUT substantially as herein described with reference to the accompanying
drawings.
6 A method for measuring a maximum operating frequency, and its corresponding
duty cycle variation of an IUT substantially as herein described with reference to the accompanying drawings.