DESC:METHOD AND SYSTEM FOR OPTIMIZING DESIGN OF ELECTRONIC ASSEMBLY
CROSS REFERENCE TO RELATED APPLICATIONS
[01] The present application claims priority from Indian Provisional Patent Application No. 202221041425 filed on 19th July 2022, the entirety of which is incorporated herein by a reference.
TECHNICAL FIELD
[02] Generally, the present disclosure relates to a method and system for optimizing design of an electronic assembly. Particularly, the present disclosure relates to the method and system for optimizing design of an electronic assembly by utilizing Electromagnetic interference (EMI) analysis and Electromagnetic compatibility (EMC) analysis of the electronic assembly.
BACKGROUND
[03] Electromagnetic emissions affects the functioning of electronic devices, electrical systems, and radio frequency (RF) systems. Regulatory agencies are formed all over the world to monitor electromagnetic emissions happening from such devices or systems, and to inhibit electromagnetic emission causing unnecessary disturbances.
[04] In automobiles, numerous electronic and electrical assemblies are employed which generate remarkable broadband Electromagnetic Interference (EMI) and bring great challenges in achieving Electromagnetic Compatibility (EMC) designs. The Regulatory agencies have defined EMI regulations and it is mandatory for devices and systems to comply with these regulations.
[05] Compliance with the EMI regulations is determined by conducting tests in multiple phases while designing the electronic and electrical assemblies. This testing and redesigning process is very costly and time consuming. Hence, we require simulation and analytic methods to accurately predict EMI performance and improve the stability and reliability of the assemblies.
[06] Conventional EMI and EMC simulation and analytic methods are not very accurate as they do not take into consideration the mechanical enclosure of the electronic and electrical assembly.
[07] Thus, there exists a need for a simulation and analytic, system and method capable of accurately predicting EMI and EMC performance and accordingly optimizing the design of an electronic assembly.
SUMMARY
[08] An object of the present disclosure is to provide a system for optimizing design of the electronic assembly that accurately predicts EMI and EMC performance of the electronic assembly.
[09] Another object of the present disclosure is to provide a system for optimizing design of the electronic assembly which reduces the time required to perform design optimization of the electronic assembly by simulating EMI and EMC analysis than the conventional simulation for the EMI and EMC analysis.
[010] Another object of the present disclosure is to provide a system for minimizing testing cost involved in the performing design optimization of the electronic assembly than the conventional testing cost involved in the design optimization.
[011] In an aspect of the present disclosure, there is provided a system for optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and an Electromagnetic compatibility (EMC) analysis of the electronic assembly, in accordance with a non-limiting embodiment of the present disclosure. The system comprises an input arrangement configured to receive instructions from an operator, an output arrangement configured to provide the optimized design to the operator, and a data processing arrangement. The data processing arrangement is configured to: identify a plurality of first elements of the electronic assembly based on the instructions received from the operator via the input arrangement, simulate and analyse the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements, import an equivalent circuit model for passive elements of the plurality of first elements, create equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements, perform circuit simulation of the created equivalent circuit for variable operating conditions, create a RLGC model based on parasitic parameters of a plurality of second elements, interconnect the created RLGC model and simulated equivalent circuit, set acceptable limits of the EMI and/or EMC compliance standards, setup a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator, determine non-clearance for a at least one element of a plurality of third elements of the interconnected design to the EMI and/or EMC compliance standards based on the extracted acceptable limits and the plurality of conditions, identify at least one test variable related to the non-clearance for the at least one element of the plurality of third elements, assign variable references for the identified at least one test variable, perform measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements, update the interconnected circuit by using the obtained best fit for optimizing the design, and display the optimized design for the electronic assembly to the operator on the output arrangement.
[012] In another aspect of the present disclosure, there is provided a method for optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and an/or Electromagnetic compatibility (EMC) analysis of the electronic assembly, in accordance with a non-limiting embodiment of the present disclosure. The method comprises identifying a plurality of first elements of the electronic assembly based on instructions received from an operator, via an input arrangement. The method further comprises simulating and analysing the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements. The method further comprises importing an equivalent circuit model for passive elements of the plurality of first elements. The method further comprises creating an equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements. The method further comprises performing circuit simulation of the created equivalent circuit for variable operating conditions. The method further comprises creating a RLGC model based on parasitic parameters of a plurality of second elements. The method further comprises interconnecting the created RLGC model and simulated equivalent circuit. The method further comprises setting acceptable limits of the EMI and/or EMC compliance standards. The method further comprises setting-up a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator. The method further comprises determining non-clearance for at least one element of a plurality of third elements of the interconnected design to the EMI and/or EMC compliance standards based on the extracted acceptable limits and the plurality of conditions. The method further comprises identifying at least one test variable related to the non-clearance for the at least one element of the plurality of third elements. The method further comprises assigning variable references for the identified at least one test variable. The method further comprises performing measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements. The method further comprises updating the interconnected circuit by using the obtained best fit for optimizing the design. Lastly, the method comprises displaying the optimized design for the electronic assembly to the operator on an output arrangement.
[013] The method and the system, as disclosed in the present disclosure is advantageous in terms of accurately predicting EMI and EMC performance of the electronic assembly. Further, the method and the system, as disclosed in the present disclosure, reduces time required to perform design optimization of the electronic assembly by simulating EMI and EMC analysis than the conventional simulation for the EMI and EMC analysis. Furthermore, the method and the system, as disclosed in the present disclosure, minimizes testing cost involved in the process of performing design optimization of the electronic assembly than the conventional testing cost involved in the process of performing design optimization.
[014] The present disclosure overcomes one or more shortcomings of the prior art and provides additional advantages discussed throughout the present disclosure.
[015] Other objects and advantages of the system of the present disclosure will be more apparent from the following description when read in conjunction with the accompanying figures, which are not intended to limit the scope of present disclosure.
[016] Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure.
BRIEF DESCRIPTION OF THE DRAWINGS
[017] The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.
[018] Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:
[019] FIG. 1 illustrates a structure of behavioural EMC and EMI noise model, in accordance with an embodiment of the present disclosure.
[020] FIG. 2 illustrates a block diagram of a system for optimizing design of an electronic assembly, in accordance with an embodiment of the present disclosure.
[021] FIG. 2 illustrates a configuration of a server arrangement, in accordance with an embodiment of the present disclosure.
[022] FIG. 3 illustrates a configuration of a data processing arrangement, in accordance with an embodiment of the present disclosure.
[023] FIG. 4 illustrates an acceptable field strength of radiation emission, in accordance with an embodiment of the present disclosure.
[024] FIG. 5 illustrates a flow chart of steps involved in the method for optimizing design of an electronic assembly, in accordance with an embodiment of the present disclosure.
[025] Common reference numerals are used throughout the drawings and the detailed description to indicate the same elements.
[026] In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.
DETAILED DESCRIPTION:
[027] The following detailed description illustrates embodiments of the present disclosure and ways in which they may be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognise that the other embodiments for carrying out or practicing the present disclosure are also possible.
[028] The detailed description set forth below in connection with the appended drawings is intended as a description of certain embodiments for optimizing design of an electronic assembly and is not intended to represent the only forms that may be developed or utilized. The description sets forth the various structures and/or functions in connection with the illustrated embodiments; however, it is to be understood that the disclosed embodiments are merely exemplary of the present disclosure that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present disclosure.
[029] While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however, that it is not intended to limit the disclosure to the particular forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the disclosure.
[030] The terms “comprises”, “comprising”, “include(s)”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, system or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or system or method. In other words, one or more elements in a system or apparatus preceded by “comprises… a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or apparatus.
[031] In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.
[032] The present disclosure will be described herein below with reference to the accompanying drawings. In the following description, well known functions or constructions are not described in detail since they would obscure the description with unnecessary detail.
[033] Referring to attached drawings, embodiments of the present disclosure will be described below. “front”, “rear”, “right”, “left”, “upper” and “lower” denote each position of a vehicle viewed from a rider. The drawings shall be viewed with regard to the reference numbers.
[034] The present disclosure describes a system that optimizes design of an electric assembly by simulating Electromagnetic interference (EMI) and Electromagnetic compatibility (EMC) analysis of the electronic assembly. The electronic assembly means a number of electronic components (i.e., circuit elements, discrete components, integrated circuits, and so forth) connected together to perform one or more specific functions.
[035] The EMI and EMC are both important considerations when working with electronic components. The EMI is caused by electromagnetic emissions that may disrupt the function of electronic devices and radio frequency (RF) systems. These devices and systems must be properly shielded from electromagnetic radiation for them to work well. The EMC measures how well these devices and systems may work in the presence of disruptive electromagnetic interference.
[036] High performance electrical and electronic architecture modelling of intelligent electric vehicle mainly includes electrical function modelling and electromagnetic interference noise modelling. FIG. 1 is a structure of behavioural of EMC and EMI noise model for a vehicle. The structure describes the EMC modelling 100 that gives a detailed view of all EMC-relevant aspects of a device from the flow of currents across a circuit board, to the propagation of fields between co-site antennas and helps them identify and resolve potential problems before testing. This not only cuts development time and costs, but may also reduce the risk of failing regulatory EMC testing.
[037] FIG. 1 shows that the EMC modelling 100 may be divided into four parts such as product body modelling 102, wire harness topology modelling 104, component modelling 106, and vehicle EMC modelling 108. The product body modelling 102 is an enclosure modelling of a product or a system demonstrates a simulation method to analyse the shielding effectiveness of enclosures. The wire harness topology modelling 104 is an interconnected sub-system modelling of the system demonstrates a simulation method to analyse the interconnection of the different/same sub-systems of the product/system. For example, simulation modelling of connection of one printed circuit board (PCB) to another PCB. The component modelling 106 demonstrates a simulation of components of the system/product to analyze electromagnetic interference effects in components of the system/product.
[038] The EMI of the electronic components for a vehicle are evaluated and validated at a component-level such as the component modelling 106. However, it is sometimes observed that the EMI level of the components may change in a vehicle-level test due to differences in the vehicle's configuration (cable routing, connecting location etc.). Therefore, a vehicle EMC modelling 108 is introduced to estimate radiated emissions from a vehicle. In a vehicle EMC modelling 108, analysis of interference source, coupling path, and sensitive equipment is performed by considering the EMI effect in a vehicle level apart from the individual level in order to predict the performance of the vehicle.
[039] The interference source may be, for example, a high-voltage interference source, a vehicle intelligent control, a vehicle control unit, an external interference source, a communication transmitter, and so forth. The high-voltage interference source may be, for example, an inverter, power converter, a vehicle charger, and so forth. The vehicle intelligent control may be, for example, a global positioning system (GPS), radar, Wireless Fidelity (WiFi), and so forth.
[040] The coupling path may be, for example, a high-voltage cable, a low-voltage cable, an ethernet cable, a controlled area network (MAY) bus cable, and so forth.
[041] The sensitive equipment may be, for example, a trans-receiver communication equipment, an electronic control unit, sensors, and so forth.
[01] Referring to Fig. 2, there is illustrated a block diagram of a system 200 for optimizing design of an electronic assembly by simulating EMI and EMC analysis of the electronic assembly, in accordance with an embodiment of the present disclosure. The system 200, as disclosed in the present disclosure, includes an input arrangement 202, an output arrangement 204, and data processing arrangement 206. All the constituent elements of the system 200 illustrated in FIG. 2 are not essential constituent elements, and the system 200 may be implemented by more constituent elements than the constituent elements illustrated in FIG. 2 or less constituent elements.
[042] FIG. 2 shows that the system 200 for optimizing design of an electronic assembly is same as the vehicle EMC modelling 108 of Fig. 1. In Fig. 2, the input arrangement 202 is connected to output arrangement 204 and data processing arrangement 206 by a wireless/wired connection. The output arrangement 204 is connected to the data processing arrangement 206 by a wireless/wired connection.
[043] The input arrangement 202 may be, but not limited to, a menu screen including texts or image data (including various information data) and data such as icons, a list menu, and a combo box, and the like. The menu screen may be a touch screen.
[044] The input arrangement 202 receives instruction from an operator. The input arrangement 202 displays the type of models associated with the electronic assembly on which tests to be performed. The operator selects one type of model from the types of models. The models include mechanical design information and electrical design information of different electronic assemblies.
[045] In a non-limiting example of an embodiment of the present disclosure, the input arrangement 202 displays a plurality of files of the different electronic assembly. The user (operator) selects a file from the plurality of files on which simulation analysis is to be performed. Each of the plurality of files includes assembly information of components, electrical connection of the components, and electrical parameter information of the respective electronic assembly.
[046] Further, the input arrangement 202 displays types of electronic assembly. The types of electronic assembly are electronic sub-assembly and an integrated assembly. The operator selects one type of electronic assembly from the system 200.
[047] In an alternative embodiment, the input arrangement 202 may be, but not limited to, a USB port, antenna port, and so forth. The input arrangement 202 receives an instruction from an external device. The received instruction includes assembly information of components present in the electronic assembly and electrical connection of components, and electrical parameter information of the components.
[048] The output arrangement 204 may be, but not limited to, a menu screen including texts or image data (including various information data) and data such as icons, a list menu, and a combo box, and the like. The menu screen may be a touch screen.
[049] The output arrangement 204 provides an optimized design to the operator. In particular, the output arrangement 204 displays the modified design of the electronic assembly after simulating the EMI and EMC analysis of the selected electronic assembly.
[050] In an alternative embodiment, the output arrangement 204 may be, but not limited to, a USB port, antenna port, and so forth. The output arrangement 204 transmits information of the optimized design to the external device.
[051] The data processing arrangement 206 generates the modified design of the selected electronic assembly by simulating EMI and EMC analysis of the selected electronic assembly.
[052] The present disclosure discloses the system 200 which optimizes design of the electronic assembly and accurately predicts EMI and EMC performance of the electronic assembly. Further, the system 200 reduces time required to perform design optimization of the electronic assembly by simulating EMI and EMC analysis than the conventional simulation for the EMI and EMC analysis. Furthermore, the system 200 minimizes testing cost involved in the process of performing design optimization of the electronic assembly than the conventional testing cost involved in the process of performing design optimization.
[053] The wired connection may be established using, without limitation, at least one of a wireline cable (for example, High-Definition Multimedia Interface (HDMITM), Mobile High-Definition Link (MHL), DisplayPort, Universal Serial Bus (USB), and so forth.
[054] The wireless connection may be established using, without limitation, at least one of Wireless Fidelity (Wi-Fi), Near Field Communication (NFC), Bluetooth, Bluetooth Low Energy (BLE), Zigbee, Wi-Fi Direct (WFD), and Ultra-Wideband (UWB).
[055] The electronic sub-assembly means a sub-assembly intended to be part of a vehicle, together with any associated electrical connections and wiring, which performs one or more specialised functions in the vehicle. The sub-assembly may be, but not limited to, an assembly of components of electronic circuits, assembly of components of electronic devices, assembly of components of electrical devices, assembly of components present in printed circuit board, and so forth. The integrated assembly means integration of different sub-assemblies.
[056] As illustrated in FIG. 3, the data processing arrangement 300 is constituted by an identification unit 302, analysis unit 304, generation unit 306, processing unit 308, control unit 310, and memory module 312. The data processing arrangement 300 is the same as the data processing arrangement 206 described in FIG. 2. All the constituent elements of the data processing arrangement 300 illustrated in FIG. 3 are not essential constituent elements, and the data processing arrangement 300 may be implemented by more constituent elements than the constituent elements illustrated in FIG. 3 or less constituent elements. All the constituent elements of the data processing arrangement 300 are communicably coupled to each other.
[057] In a non-limiting embodiment of the present disclosure, the identification unit 302 identifies a plurality of first elements of the electronic assembly based on the received instruction. In particular, the identification unit 302 receives information of the electronic assembly and identifies components of the electronic assembly by using the assembly information of different components present in the information of the electronic assembly.
[058] In a non-limiting embodiment of the present disclosure, the identification unit 302 identifies parasitic parameters of each of the identified plurality of first elements. In particular, the identification unit 302 identifies parasitic parameters of the identified elements from the memory module 312. In an alternative embodiment, each of the identified elements includes an information that indicates the parasitic parameters of the respective element. The identification unit 302 identifies/calculates the parasitic parameter of each of the identified elements from the information.
[059] The parasitic parameter indicates a value of a parasitic component present in the elements. The parasitic parameter is associated with an unwanted effect that is unavoidably present in all real electronic devices.
[060] In a non-limiting embodiment of the present disclosure, the identification unit 302 identifies a plurality of second elements of the electronic assembly based on the received instruction. In particular, the identification unit 302 receives information of the selected assembly and identifies the second elements by using the traces present in the selected electronic assembly.
[061] In a non-limiting embodiment of the present disclosure, the analysis unit 304 simulates and analyses the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements. In particular, the analysis unit 304 simulates and analyses circuit components of the identified elements by using the parasitic parameter of the identified elements in order to check feasibility of the identified elements. The simulation and analysis of the identified elements further includes circuit analysis of the identified elements. The circuit analysis of the identified elements includes analysis of the current and voltage at different nodes and lines of a circuit associated with each of the identified elements.
[062] In a non-limiting embodiment of the present disclosure, the generation unit 306 creates an equivalent circuit of the electronic assembly based on imported equivalent circuit model and the analysed plurality of first elements. In particular, firstly, the generation unit 306 imports an equivalent circuit model for passive elements of the identified elements from the memory module 312. After the importation of the equivalent circuit, the generation unit 306 first imports a circuit of the electronic assembly from the memory module 310. After the importation of the circuit of the electronic assembly, the generation unit 306 locates the identified elements and equivalent circuit model in the circuit of the electronic assembly and interconnects the identified elements and equivalent circuit model in the circuit of the electronic assembly.
[063] In a non-limiting embodiment of the present disclosure, the generation unit 306 generates/creates a RLGC model based on parasitic parameters of the second elements of the electronic assembly. The RLCG model is a RLCG Transmission Line block that includes frequency-dependent resistance, inductance, capacitance, and conductance. The transmission line, which may be lossy or lossless, is treated as a two-port linear network.
[064] In a non-limiting example of an embodiment of the present disclosure, after receiving the instruction of the electronic assembly, the identification unit 302 identifies the traces present in the electronic assembly. By using the traces, the identification unit 302 identifies the elements present in the traces. The generation unit 306 creates the RLGC model based on the identified elements that are associated with the identified traces.
[065] In a non-limiting embodiment of the present disclosure, the processing unit 308 performs simulation of the created equivalent circuit for variable operating conditions. In particular, the processing unit 308 performs simulation of the created equivalent circuit for different operation conditions of the circuit in order to identify EMI and EMC performance of the circuit in the different operating conditions.
[066] In a non-limiting example of an embodiment of the present disclosure, the processing unit 308 creates the equivalent circuit of an electronic device. The operating condition of the electronic device is A, B, and C. After that, the processing unit 308 performs the simulation of the created equivalent circuit for each of the operating conditions. The processing unit 308 identifies the less EMI when the created equivalent circuit is simulated in the operating condition of B.
[067] In a non-limiting embodiment of the present disclosure, the processing unit 308 interconnects the created RLGC model with the simulated equivalent circuit. In particular, the processing unit 308 interconnects an input port of the RLGC model with an output port of the simulated equivalent circuit. Alternatively, the processing unit 308 interconnects an input port of the simulated equivalent circuit with an output port of the RLGC model. This interconnection is performed based on the working capability of the assembly.
[068] In a non-limiting embodiment of the present disclosure, the processing unit 308 sets acceptable limits of the EMI and EMC standards. The EMC standards specify the acceptable limit of EMI in any electrical or electronic system. EMC standards ensure that a device’s operation does not disturb the communication system around it or the devices adjacent to it. The acceptable limits of the EMI and EMC standard is associated with Radiated emission measurements. The Radiated emission measurements are unique in that they must always state “the horizontal distance from the Equipment-Under-Test (EUT) to the receiving antenna” in order to compare the measured values to the appropriate regulatory limit. This horizontal distance, which is typically one, three, five, ten, or 30 meters, and the limits (both regulatory and standard-based) associated with those horizontal distances are the subject of this article. Fig. 4 describes the field strength of radiated emissions at a distance of 3 and 10 meters.
[069] In a non-limiting embodiment of the present disclosure, the processing unit 308 sets a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator. The test to be performed on the interconnected design may be, for example, a radiated emission test, a conducted emission test, a radiated immunity test, a conducted immunity test, an electrostatic discharge (ESD) test, an electrical fast transient (EFT) test, or an electrical surge test. The conditions include environment conditions in which test to be performed. Further, the conditions include chamber property in which the interconnected design is placed and a test on the interconnected design is performed in the chamber.
[070] In a non-limiting example of an embodiment of the present disclosure, an interconnected design is placed in a model where the test to be performed on interconnected design. In particular, the input arrangement (such as input arrangement 202) receives model information as the instruction from the operator or an external device. The model information corresponds to hardware set up information where the electronic assembly is placed. The hardware setup information includes information of devices different from the electronic assembly. The processing unit 308 first extracts a model from the model information present in the instruction received from the operator/external device. The processing unit 308 identifies the environment condition of the model, property of the model, property of the component present in the model, and so forth. The processing unit 308 sets the identified conditions for the tests to be performed on the interconnected design.
[071] The interconnected design includes elements of the RLGC model and simulated equivalent circuit. Number of elements of the interconnected design is different from a number of elements of the RLGC model and a number of elements of the simulated equivalent circuit. The identification unit 302 identifies elements of the interconnected design on which the test to be performed.
[072] In a non-limiting embodiment of the present disclosure, the processing unit 308 determines non-clearance for at least one element of a plurality of third elements of the interconnected design to the EMI and EMC compliance standards based on the extracted acceptable limits and the plurality of conditions. In particular, the processing unit 308 performs the test on the elements of the interconnected design by using the set conditions. Further, the processing unit 308 performs an electromagnetic scan on the interconnected design. The electromagnetic scan identifies distribution of electric and magnetic field on the elements. The processing unit 308 identifies failed elements from the elements of the interconnected design based on the performed test and electromagnetic scan The failed elements correspond to those elements whose response is outside the acceptable limits of the EMC and EMI compliance standards. Further, the failed elements are those elements where the distribution of the electric and magnetic field is uneven. Therefore, identification of the failed elements by using the electromagnetic scan eliminates manual operation to identify failed elements.
[073] In a non-limiting embodiment of the present disclosure, the processing unit 308 identifies test variables of each of the failed elements. The test variables are those variables which are responsible for deviation of the response of the respective element outside the acceptable limits. Further, The processing unit 308 assigns variable reference for each of the test variables. Furthermore, the processing unit 308 performs measurable iteration simulation, based on the assigned variable references, for the identified test variables by implementing an opti-metricTM iteration to obtain a best fit for qualifying the non-cleared elements.
[074] The opti-metricTM allows a parametric and optimization analysis of models using multiple variables. The opti-metricTM provides an intuitive interface on top of advanced macro language built into high frequency simulator structure (HFSS). The HFSS is a high-performance full-wave electromagnetic field simulator for arbitrary 3D volumetric passive device modelling.
[075] In a non-limiting example of the embodiment of the present disclosure, the processing unit 308 identifies the two-test variable for a first failed element and three-test variable for a second failed element. The processing unit 308 assigns an upper bound value and lower bound value of each of the two-test variables. The upper bound value and the lower bound value indicate a boundary between a value of a variable varies. The processing unit 308 performs the iteration simulation for the first failed element by changing value of each of the two-test variables. The value of each of the two-test variables is changed within the respective upper bound value and the lower bound value. The processing unit 308 identifies best value of each of the two-test variables which provides the response of the first failed element within the acceptable limits and improves the stability and reliability of the interconnected design. Further, the processing unit 308 assigns an upper bound value and lower bound value of each of the three-test variables. The processing unit 308 performs the iteration simulation for the second failed element by changing value of each of the three-test variables. The processing unit 308 identifies best value of each of the three-test variables which provides the response of the second failed element within the acceptable limits and improve the stability and reliability of the interconnected design.
[076] Furthermore, the processing unit 308 updates the interconnected design by using the best fit for optimizing the design. In particular, the processing unit 308 updates the interconnected design by changing value of variables of each of the failed elements with the identified best value of variables of each of the failed elements.
[077] The memory module 310 stores data, programs, and the like which are required to operate the data processing arrangement 300. Further, the memory module 310 stores parasitic parameters of elements of multiple electronic assemblies. Further, the memory module 310 stores an equivalent circuit model for passive elements of the elements of the multiple electronic assemblies. Furthermore, the memory module 310 stores a circuit of multiple electric assemblies.
[078] The memory module 310 may be, for example, conventional magnetic disks, magnetic tape storage, magneto-optical (MO) storage media, solid state disks, flash memory-based devices, or any other type of non-volatile storage devices suitable for storing large volumes of data. The memory module 310 may also be combinations of such devices. In the case of disk storage media, the memory module 310 may be organized into one or more volumes of redundant array of inexpensive disks (RAID).
[079] The control unit 312 controls an overall function of the data processing arrangement 300. In particular, the control unit 312 controls signal flows and data transmission between components 302-310 of the data processing arrangement 300 and performs data processing functions. The control unit 312 includes a processor which executes the programs stored in the memory module 310 and controls the overall functions of the data processing arrangement 300.
[080] FIG. 5 is a flowchart showing steps of a method 500 for optimizing design of an electronic assembly by simulating EMI and EMC analysis of the electronic assembly, in accordance with a non-limiting embodiment of the present disclosure. The method 500 starts at a step 502, at the step 502 the method includes identifying a plurality of first elements of the electronic assembly based on instructions received from an operator, via an input arrangement (such as the input arrangement 202 of Fig. 1). The instruction received from the operator includes selection of files from a plurality of files displayed on the input arrangement 202. Further, the instruction received from the operator includes selection of types of electronic assembly. The types of electronic assembly include electronic sub-assembly and an integrated assembly.
[081] At a step 504 the method 500 includes simulating and analysing the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements.
[082] At a step 506 the method 500 includes importing an equivalent circuit model for passive elements of the plurality of first elements. At a step 508 the method 500 includes creating an equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements. At a step 510 the method 500 includes performing circuit simulation of the created equivalent circuit for variable operating conditions.
[083] At a step 512 the method 500 includes creating a RLGC model based on parasitic parameters of a plurality of second elements. In particular, the method 500 includes identifying traces present in the electronic assembly, identifying elements associated with the identified traces, and creating the RLGC model based on the identified elements that are associated with the identified traces.
[084] At a step 514 the method 500 includes interconnecting the created RLGC model and simulated equivalent circuit. At a step 516 the method 500 includes setting acceptable limits of the EMI and/or EMC compliance standards.
[085] At a step 518 the method 500 includes setting-up a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator. The test to be performed on the interconnected design may be, for example, a radiated emission test, a conducted emission test, a radiated immunity test, a conducted immunity test, an electrostatic discharge (ESD) test, an electrical fast transient (EFT) test, or an electrical surge test. The conditions include environment conditions in which test to be performed. Further, the conditions include chamber property in which the interconnected design is placed and a test on the interconnected design is performed in the chamber.
[086] At a step 520 the method 500 includes determining non-clearance for at least one element of a plurality of third elements of the interconnected design to the EMI and/or EMC compliance standards based on the extracted acceptable limits and the plurality of conditions. In particular, the method 500 includes performing the at least one test on the plurality of third elements by using the set conditions, scanning on the interconnected design, and identifies at least one element of the plurality of the third elements based on the performed at least one test and electromagnetic scan. The failed elements correspond to those elements whose response is outside the acceptable limits of the EMC and EMI compliance standards. Further, the failed elements are those elements where the distribution of the electric and magnetic field is uneven. Therefore, identification of the failed elements by using the electromagnetic scan eliminates manual operation to identify failed elements.
[087] At a step 522 the method 500 includes identifying at least one test variable related to the non-clearance for the at least one element of the plurality of third elements. At a step 524 the method 500 includes assigning variable references for the identified at least one test variable. At a step 526 the method 500 includes performing measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements. At a step 528 the method 500 includes updating the interconnected circuit by using the obtained best fit for optimizing the design, and displaying the optimized design for the electronic assembly to the operator on an output arrangement (such as the output arrangement 204 of Fig. 1)
[088] The present disclosure discloses that the method 500 which optimizes design of the electronic assembly and accurately predicts EMI and EMC performance of the electronic assembly. Further, the method 500 reduces time required to perform design optimization of the electronic assembly by simulating EMI and EMC analysis then the conventional simulation for the EMI and EMC analysis. Furthermore, the method 500 minimizes testing cost involved in the process of performing design optimization of the electronic assembly then the conventional testing cost involved in the process of performing design optimization.
[089] In the embodiment of the present disclosure, if the electronic sub-assembly is selected by the operator or external device then the steps 502-528 is performed.
[090] In the embodiment of the present disclosure, if the integrated assembly is selected by the operator or external device then the steps 502-528 is performed for each of the electronic sub-assemblies present in the integrated assembly. In particular, the integrated assembly includes integration of a plurality of two sub-assemblies. Step 502-28 is performed for each of the plurality of two sub-assemblies. After that interconnection of plurality of two sub-assemblies is performed. After the interconnection step 516-28 is performed for the interconnected sub-assemblies to identify optimized design for the integrated assembly.
[091] The illustrated steps are set out to explain the exemplary embodiments shown, and it should be anticipated that ongoing technological development will change the manner in which particular functions are performed. These examples are presented herein for purposes of illustration, and not limitation. Further, the boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternative boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.
[092] As will be appreciated by one skilled in the art, the present disclosure may be embodied as a system, method, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.), or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” or “system.” Furthermore, the computer program instructions may also be loaded onto a computer and/or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer and/or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
[093] The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. Further, the user’s computer may include but not limited to cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, infotainment system of the vehicle, and so forth.
[094] The present disclosure is described below with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, may be implemented by computer program instructions.
[095] These computer program instructions may be provided to a processor of a general-purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable medium that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.
[096] A tangible, non-transitory, computer-readable medium may include an electronic, magnetic, optical, electromagnetic, or semiconductor data storage system, apparatus, or device. More specific examples of the computer readable medium would include the following: a portable computer diskette, a Random Access Memory (RAM) circuit, a read-only memory (ROM) circuit, an erasable programmable read-only memory (EPROM or flash memory) circuit, a portable compact disc read-only memory (CD-ROM), and a portable digital video disc read-only memory (DVD/Blu-ray).
[097] As used herein, the terms ‘processing unit’ and ‘processor’ used interchangeably and refer to a computational element that is operable to respond to and processes instructions that drive the system 200. Optionally, the processor includes, but is not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processing circuit. Furthermore, the term “processor” may refer to one or more individual processors, processing devices and various elements associated with a processing device that may be shared by other processing devices. Additionally, the one or more individual processors, processing devices and elements are arranged in various architectures for responding to and processing the instructions that drive the system.
[098] As used herein, the term ‘communicably coupled’ refers to a bi-directional connection between the various components of the data processing arrangement 300. The bi-directional connection between the various components of the data processing arrangement 300 enables exchange of data between two or more components of the data processing arrangement 300. In an exemplary embodiment, the generating unit and the analysis unit are communicably coupled through a network.
[099] Throughout the present disclosure, the term “network” relates to an arrangement of interconnected programmable and/or non-programmable components that are configured to facilitate data communication between one or more electronic devices and/or databases, whether available or known at the time of filing or as later developed. Furthermore, the network may include, but is not limited to, a public network such as the global computer network known as the Internet, a private network, a cellular network and any other communication system or systems at one or more locations. Additionally, the network includes wired or wireless communication that may be carried out via any number of known protocols, including, but not limited to, Internet Protocol (IP), Wireless Access Protocol (WAP), Frame Relay, or Asynchronous Transfer Mode (ATM). Moreover, any other suitable protocols using voice, video, data, or combinations thereof, may also be employed. Moreover, although the system is frequently described herein as being implemented with TCP/IP communications protocols, the system may also be implemented using IPX, Appletalk, IP-6, NetBIOS, OSI, any tunnelling protocol (e.g. IPsec, SSH), or any number of existing or future protocols.
[0100] Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural where appropriate.
[0101] Although embodiments have been described with reference to a number of illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments may be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. More particularly, various variations and modifications are possible in the component parts and/or arrangements of the subject combination arrangement within the scope of the present disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

WE CLAIM:
1. A system (200) for optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and an Electromagnetic compatibility (EMC) analysis of the electronic assembly, the system (200) comprises:
an input arrangement (202) configured to receive instructions from an operator;
an output arrangement (204) configured to provide the optimized design to the operator; and
a data processing arrangement (206) configured to:
identify a plurality of first elements of the electronic assembly based on the instructions received from the operator via the input arrangement;
simulate and analyse the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements;
import an equivalent circuit model for passive elements of the plurality of first elements;
create equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements;
perform circuit simulation of the created equivalent circuit for variable operating conditions;
create a RLGC model based on parasitic parameters of a plurality of second elements;
interconnect the created RLGC model and simulated equivalent circuit;
set acceptable limits of the at least one of the EMI and EMC compliance standards;
setup a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator;
determine non-clearance for a at least one element of a plurality of third elements of the interconnected design to the at least one of the EMI and EMC compliance standards based on the extracted acceptable limits and the plurality of conditions;
identify at least one test variable related to the non-clearance for the at least one element of the plurality of third elements;
assign variable references for the identified at least one test variable;
perform measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements;
update the interconnected circuit by using the obtained best fit for optimizing the design; and
display the optimized design for the electronic assembly to the operator on the output arrangement (204).
2. The system (200) as claimed in claim 1, wherein the data processing arrangement (206) is configured to:
extract parasitic parameters of the plurality of second elements of the electronic assembly; and
create the RLGC model based on the extracted parasitic parameters of the plurality of second elements.
3. The system (200) as claimed in claim 1, wherein the data processing arrangement (206) is configured to:
perform an electromagnetic scan on the interconnected design;
identify the least one element of the plurality of third elements of the interconnected design based on the performed electromagnetic scan, wherein the identified at least one element of the plurality of third elements is associated with an uneven distribution of an electric field and a magnetic field on the at least one element of the plurality of third elements; and
determine non-clearance for the least one third elements of the plurality of third elements based on the identified at least one element of the plurality of third elements.
4. The system (200) as claimed in claim 1, wherein the instruction from the operator includes selection of one of electronic sub assembly and integrated sub assembly.
5. The system (200) as claimed in claim 1, wherein the at least one test includes at least one of a radiated emission, a conducted emission, a radiated immunity, a conducted immunity, an electrostatic discharge (ESD), an electrical fast transient (EFT), or an electrical surge.
6. A method of optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and Electromagnetic compatibility (EMC) analysis of the electronic assembly, the method comprising:
identifying a plurality of first elements of the electronic assembly based on instructions received from an operator, via an input arrangement (202);
simulating and analysing, by a data processing arrangement (206), the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements;
importing, by the data processing arrangement (206), an equivalent circuit model for passive elements of the plurality of first elements;
creating, by the data processing arrangement (206), equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements;
performing, by the data processing arrangement (206), circuit simulation of the created equivalent circuit for variable operating conditions;
creating, by the data processing arrangement (206), a RLGC model based on parasitic parameters of a plurality of second elements;
interconnecting, by the data processing arrangement (206), the created RLGC model and simulated equivalent circuit;
setting, by the data processing arrangement (206), acceptable limits of the at least one of the EMI and EMC compliance standards;
setting-up, by the data processing arrangement (206), a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator;
determining, by the data processing arrangement (206), non-clearance for a at least one element of a plurality of third elements of the interconnected design to the at least one of the EMI and EMC compliance standards based on the extracted acceptable limits and the plurality of conditions;
identifying, by the data processing arrangement (206), at least one test variable related to the non-clearance for the at least one element of the plurality of third elements;
assigning, by the data processing arrangement (206), variable references for the identified at least one test variable;
performing, by the data processing arrangement (206), measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements;
updating, by the data processing arrangement (206), the interconnected circuit by using the obtained best fit for optimizing the design; and
displaying the optimized design for the electronic assembly to the operator on an output arrangement (204).
7. The method as claimed in claim 6, the method further comprises:
extracting, by the data processing arrangement (206), parasitic parameters of the plurality of second elements of the electronic assembly; and
creating, by the data processing arrangement (206), the RLGC model based on the extracted parasitic parameters of the plurality of second elements.
8. The method as claimed in claim 6, the method further comprises:
performing, by the data processing arrangement (206), an electromagnetic scan on the interconnected design;
identifying, by the data processing arrangement (206), the least one element of the plurality of third elements of the interconnected design based on the performed electromagnetic scan, wherein the identified at least one element of the plurality of third elements is associated with an uneven distribution of the electric and magnetic field on the at least one element of the plurality of third elements; and
determining non-clearance for the least one third elements of plurality of third elements based on the identified at least one third elements.
9. The method as claimed in claim 6, wherein the instruction from the operator includes selection of one of electronic sub assembly and integrated sub assembly.
10. The method as claimed in claim 6, wherein the at least one test includes at least one of a radiated emission, a conducted emission, a radiated immunity, a conducted immunity, an electrostatic discharge (ESD), an electrical fast transient (EFT), or an electrical surge.
ABSTRACT

METHOD AND SYSTEM FOR OPTIMIZING DESIGN OF ELECTRONIC ASSEMBLY
The present disclosure describes a system (200) for optimizing design of an electronic assembly. The system (200) comprises an input arrangement (202) configured to receive instructions from an operator, an output arrangement (204) configured to provide the optimized design to the operator, and a data processing arrangement (206). The data processing arrangement (206) is configured to: identify a plurality of first elements of the electronic assembly based on the received instructions, create an equivalent circuit based on an equivalent circuit model and the plurality of first elements, interconnect an RLGC model of the electronic assembly and the equivalent circuit, determine non-clearance for at least one element of a plurality of third elements of the interconnected design, perform measurable iteration simulation for at least one test variable to obtain a best fit, and update the interconnected circuit by using the obtained best fit.
FIG. 5

,CLAIMS:WE CLAIM:
1. A system (200) for optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and an Electromagnetic compatibility (EMC) analysis of the electronic assembly, the system (200) comprises:
an input arrangement (202) configured to receive instructions from an operator;
an output arrangement (204) configured to provide the optimized design to the operator; and
a data processing arrangement (206) configured to:
identify a plurality of first elements of the electronic assembly based on the instructions received from the operator via the input arrangement;
simulate and analyse the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements;
import an equivalent circuit model for passive elements of the plurality of first elements;
create equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements;
perform circuit simulation of the created equivalent circuit for variable operating conditions;
create a RLGC model based on parasitic parameters of a plurality of second elements;
interconnect the created RLGC model and simulated equivalent circuit;
set acceptable limits of the at least one of the EMI and EMC compliance standards;
setup a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator;
determine non-clearance for a at least one element of a plurality of third elements of the interconnected design to the at least one of the EMI and EMC compliance standards based on the extracted acceptable limits and the plurality of conditions;
identify at least one test variable related to the non-clearance for the at least one element of the plurality of third elements;
assign variable references for the identified at least one test variable;
perform measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements;
update the interconnected circuit by using the obtained best fit for optimizing the design; and
display the optimized design for the electronic assembly to the operator on the output arrangement (204).
2. The system (200) as claimed in claim 1, wherein the data processing arrangement (206) is configured to:
extract parasitic parameters of the plurality of second elements of the electronic assembly; and
create the RLGC model based on the extracted parasitic parameters of the plurality of second elements.
3. The system (200) as claimed in claim 1, wherein the data processing arrangement (206) is configured to:
perform an electromagnetic scan on the interconnected design;
identify the least one element of the plurality of third elements of the interconnected design based on the performed electromagnetic scan, wherein the identified at least one element of the plurality of third elements is associated with an uneven distribution of an electric field and a magnetic field on the at least one element of the plurality of third elements; and
determine non-clearance for the least one third elements of the plurality of third elements based on the identified at least one element of the plurality of third elements.
4. The system (200) as claimed in claim 1, wherein the instruction from the operator includes selection of one of electronic sub assembly and integrated sub assembly.
5. The system (200) as claimed in claim 1, wherein the at least one test includes at least one of a radiated emission, a conducted emission, a radiated immunity, a conducted immunity, an electrostatic discharge (ESD), an electrical fast transient (EFT), or an electrical surge.
6. A method of optimizing design of an electronic assembly by simulating at least one of an Electromagnetic interference (EMI) and Electromagnetic compatibility (EMC) analysis of the electronic assembly, the method comprising:
identifying a plurality of first elements of the electronic assembly based on instructions received from an operator, via an input arrangement (202);
simulating and analysing, by a data processing arrangement (206), the identified plurality of first elements by calculating at least one parasitic parameter associated with the identified plurality of first elements;
importing, by the data processing arrangement (206), an equivalent circuit model for passive elements of the plurality of first elements;
creating, by the data processing arrangement (206), equivalent circuit of the electronic assembly based on the imported equivalent circuit model and the analysed plurality of first elements;
performing, by the data processing arrangement (206), circuit simulation of the created equivalent circuit for variable operating conditions;
creating, by the data processing arrangement (206), a RLGC model based on parasitic parameters of a plurality of second elements;
interconnecting, by the data processing arrangement (206), the created RLGC model and simulated equivalent circuit;
setting, by the data processing arrangement (206), acceptable limits of the at least one of the EMI and EMC compliance standards;
setting-up, by the data processing arrangement (206), a plurality of conditions for at least one test to be performed on the interconnected design based on the instructions received from the operator;
determining, by the data processing arrangement (206), non-clearance for a at least one element of a plurality of third elements of the interconnected design to the at least one of the EMI and EMC compliance standards based on the extracted acceptable limits and the plurality of conditions;
identifying, by the data processing arrangement (206), at least one test variable related to the non-clearance for the at least one element of the plurality of third elements;
assigning, by the data processing arrangement (206), variable references for the identified at least one test variable;
performing, by the data processing arrangement (206), measurable iteration simulation, based on the assigned variable references, for the identified at least one test variable by implementing an opti-metric iteration to obtain a best fit for qualifying the non-cleared elements;
updating, by the data processing arrangement (206), the interconnected circuit by using the obtained best fit for optimizing the design; and
displaying the optimized design for the electronic assembly to the operator on an output arrangement (204).
7. The method as claimed in claim 6, the method further comprises:
extracting, by the data processing arrangement (206), parasitic parameters of the plurality of second elements of the electronic assembly; and
creating, by the data processing arrangement (206), the RLGC model based on the extracted parasitic parameters of the plurality of second elements.
8. The method as claimed in claim 6, the method further comprises:
performing, by the data processing arrangement (206), an electromagnetic scan on the interconnected design;
identifying, by the data processing arrangement (206), the least one element of the plurality of third elements of the interconnected design based on the performed electromagnetic scan, wherein the identified at least one element of the plurality of third elements is associated with an uneven distribution of the electric and magnetic field on the at least one element of the plurality of third elements; and
determining non-clearance for the least one third elements of plurality of third elements based on the identified at least one third elements.
9. The method as claimed in claim 6, wherein the instruction from the operator includes selection of one of electronic sub assembly and integrated sub assembly.
10. The method as claimed in claim 6, wherein the at least one test includes at least one of a radiated emission, a conducted emission, a radiated immunity, a conducted immunity, an electrostatic discharge (ESD), an electrical fast transient (EFT), or an electrical surge.