CLIAMS:We claim:
1. A method of testing a software, the method comprising:
providing an input event to the software under test, wherein the software under test is associated with a time delay between the input event and an output event;
identifying one or more discrete time instances based on the time delay between the input event and the output event; and
testing the software under test by synthetically setting a clock to the one or more discrete time instances, wherein synthetically setting the clock to the one or more discrete time instances comprises providing predetermined inputs sequentially at the one or more discrete time instances.

2. The method of claim 1, wherein the input event comprises a Boolean expression of a plurality of sub-events.

3. The method of claim 1, wherein the output event triggers a second event under test and wherein the second event may be a single event or a Boolean expression of a plurality of second set of sub-events.

4. The method of claim 1, wherein the one or more discrete time instances are identified based on a function of the time delay between the input event and the output event.

5. The method of claim 1, wherein testing the software under test comprises comparing the output event with a predetermined expected output.

6. The method of claim 1, wherein synthetically setting the clock comprises progressing the clock independent from the wall clock time.

7. An apparatus for testing a software, comprising:
a processor; and
a memory disposed in communication with the processor and storing processor-executable instructions, the instructions comprising instructions to:
provide an input event to the software under test, wherein the software under test is associated with a time delay between the input event and an output event;
identify one or more discrete time instances based on the time delay between the input event and the output event;
test the software under test by synthetically setting a clock associated with the processor to the one or more discrete time instances, wherein synthetically setting the clock to the one or more discrete time instances comprises providing predetermined inputs sequentially at the one or more discrete time instances.

8. The apparatus of claim 7, wherein the input event comprises a Boolean expression of a plurality of sub-events.

9. The apparatus of claim 7, wherein the output event triggers a second event under test, and wherein the second event may be a single event or a Boolean expression of second set of sub-events.

10. The apparatus of claim 7, wherein the one or more discrete time instances are identified based on a function of the time delay between the input event and the output event.

11. The apparatus of claim 7, wherein testing the software under test comprises comparing the output event with a predetermined expected output.

12. The apparatus of claim 7, wherein synthetically setting the clock comprises progressing the clock independent from the wall clock time.

13. A non-transitory computer-readable storage medium storing instructions which when executed by a processor enable the processor to test a software, the instructions comprising instructions to:
provide an input event to the software under test, wherein the software under test is associated with a time delay between the input event and an output event;
identify one or more discrete time instances based on the time delay between the input event and the output event;
test the software under test by synthetically setting a clock to the one or more discrete time instances, wherein synthetically setting the clock to the one or more discrete time instances comprises providing predetermined inputs sequentially at the one or more discrete time instances.

Dated this 29th day of December, 2014

Swetha S.N
Of K&S Partners
Agent for the Applicant
,TagSPECI:TECHNICAL FIELD
This disclosure relates generally to software testing, and more particularly to a method and system for time scaled testing.