Claims:CLAIMS
What is claimed is:
1. A method for measuring throughput of a semi-conductor manufacturing tool, said method comprising:
receiving a layout of said semi-conductor manufacturing tool as input, by an Input/Output (I/O) interface sub-module of a throughput determination module;
determining number of wafers to be processed by said semi-conductor manufacturing tool, automatically, by an optimization sub-module of said throughput determination module;
scheduling automatically, at least one slot for processing said input, by a path detection sub-module of said throughput determination module;
determining a time for said input to enter said at least one slot, based on a feedback value, by a time assessment sub-module of said throughput determination module; and
determining a process completion time, by said time assessment sub-module, wherein said process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by said layout.
2. The method as claimed in claim 1, wherein said number of wafers to be processed is determined based on number of processing modules in said tool, by said optimization sub-module.
3. The method as claimed in claim 1, wherein said slot is scheduled based on at least one of a transfer time, processing time, shortest path value, and waiting time, by said path detection sub-module.
4. The method as claimed in claim 1, wherein determining said time to enter said at least one slot further comprises of:
checking a nodeTime entered by a wafer that has been entered by at least one other wafer previously processed by said at least one slot, by said time assessment sub-module, wherein said nodeTime indicates time from which said at least one slot is available for processing;
identifying said time indicated by said nodeTime as the time to enter said at least one node, by said time assessment sub-module; and
adding a wait time to said identified time, if required, by said time assessment sub-module.
5. The method as claimed in claim 1, wherein said process completion time is determined based on at least one of a nodeTime corresponding to each slot, and a processing capability of at least one processing module in said semi-conductor manufacturing tool represented by said layout, by said time assessment sub-module.
6. A system for measuring throughput of a semi-conductor manufacturing tool, said system configured for:
receiving a layout of said semi-conductor manufacturing tool as input, by an Input/Output (I/O) interface sub-module of a throughput determination system;
determining number of wafers to be processed by said semi-conductor manufacturing tool, automatically, by an optimization sub-module of said throughput determination system;
scheduling automatically, at least one slot for processing said input, by a path detection sub-module of said throughput determination system;
determining a time for said input to enter said at least one slot, based on a feedback value, by a time assessment sub-module of said throughput determination system; and
determining a process completion time, by said time assessment sub-module, wherein said process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by said layout.
7. The system as claimed in claim 6, wherein said optimization sub-module is configured to determine said number of wafers to be processed, based on number of processing modules in said semi-conductor manufacturing tool, by said optimization sub-module.
8. The system as claimed in claim 6, wherein said path detection sub-module is configured to schedule said slot based on at least one of a transfer time, processing time, shortest path value, and waiting time.
9. The system as claimed in claim 6, wherein said time assessment sub-module is configured to determine said time to enter said at least one slot by:
checking a nodeTime entered by a wafer that has been entered by at least one other wafer previously processed by said at least one slot, wherein said nodeTime indicates time from which said at least one slot is available for processing;
identifying said time indicated by said nodeTime as the time to enter said at least one node; and
adding a wait time to said identified time, if required.
10. The system as claimed in claim 6, wherein said time assessment sub-module is configured to determine said process completion time based on at least one of a nodeTime corresponding to each slot, and a processing capability of at least one processing module, in said semi-conductor manufacturing tool represented by said layout.

Dated this 31st July 2015

Signature:
Name: Kalyan Chakravarthy
(Patent Agent)
, Description:FORM 2
The Patent Act 1970
(39 of 1970)
&
The Patent Rules, 2005

COMPLETE SPECIFICATION
(SEE SECTION 10 AND RULE 13)

TITLE OF THE INVENTION

“Method and System for throughput determination of a Semiconductor cluster tool”

APPLICANTS:

Name Nationality Address
SAMSUNG R&D Institute India - Bangalore Private Limited India # 2870, Orion Building, Bagmane Constellation Business Park, Outer Ring Road, Doddanekundi Circle, Marathahalli Post,Bangalore-560 037, India

The following specification particularly describes and ascertains the nature of this invention and the manner in which it is to be performed:-
TECHNICAL FIELD
[001] The embodiments herein relate to tool manufacturing and, more particularly, to predict throughput of equipments used in semi-conductor chip manufacturing.
BACKGROUND
[002] Any manufacturing industry uses a number of tools at various stages of production. Efficiency and throughput of a production unit increases with increase in efficiency of tools used. Efficiency may be defined in terms of various parameters such as speed of the tools (i.e. number of outputs in a given time), and quality of output.
[003] Manufacturers of the tools are engaged in continuous research to develop tools with higher efficiency. Traditional method involves developing tools, testing their efficiency, and making necessary modifications if necessary. However, this is not a feasible solution as the tool itself may be huge and complicated to be manufactured and modified every time.
[004] Another method being practiced by the industry involves determining throughput of a tool, with the help of throughput models. In this method, throughput of a tool is determined for a desired manufacturing scenario, based on throughput models that are generated by a system. The throughput thus generated can be used by a user/designer to assess performance of the tool, and make changes if required. However, systems that function based on the throughput models have the disadvantage that they are configured for a particular type of tool, hence lacking inter-operability.

OBJECT OF INVENTION
[005] An object of the embodiments herein is to measure throughput of a tool, based on a layout of the tool inputted by a user.

SUMMARY
[006] In view of the foregoing, an embodiment herein provides a method for measuring throughput of a semi-conductor manufacturing tool. A layout of the semi-conductor manufacturing tool is received as input, by an Input/Output (I/O) interface sub-module of the throughput determination module. Further, number of wafers to be processed by the semi-conductor manufacturing tool is determined automatically, by an optimization sub-module of the throughput determination module. Further, at least one slot for processing the input is scheduled automatically, by a path detection sub-module of the throughput determination module. Further, a time for the input to enter the at least one slot is determined, based on a feedback value, by a time assessment sub-module of the throughput determination module. Further, a process completion time is determined, by the time assessment sub-module, wherein the process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by the layout.
[007] Embodiments further disclose a system for measuring throughput of a semi-conductor manufacturing tool. The system is configured for receiving a layout of the semi-conductor manufacturing tool as input, by an Input/Output (I/O) interface of the throughput determination module. Further, number of wafers to be processed by the semi-conductor manufacturing tool is determined automatically, by an optimization sub-module of the throughput determination module. Further, at least one slot for processing the input is scheduled automatically, by a path detection sub-module of the throughput determination module. Further, a time for the input to enter the at least one slot is determined, based on a feedback value, by a time assessment sub-module of the throughput determination module. Further, a process completion time is determined, by the time assessment sub-module, wherein the process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by the layout.
[008] These and other aspects of the embodiments herein will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES
[009] The embodiments herein will be better understood from the following detailed description with reference to the drawings, in which:
[0010] FIG. 1 illustrates a block diagram of a throughput determination module, as disclosed in the embodiments herein;
[0011] FIG. 2 illustrates a block diagram that shows components of a throughput determination module, as disclosed in the embodiments herein;
[0012] FIG. 3 is a flow diagram that depicts steps involved in the process of determining throughput of a tool, using the throughput determination module, as disclosed in the embodiments herein; and
[0013] FIG. 4 depicts an example layout for which throughput is determined using the throughput determination module, as disclosed in the embodiments herein.

DETAILED DESCRIPTION OF EMBODIMENTS
[0014] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein may be practiced and to further enable those of skill in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.
[0015] The embodiments herein disclose a throughput measurement system. The throughput measurement system disclosed herein can be used to measure and predict throughput of a semiconductor chip manufacturing tool, and any such tool that can be modeled as components and component behaviors. Referring now to the drawings, and more particularly to FIGS. 1 through 4, where similar reference characters denote corresponding features consistently throughout the figures, there are shown embodiments.
[0016] FIG. 1 illustrates a block diagram of a throughput determination module, as disclosed in the embodiments herein. The throughput determination module 100 can be configured to receive, using a suitable input module of the throughput determination module 100, at least one real-time design and configuration of a semi-conductor manufacturing tool/SEMI cluster tool (hereinafter referred to as tool) as input, for measuring throughput of the tool. In a preferred embodiment, the input is a layout of the tool, wherein the layout indicates number of components at each stage of the tool, and connection between each component. The input may further comprise of value of at least one parameter associated with at least one component depicted in the layout. For example, the input can be name and/or type of a component that is intended to be present in the tool as indicated by the layout. The throughput determination module 100 can be further configured to possess information pertaining to capability of each component, in terms of at least one performance parameter that defines performance speed of the component. The throughput determination module 100 can be further configured to determine throughput of the tool being represented by the layout, based on real-time configuration received as input. In a preferred embodiment, the throughput of a tool is determined in terms of time taken by the tool to process all inputs. The throughput determination module 100 can be further configured to provide at least one option for the user to specify and change components that may constitute the tool as represented by the layout; such that change in throughput of the tool with different components can be determined.
[0017] FIG. 2 illustrates a block diagram that shows components of a throughput determination module, as disclosed in the embodiments herein. The throughput determination module 100 comprises of an optimization sub-module 201, a path detection sub-module 202, a time assessment sub-module 203, a memory sub-module 206, and an Input/Output (I/O) interface sub-module 207. The time assessment sub-module 203 further comprises of a correction sub-module 204, and a feedback generation sub-module 205.
[0018] The optimizations module 201 can be configured to determine an optimum number of wafers that can be processed in one iteration. In a semi-conductor manufacturing tool, wafers to be processed enter a processing chamber from a loadlock. If the number of slots in the processing chamber is less than the number of slots in the loadlock, wafers that are in the loadlock may have to wait for some time to enter the processing chamber, which in turn causes a delay. In order to avoid this, the optimization sub-module 201 determines optimum number of wafers such that wafers in loadlock can enter the processing chamber, with minimum waiting period. In a preferred embodiment, the optimization chamber determines the optimum number of wafers, based on a Full Capacity Number (FCN) that is calculated as:
Full Capacity Number (FCN) = Min (Slots in loadlock, Slots in processing chamber) ----- (1)
[0019] The path detection sub-module 202 can be configured to determine a path using which the wafer can be moved to next node. In an embodiment wherein only one path is available between a source node (where the wafer is currently placed) and a destination node (to which the wafer needs to be moved), by default, that path is used. In another embodiment wherein more than one path is present between the source and destination nodes, the path detection sub-module 202 selects at least one path from the available paths, based on heuristics; wherein heuristics is a combination of at least two of the following parameters:
1) Transfer time:- Indicates transfer time for a path (For example, in a semi-conductor manufacturing tool, the transfer time can vary for different processing chambers, for the same robot)
2) Processing time:- Processing time specific to processing chambers (This can vary based on factors such as but not limited to Aging of processing chambers)
3) Shortest path to destination:- Indicates shortest path to reach destination, through a selected path
4) Waiting Time: - Represents time taken for a processing chamber to be ready after undergoing pre-processing. This in turn indicates time for which the wafer may have to wait to enter the processing chamber.
[0020] Assuming that parameters listed above are used for determining the heuristics value, the value can be determined as:
Heuristics Value = (Shortest path) alpha * (transfer time) beta * (waiting time) gamma * (processing time) delta ---------- (2)
[0021] The time assessment sub-module 203 can be configured to determine time for a wafer to enter a slot. In a preferred embodiment, the time assessment sub-module determines the time for the wafer to enter the slot, based on a nodeTime being collected from the feedback generation sub-module 205. Here the NodeTime for a particular slot/node represents time period during which the node/slot is available for processing. The time assessment sub-module 203 can be further configured to determine the throughput of the tool, in terms of time. In this process, the time assessment sub-module 203 can consider factors such as but not limited to layout of the tool, paths between components of the tool indicated by the layout, nodeTime, and capacity of the processing module. In a preferred embodiment, the time assessment sub-module 203 collects correction data and feedback time from the correction sub-module 204 and the feedback generation sub-module 205 respectively; and uses the correction data and the feedback time information for determining the time for the wafer to enter the slot.
[0022] The correction sub-module 204 can be configured to check if any correction is required, in terms of the path selected for a wafer, and make necessary corrections to the path. For example, while determining a path for the wafer, current states of components are considered. But in some scenarios, it is possible that the state of at least one component is changed by any other wafer, after determining the path. In this case, path correction is required, as the wafer cannot proceed on the path that was previously decided.
[0023] The feedback generation sub-module 205 can be configured to identify a nodeTime corresponding to a node being considered, and provide the nodeTime as a feedback time that represents time at which the node being considered is available, to the time assessment sub-module 203. In an embodiment, the time assessment sub-module 203 can be configured to collect details pertaining to a path being considered by the path detection sub-module 202, identify nodes in the path, and collect corresponding nodeTime.
[0024] The memory sub-module 206 can be configured to store all data required to execute the throughput determination process. In an embodiment, the memory sub-module 206 can store static information that is pre-configured by an authorized user. For example, performance parameters of various components can be stored as static information. In another embodiment, the memory sub-module 206 can dynamically receive and store information, for further processing. For example configuration data as well as layouts can be received and stored as dynamic inputs. The memory sub-module 206 can be configured to support actions such as but not limited to editing, formatting, and deletion of data stored in the memory sub-module 206.
[0025] The I/O interface sub-module 207 can be configured to provide at least one option for a user to provide at least one input to the throughput determination module 100. The I/O interface sub-module 207 can be further configured to provide output of the throughput determination module 100 to the user, in at least one suitable format, as pre-configured by a user.
[0026] FIG. 3 is a flow diagram that depicts steps involved in the process of determining throughput of a tool, using the throughput determination module, as disclosed in the embodiments herein. In order to determine throughput of a tool, layout of the tool is provided as input to the throughput determination module 100. Upon receiving the layout, the throughput determination module 100 parses, and analyzes the input to identify structure of the tool, wherein ‘structure of the tool’ refers to information such as but not limited to components of the tool, various stages of the tool, number of slots at each stage, connections between different stages, different slots, and processing modules.
[0027] The throughput determination module 100 further collects information pertaining to number of wafers to be processed. Further, the optimization sub-module 201 of the throughput determination module 100 generates a FCN value based of the layout, and determines (302) number of inputs that the tool can process at a time.
[0028] Further, path for the wafer to enter different stages of the tool is determined (304) by the path detection sub-module 202. In a preferred embodiment, the path is determined based on a heuristics value generated by the path detection sub-module 202, in a scenario wherein more than one path is available between a source and destination.
[0029] Further, time for the wafer to enter a node is scheduled (306) by the time assessment sub-module 203 of the throughput determination module 100. In an embodiment, the scheduling may not be required in a first iteration of the manufacturing, in which all stages of the tool are assumed to be free. However, in successive iterations, the scheduling is required, as the nodes may not be free all the time. In the throughput determination module 100, time at which each wafer enters and leaves each node is marked as nodeTime. The nodeTimes marked by different wafers for different nodes can collectively indicate time of availability of each node. The nodeTime entered by different wafers act as a reference data for other nodes in the same and/or subsequent iterations.
[0030] Further, the system checks (308) if correction is required or not, wherein correction refers to any adjustment for the pre-decided time schedule for entering at least one node in at least one stage of the tool. The system can be configured to decide whether the correction is required or not, by checking if the schedule can result in any deadlock, due to change in status of any node, after the schedule has been decided initially by the time assessment sub-module 203.
[0031] If any correction is found to be required, the time assessment sub-module 203 makes (310) the required correction, wherein making correction may refer to adjusting the scheduled time by adding or subtracting any suitable offset value, such that the time as per the new schedule does not result in a deadlock condition.
[0032] Further, the throughput of the tool is measured (312) by the time assessment sub-module 203. In a preferred embodiment, the throughput is measured in terms of time within which the tool can process all the inputs i.e. wafers. Assume that there are 4 wafers in total, and the tool can process only 2 at a time. That means two iterations are required. In this scenario, the throughput determination module 100 determines total time required by the tool indicated by the layout to process all 4 wafers. The user can change configuration of the layout dynamically, and observe change in throughput of the tool with change in configuration; thus can identify the configuration that provides a desired throughput. The measured throughput may be then provided to the user in a suitable format, using the I/O interface 207.
[0033] The various actions in method 300 may be performed in the order presented, in a different order or simultaneously. Further, in some embodiments, some actions listed in FIG. 3 may be omitted.
Use case scenario:
[0034] Consider the layout depicted in Fig. 4. Let us consider:
i. Load Port is source and destination
ii. all edge weights are 5 units
iii. Processing Module’s processing time is 10 units
iv. LoadLock pump and vent time is 10 time units
[0035] Recipe steps are:
i. PM1 or PM2
ii. Cooler
[0036] Assuming that the Load Port is source and destination, time taken to process x wafers using the design and configuration of the given layout as:
[0037] In the layout depicted in Fig. 4, slots represent nodes and transfer time represents edge weight.
[0038] For the given layout, the FCN is calculated as:
[0039] FCN = Min (slots in Loadlock leading to PM, slots in Processing Chamber)
= Min (2, 4)
= 2
[0040] So, FCN is calculated as 2 and so, in each iteration, 2 wafers can complete their wafer cycle.
[0041] Please note that, unless the first iteration completes, the second iteration cannot start. Also, wafers are created and start from source component.

Iteration 1:
[0042] The first wafer i.e. wafer1 is present in slot 1 of LoadPort. Upon detecting that there are 2 outgoing paths, the wafer 1 uses heuristics to determine the best outgoing path. Since, both the paths have same transfer time, no waiting time, same shortest path and no processing time, both are optimal. Wafer1 selects node 3 as next target node and visits node 3. Similarly, wafer1 visits node 5 of LoadLock at time 10 units. While leaving node 3, wafer1 adds an entry of 0-10 (0 is entryTime and 5 is exitTime) in node 3. Upon reaching the LoadLock, the wafer 1 checks if wafers in LoadLock are equal to FCN, and finds out another wafer can be accommodated according to FCN rule.
[0043] Second wafer i.e. wafer2 present in slot 1 of LoadPort starts its cycle. Wafer2 uses heuristics to find the next outgoing path. As path leading to node 3 exitTime of 5 time units, wafer2 knows that path is available only after 5 time units. So, the heuristics gives path leading to node 4 as the optimal path since node 4 has exitTime of 0 time units; making it the best path. Wafer2 visits node 4 and moves towards node 6 of LoadLock. While leaving node 4, wafer2 adds an entry of 0-5(0 is entryTime and 5 is exitTime) in node 4. After reaching LoadLock, wafer2 finds out that number of wafers in LoadLock are equal to FCN. So, next wafer cycle is not started unless both wafer1 and wafer2 cycle are completed.
[0044] Both the wafers reach the LoadLock at 10 time units. Both the wafers pump the LoadLock to Vacuum state at time 20 time units.
[0045] Wafer1 finds only one outgoing edge from current node 5. So, it adds the entry of 10-20 in node 5 and visits node 9 at time 25. Node 9 has 2 outgoing edges and according to heuristics, both are equally optimal. So, wafer1 visits node 11 at time 30 time units. It also adds the entry 20-30 node 9 as 25 units. Wafer2 similarly visits node 10 at time 25 units. Now, wafer2 has two outgoing paths one leading to PM1 and other leading to PM2. Both of the paths are equally optimal. But, wafer2 chooses node 12 of PM1 since its peer wafer i.e. wafer1 has opted for PM1.
[0046] So, both the wafers reach Processing Module 1 (PM1) at time 30 time units, and they get processed in PM1 for 10 time units i.e. processing of both the wafers is completed at 40 units. Since PM1 is included in recipe too, recipe step index is incremented to reflect the next recipe step.
[0047] After completing the PM processing, wafer1 moves towards node 9 and reaches node 9 at time 45. Since the next target node belongs to LoadLock, wafer1 checks if the LoadLock is in Vacuum state at 45 time units. LoadLock is in Vacuum state at 45 units. So, wafer1 reaches node 7 at time 50 time units. Similarly, wafer2 reaches node 10 at 45 units and then node 8 at time 50, and adds the entry 40-50 to node 10. Both wafers vent LoadLock at time 60 units, and add entry 50-60 to node 7 and node 8.
[0048] Wafer1 reaches node 3 at 65 units and it has two paths: one leading to destination and other leading to Cooler. Since Cooler is the next recipe step, wafer1 visits Cooler at time 70 units. Similarly, wafer2 reaches Cooler at 70 time units. Both wafers get processed in Cooler for 5 units i.e. total time becomes 75 units. Since, recipe step is visited, recipe index is incremented. Also, an entry of 70-75 is added to node 15 and node 16. Wafer1 visits node 3 at 80 units and since all recipe steps are visited, wafer1 moves back to LoadPort at 85 units. Entry of 75-85 is added to node 3. Similarly, wafer2 returns to destination LoadPort and an entry of 75-85 is added to node 4 and the first iteration ends.
Equipment Nodes Iteration 1
(Entry Time - Exit Time)
Robot 1 3, 4 0-10, 60-70
LoadLock 5, 6 10-20,
7, 8 50-60
Robot 2 9, 10 20-30, 40-50
PM1 11, 12 30-40
Cooler 15, 16 70-75
Table 1: Entries in Nodes after Iteration 1

Iteration 2:
[0049] After wafer1 and wafer2 are completely processed, iteration 2 starts. Wafer3 present in LoadLock starts its execution. Wafer3 has two outgoing paths: one path leading to node 3 and one path leading to node 4. Wafer3 checks the entries made by previous wafers (wafer1 and wafer2 in this example scenario) in node 3 and node 4 to find out when the nodes are available. Wafer1 and wafer2 have made three entries: 0-10, 60-70 and 75-85 in node 3 and node 4 respectively, and it indicates that node 3 and node 4 are available from 10-60 units.
[0050] Wafer3 uses heuristics to find out the best outgoing path, which is path leading to node 3. Wafer3 starts from node 1 at time 10 units and reaches node 3 at time 15 units. Since the next node is LoadLock, Wafer3 checks the state of LoadLock at time 20 units (since wafer3 will take additional 5 units to reach LoadLock). LoadLock was at Vacuum state at 20 time units. Wafer3 vents LoadLock at time 30 units and enters node 5.
[0051] Similarly, wafer4 reaches node 6 at 30 time units. Both wafers add entry 10-30 in node 3 and node 4. Wafer3 and wafer4 pump LoadLock at time 40 units. Wafer3 tries to reach next target node 9 at time 40. But, node 9 has an entry 40-50. So, wafer3 knows that node 9 is not available until 50 time units. Hence, wafer3 waits until 50 time units in node 5. At time 50, wafer3 moves towards node 9 and reaches node 9 at 55 units. Wafer3 has 2 paths: one leading to node 11 and other leading to node 13. According to heuristics, both the nodes have same optimality. So, wafer3 chooses node 11 and reaches node 11 at time 60.
[0052] Similarly, wafer4 reaches node 12 at time 60. Both wafers add entry 20-50 to node 5 and node 6 respectively. Also, they add entry 50-60 to node 9 and node 10 respectively. Both the wafers get processed in PM1 until 70 units. They add entry 60-70 to node 11 and node 12 respectively. Wafer3 reaches node 9 at time 75 and tries to enter in LoadLock. But, LoadLock at time 75 is in Atmospheric state. So, wafer3 pumps LoadLock and enters node 7 at time 90 units. Similarly, wafer4 enters node 8 at 90 units. An entry of 70-90 is added to node 9 and node 10 respectively. Both wafers vent LoadLock at 100 units. While leaving LoadLock, entry 90-100 is added to node 7 and node 8.
[0053] Wafer3 reaches node 3 at time 105 and it follows recipe which takes it to node 15. It reaches node 15 at time 110. Similarly, wafer4 reaches node 16 at time 110. Both the wafers are processed in cooler until 115 when wafer3 visits node 3. Since the recipe is completed, wafer3 moves back to destination node 1 at time 125. Also, wafer4 moves back to node 1 at time 125.
Equipment Nodes Iteration 1
(Entry Time - Exit Time) Iteration 2
(Entry Time - Exit Time)
Robot 1 3, 4 0-10, 60-70, 75-85 10-30, 100-110, 115-125
LoadLock 5, 6 10-20 20-50
7, 8 50-60 80-100
Robot 2 9, 10 20-30, 40-50 50-60, 70-90
PM1 11, 12 30-40 60-70
Cooler 15, 16 70-75 110-115
Table 2: Entries in Nodes after Iteration 2

Iteration 3:
[0054] After wafer3 and wafer4 return back to destination, iteration 3 starts. In iteration 3, wafer5 and wafer6 will be processed. Based on the entries made in Table. 1 and Table. 2, it can be seen that LoadLock is not available until 60 units and Robot1 i.e. node 3 is not busy from 30-60. So, wafer5 starts its execution at 50 units. It has two outgoing paths: one leading to node 3 and other leading to node 4. Heuristics assigns same optimality to both paths. Wafer5 chooses node 3 and it reaches node 3 at time 55. Since the next node 5 is in LoadLock, it checks if LoadLock is in Atmospheric state at time 60 (since 5 is additional transfer time). LoadLock is in Atmospheric state at time 60. So, wafer5 moves to node 5 at time 60. Since, FCN is greater than number of wafers, wafer6 also follows the same process and enters node 6 at time 60.
[0055] Both the wafers pump LoadLock to Vacuum state at time 70. After pumping, wafer5 checks if this state change in LoadLock affects any previous wafers i.e. wafer5 checks if there is any previous wafer which has considered LoadLock in Atmospheric state after 70 time units. It can be seen clearly from above iteration2, that wafer3 and wafer4 considered LoadLock in Atmospheric state at time 80 and hence wafer3 and wafer4 had to pump LoadLock. But, since wafer5 and wafer6 have already pumped LoadLock, wafer3 and wafer4 can enter LoadLock without pumping. So, the cycle of wafer3 and wafer4 can be optimized. Hence, self-correction sub-module takes control and starts correcting wafer3 and wafer4.
Iteration 2 Self-Correction:
[0056] The cycle of wafer3 and wafer4 is started when Robot2 picks up both the wafers. Wafer3 moves to node 9 at time 75. Since, the next target node i.e. node 7 is in LoadLock, wafer3 checks if LoadLock is in Vacuum state at time 80. Since LoadLock is now pumped by wafer5 and wafer6, it is in Vacuum state at time 80. So, wafer3 reaches node 7 at time 80. Similarly, wafer4 reaches node 8 at time 80. Both the wafers vent LoadLock to Atmospheric state at time 90. Similarly, the cycle of both the wafers is completed at time 115, saving 10 units of time.
Resuming Iteration 3:
[0057] After self-correction is completed, wafer5 and wafer6 are processed. Wafer5 finds next target node as node 9. Its current time is 70 units. But, node 9 has entry 70-80, which means node 9 is available only after 80 units. So, wafer5 adds wait time of 10 to its current time and reaches node 9 at time 95 and then reaches node 11 at time 100. Similarly, wafer6 reaches node 12 at time 100. Both the wafers are processed in PM for 10 units until time 110.
Equipment Nodes Iteration 1
(Entry Time - Exit Time) Iteration 2
(Entry Time - Exit Time) Iteration 3
(Entry Time - Exit Time)
Robot 1 3, 4 0-10, 60-70, 75-85 10-30, 100-110(90-100), 115-125(105-115) 50-60, 145-155
LoadLock 5, 6 10-20 20-50 60-80
7, 8 50-60 80-100, (80-90) 110-130
Robot 2 9, 10 20-30, 40-50 50-60, 70-90, (70-80) 80-90, 100-120
PM1 11, 12 30-40 60-70 90-100
Cooler 15, 16 70-75 110-115(100-105) 140-145
Load Port 1 75 125(115) 155

Table 3: Entries in Nodes after Iteration 3
[0058] Strikethrough indicates the values before self-correction. The values in brackets indicate corrected values.
[0059] The embodiments disclosed herein can be implemented through at least one software program running on at least one hardware device and performing network management functions to control the network elements. The network elements shown in Fig. 2 include blocks which can be at least one of a hardware device, or a combination of hardware device and software module.
[0060] The embodiments disclosed herein specify a system and method for throughput determination of a tool. The mechanism allows determination of throughput of a tool, providing a system thereof. Therefore, it is understood that the scope of protection is extended to such a system and by extension, to a computer readable means having a message therein, said computer readable means containing a program code for implementation of one or more steps of the method, when the program runs on a server or mobile device or any suitable programmable device. The method is implemented in a preferred embodiment using the system together with a software program written in, for ex. Very high speed integrated circuit Hardware Description Language (VHDL), another programming language, or implemented by one or more VHDL or several software modules being executed on at least one hardware device. The hardware device can be any kind of device which can be programmed including, for ex. any kind of a computer like a server or a personal computer, or the like, or any combination thereof, for ex. one processor and two FPGAs. The device may also include means which could be for ex. hardware means like an ASIC or a combination of hardware and software means, an ASIC and an FPGA, or at least one microprocessor and at least one memory with software modules located therein. Thus, the means are at least one hardware means or at least one hardware-cum-software means. The method embodiments described herein could be implemented in pure hardware or partly in hardware and partly in software. Alternatively, the embodiment may be implemented on different hardware devices, for ex. using a plurality of CPUs.
[0061] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the claims as described herein.

CLAIMS
What is claimed is:
1. A method for measuring throughput of a semi-conductor manufacturing tool, said method comprising:
receiving a layout of said semi-conductor manufacturing tool as input, by an Input/Output (I/O) interface sub-module of a throughput determination module;
determining number of wafers to be processed by said semi-conductor manufacturing tool, automatically, by an optimization sub-module of said throughput determination module;
scheduling automatically, at least one slot for processing said input, by a path detection sub-module of said throughput determination module;
determining a time for said input to enter said at least one slot, based on a feedback value, by a time assessment sub-module of said throughput determination module; and
determining a process completion time, by said time assessment sub-module, wherein said process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by said layout.
2. The method as claimed in claim 1, wherein said number of wafers to be processed is determined based on number of processing modules in said tool, by said optimization sub-module.
3. The method as claimed in claim 1, wherein said slot is scheduled based on at least one of a transfer time, processing time, shortest path value, and waiting time, by said path detection sub-module.
4. The method as claimed in claim 1, wherein determining said time to enter said at least one slot further comprises of:
checking a nodeTime entered by a wafer that has been entered by at least one other wafer previously processed by said at least one slot, by said time assessment sub-module, wherein said nodeTime indicates time from which said at least one slot is available for processing;
identifying said time indicated by said nodeTime as the time to enter said at least one node, by said time assessment sub-module; and
adding a wait time to said identified time, if required, by said time assessment sub-module.
5. The method as claimed in claim 1, wherein said process completion time is determined based on at least one of a nodeTime corresponding to each slot, and a processing capability of at least one processing module in said semi-conductor manufacturing tool represented by said layout, by said time assessment sub-module.
6. A system for measuring throughput of a semi-conductor manufacturing tool, said system configured for:
receiving a layout of said semi-conductor manufacturing tool as input, by an Input/Output (I/O) interface sub-module of a throughput determination system;
determining number of wafers to be processed by said semi-conductor manufacturing tool, automatically, by an optimization sub-module of said throughput determination system;
scheduling automatically, at least one slot for processing said input, by a path detection sub-module of said throughput determination system;
determining a time for said input to enter said at least one slot, based on a feedback value, by a time assessment sub-module of said throughput determination system; and
determining a process completion time, by said time assessment sub-module, wherein said process completion time indicates time required for generating output by a semi-conductor manufacturing tool represented by said layout.
7. The system as claimed in claim 6, wherein said optimization sub-module is configured to determine said number of wafers to be processed, based on number of processing modules in said semi-conductor manufacturing tool, by said optimization sub-module.
8. The system as claimed in claim 6, wherein said path detection sub-module is configured to schedule said slot based on at least one of a transfer time, processing time, shortest path value, and waiting time.
9. The system as claimed in claim 6, wherein said time assessment sub-module is configured to determine said time to enter said at least one slot by:
checking a nodeTime entered by a wafer that has been entered by at least one other wafer previously processed by said at least one slot, wherein said nodeTime indicates time from which said at least one slot is available for processing;
identifying said time indicated by said nodeTime as the time to enter said at least one node; and
adding a wait time to said identified time, if required.
10. The system as claimed in claim 6, wherein said time assessment sub-module is configured to determine said process completion time based on at least one of a nodeTime corresponding to each slot, and a processing capability of at least one processing module, in said semi-conductor manufacturing tool represented by said layout.

Dated this 31st July 2015

Signature:
Name: Kalyan Chakravarthy
(Patent Agent)

ABSTRACT
A method and system for determining throughput of a manufacturing tool. The system determines number of inputs to be processed. The system further schedules slot in which each identified input needs to enter. The system also determines the time at which the input needs to enter a selected slot, based on a feedback mechanism. The system further checks if any corrections are required in terms of the order in which the inputs are processed in the system, and if any correction is required, the system accordingly adjusts time by adding a correction value. Further, throughput of the manufacturing tool represented by the layout is determined by the system.
FIG. 1