THE PATENTS ACT, 1970
(39 of 1970)
As amended by the Patents (Amendment) Act, 2005
&
The Patents Rules, 2003
As amended by the Patents (Amendment) Rules, 2006
COMPLETE SPECIFICATION
(See section 10 and rule 13)
TITLE OF THE INVENTION
A method, system and computer readable medium for detecting winding faults
APPLICANTS
Crompton Greaves Limited, CG House, Dr Annie Besant Road, Worli, Mumbai 400 030, Maharashtra, India, an Indian Company
INVENTORS
Velandy Jeyabalan and Sundaresan Sathish, of Crompton Greaves Ltd, High voltage product technology centre, Global R&D, Kanjur Marg, Mumabi 400 042, Indian Nationals.
PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed.

FIELD OF THE INVENTION
This invention relates to a method, system and computer readable medium for detecting winding faults in transformers. Particularly, this invention relates to interpretation techniques for detection of winding deformation and faults in power transformers, reactors and instrument transformers.
BACKGROUND OF THE INVENTION
Power transformer is one of the most important equipment, playing a major role in deciding the reliability of a power system. The basic function of winding insulation of the transformer is to withstand the electrical stress without any major damage during the expected life time in service.
Sweep frequency response analysis (SFRA) test is a known technique and a very sensitive technique for detecting winding movement faults caused by loss of clamping pressure or by short circuit forces in transformers. SFRA principle can be adopted to the following general cases by theoretically and experimentally.
With increasing the utilization of fast digitizer technologies for signal acquisition (IEC 61083-1991) of transformer to make a decision about either acceptance or go/no-go criteria after impulse test, it would be instructive to provide the identification of minor fault (inter turn / disc, between layers or partial discharge) in transformer, reactor. Though IEC and ANSI standards provide guideline for failure identification based on visual examination or transfer function of

voltages and current waveforms between reduced and rated impulse test voltages or between successive measurements at rated test voltage, identification of minor fault is a non-trivial task and to some extent remains subjective. The visual examination in the shape of the voltages and current waveform due to winding fault does not provide any conclusive evidence for the test engineer to declare about the transformer and it often becomes controversial.
Though, a few researches have been performed on wavelet transforms, transfer function methods, it can be noted that only limited success is achieved. Hence, reliable method for detection of winding fault is critical need for industry to improve personal safety and decrease the potential loss during service as well as fundamental requirement for condition based maintenance before dispatch.
The aforesaid methods are graphical in nature and therefore require trained experts to interpret the test results. Further, it is difficult to detect the severity of fault quantitatively and it does not give conclusive evidence for detection.
Considering the above there is need to develop a method, system and computer readable medium for detecting winding faults in transformers.
OBJECT OF THE INVENTION
An objective of the invention is to provide a method for detecting winding faults in transformers.

Another objective of the invention is to provide a system for detecting winding faults in transformers.
Yet, another objective of the invention is to provide a computer readable medium for detecting winding faults in transformers.
SUMMARY OF THE INVENTION
According to one aspect of the invention, there is provided a computer implemented method executed by one or more computing devices for detecting a winding fault in a transformer, said method comprising the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response , then said transformer withstands said second full impulse voltage;

g) measuring a third fault response by applying a third full impulse voltage to said
transformer; h) . if said reference response is equal to said third fault response, then said
transformer withstands said third full impulse voltage; i) if said reference response is not equal to said first fault response or said second
fault response or said third fault response, then said transformer does not
withstand said respective impulse voltages.
According to another aspect of the invention, there is provided a system for detecting a winding fault in a transformer, the system comprising: a memory; and a processor operatively coupled to the memory, the processor configured to perform the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response , then said transformer withstands said second full impulse voltage;

g) measuring a third fault response by applying a third full impulse voltage to said
transformer; h) if said reference response is equal to said third fault response, then said
transformer withstands said third full impulse voltage; i) if said reference response is not equal to said first fault response or said second
fault response or said third fault response, then said transformer does not
withstand said respective impulse voltages.
According to another aspect of the invention, there is provided a computer-readable code stored on a non-transitory computer-readable medium that, when executed by a computing device, performs a method for detecting a winding fault in a transformer, said method comprising the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response , then said transformer withstands said second full impulse voltage;

g) measuring a third fault response by applying a third full impulse voltage to said
transformer; h) if said reference response is equal to said third fault response, then said
transformer withstands said third full impulse voltage; i) if said reference response is not equal to said first fault response or said second
fault response or said third fault response, then said transformer does not
withstand said respective impulse voltages.
DETAILED DESCRIPTION OF THE INVENTION
The present invention relates to interpreting the reference responses and fault responses for detection of winding deformation and faults in transformers using statistical techniques methods.
According to the present invention, an impulse voltage which is less than the standard voltage (i.e. reduced impulse voltage) is applied to the transformer and a shunt response is measured to get a reference response for fault detection. Further, a first full impulse voltage is applied and the shunt response is measured and it is considered as a first fault response. The reference response and fault response are compared numerically using the statistical techniques. If the reference response is equal to the first fault response then the transformer withstands the first full impulse voltage. If the reference response is not equal to the first fault response, then the transformer does not withstand the first full impulse voltage and then a fault and severity of the transformer is detected.

Once the transformer withstands the first full impulse voltage, then a second full impulse voltage is applied and the shunt response is measured and it is considered as a second fault response. If the reference response is equal to the second fault response, then the transformer withstands the second full impulse voltage. If the reference response is not equal to the second fault response, then the transformer does not withstand the second full impulse voltage and then a fault and severity of the transformer is detected.
Once the transformer withstands the second full impulse voltage, then a third full impulse voltage is applied and the shunt response is measured and it is considered as a third fault response. If the reference response is equal to the third fault response, then the transformer withstands the third full impulse voltage. If the reference response is not equal to the third fault response, then the transformer does not withstand the third full impulse voltage and then a fault and severity of the transformer is detected.
Further, if the transformer is failed at reduced impulse voltage then it is considered as the fault response. The reference response is obtained by using Hybrid transformer model through transformer design parameters (winding capacitance, resistance, inductance and shunt capacitance).
The system comprises a processing unit and memory. The processing unit executes computer-executable instructions. The memory can be a volatile memory (e.g., registers, cache, RAM), a non-volatile memory (e.g., ROM, EEPROM, flash memory, etc.), or some combination of the two. The system further has additional features such as storage, one or more input devices, one or more output devices, and one or more communication connections. An interconnection

mechanism such as a bus, controller, or network interconnects the components of the system. The storage can be removable or non-removable, and includes magnetic disks, magnetic tapes or cassettes, CD-ROMs, CD-RWs, DVDs, or any other medium which can be used to store information and which can be accessed within the system.
The input device(s) are such as a keyboard, mouse, pen, trackball, touch screen, or game controller, a voice input device, a scanning device, a digital camera, or another device that provides input to the system. The output device(s) are such as a display, printer, speaker, or another device that provides output from the system. Computer-readable media are any available media that can be accessed within the system.
With practical data from analog-to-digital converters, some form of Fast fourier transform (FFT) routines with sophisticated digital filtering methods are required to extract the exact frequency components of fault signal alone before using any Statistical techniques. Hence, multivariate denoising procedure with Butterworth bandpass digital filter is used for measured reference signal and fault signals. The multivariate denoising procedure consists of wavelets and Principal component analysis (PCA).
Statistical techniques (linear regression line & polynomial regression. Dot invention rule, standard deviations, absolute sum of log error, Dispersion, spectral deviations, standard deviation of the mean), confidence evaluation methods (T distribution & t test, F distribution & F test, Chi test, Probability value, line of intersection with correlation coefficients and tangential angle, residual variance), interpretation methods (Variate transformation, standard error and probable error) can be used in the present invention.

The present invention numerically detects the severity of fault, ageing and life time estimation, which is an advantage over the prior arts.
Although the invention has been described with reference to a specific embodiment, this description is not meant to be construed in a limiting sense. Various modifications of the disclosed embodiment, as well as alternate embodiments of the invention, will become apparent to persons skilled in the art upon reference to the description of the invention. It is therefore contemplated that such modifications can be made without departing from the spirit or scope of the invention as defined.

WE CLAIM
1. A computer implemented method executed by one or more computing devices for detecting a winding fault in a transformer, said method comprising the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response , then said transformer withstands said second full impulse voltage;
g) measuring a third fault response by applying a third full impulse voltage to said transformer;
h) if said reference response is equal to said third fault response, then said
transformer withstands said third full impulse voltage; i) if said reference response is not equal to said first fault response or said second
fault response or said third fault response, then said transformer does not
withstand said respective impulse voltages.

2) A system for detecting a winding fault in a transformer, the system comprising; a memory; and a processor operatively coupled to the memory, the processor configured to perform the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response, then said transformer withstands said second full impulse voltage;
g) measuring a third fault response by applying a third full impulse voltage to said transformer;
h) if said reference response is equal to said third fault response, then said
transformer withstands said third full impulse voltage; i) if said reference response is not equal to said first fault response or said
second fault response or said third fault response, then said transformer does
not withstand said respective impulse voltages.

3) Computer-readable code stored on a non-transitory computer-readable medium that, when executed by a computing device, performs a method for detecting a winding fault in a transformer, said method comprising the steps of:
a) measuring a reference response by applying an impulse voltage less than a standard voltage to said transformer;
b) measuring a first fault response by applying a first full impulse voltage to said transformer;
c) filtering said reference response and said first fault response by using a butterworth bandpass digital filter and a multivariate denoising procedure;
d) if said reference response is equal to said first fault response, then said transformer withstands said first full impulse voltage;
e) measuring a second fault response by applying a second full impulse voltage to said transformer;
f) if said reference response is equal to said second fault response, then said transformer withstands said second full impulse voltage;
g) measuring a third fault response by applying a third full impulse voltage to said transformer;
h) if said reference response is equal to said third fault response, then said transformer withstands said third full impulse voltage;

i) if said reference response is not equal to said first fault response or said second fault response or said third fault response, then said transformer does not withstand said respective impulse voltages.