DESC:TECHNICAL FIELD
[0001] The present invention relates to the field of semiconductor device technology and microelectronics. Specifically, it is related to high electron mobility transistors (HEMTs) based on p-type gallium nitride (p-GaN) material. HEMTs are a type of field-effect transistor (FET) that are widely used in high-frequency and high-power applications due to their excellent electronic properties.

BACKGROUND
[0002] To achieve fail-safe normally-off operation and simplified gate driver circuitry, p-GaN gate AlGaN/GaN HEMTs are preferred due to their potential for industrialization. However, these HEMTs face challenges related to gate leakage current and gate breakdown characteristics. The p-GaN cap layer forming a Schottky junction with the gate metal leads to strong electric fields in the depletion region, degrading gate breakdown characteristics. Moreover, practical applications often require a high gate voltage swing of around 8V, but the current safe gate operating voltage is limited to 4-7V, which is insufficient for meeting switching requirements.
[0003] Additionally, the low hole concentration in p-GaN, caused by the low activation rate of the Mg dopants, results in a low threshold voltage (0 to 2V) for p-GaN gate HEMTs. This can result in a false turn-on of the device in practical applications. Therefore, increasing the threshold voltage and extending the gate drive voltage range becomes crucial. Various methods have been proposed to improve the threshold voltage, such as changing the Schottky gate metal, using double heterostructures, or using p-FET bridge, p-GaN Gate HEMTs with Oxidation Interlayer, or MIS gates. However, these approaches often involve tradeoffs, like higher gate leakage, VTH instability, weaker gate control, and SS degradation, despite achieving an improvement in threshold voltage.
[0004] Additionally, for improved gate stability, an Ohmic gate metal/p-GaN contact was reported, which resulted in a relatively stable VTH; however, it caused an increased forward gate leakage and reduced gate voltage swing. A Schottky contact on the p-GaN gate minimizes this forward gate leakage by preventing hole injection through the reverse-biased metal/p-GaN Schottky junction, however, it results in a floating p-GaN region during device operation, leading to charge accumulation induced VTH shift and instability. Additionally, higher electric fields in the depletion region under forward gate overdrive lead to defect generation and avalanche action near the Schottky contact. This limits the gate overdrive and reduces the device's lifetime. Gate leakage and p-GaN depletion electric field can be controlled by inserting a gate dielectric between metal and p-GaN. However, it results in weaker gate control and deteriorates on-state performance.
[0005] Therefore, there is a need to overcome the above recited drawbacks and limitations of the existing HEMTs. Aluminium titanium Oxide (AlTiO)/p-GaN integration AlTiO/p-GaN gate stack architecture to improve the VT H of the e-mode HEMT while simultaneously improving gate leakage, on-state current, VTH stability, gate control, and gate breakdown performance

OBJECTS OF INVENTION
[0006] Some of the objects of the present disclosure, that at least one embodiment herein satisfy are as listed herein below.
[0007] It is an object of the present disclosure to overcome the drawbacks and limitations of the existing systems for the method for High Threshold Voltage and High Breakdown Gate Stack in p-GaN Gate e-mode HEMTs.
[0008] It is an object of the present disclosure to raise the threshold voltage of the p-GaN gate e-mode HEMTs as a higher threshold voltage is desirable in certain applications to control the turn-on behavior of the transistor and prevent unintentional conduction.
[0009] It is an object of the present disclosure to increase the breakdown voltage of the gate stack in the p-GaN HEMTs as a higher breakdown voltage indicates that the transistor can handle higher voltage levels without suffering from electrical breakdown, making it more suitable for high-power and high-voltage applications.
[0010] It is an object of the present disclosure to enhance overall reliability and robustness of the p-GaN gate e-mode HEMTs by optimizing the gate stack design, to increase resistance to electrical stress, thermal effects, and environmental factors that degrades performance.
[0011] It is an object of the present disclosure to minimize leakage current, especially when the transistor is in the off-state, which is crucial for power efficiency and preventing unnecessary energy consumption.
[0012] It is an object of the present disclosure to develop a gate stack fabrication method that is compatible with existing semiconductor fabrication processes which would facilitate the integration of the improved gate stack into existing manufacturing workflows.
[0013] It is an object of the present disclosure to achieve improvements in a cost-effective manner involving optimizing material usage, processing steps, and equipment requirements.
[0014] It is an object of the present disclosure to contribute to the advancement of semiconductor device technology and transistor performance which involves novel materials, design concepts, or fabrication techniques that lead to breakthroughs in the field.

SUMMARY
[0015] To tackle these performance issues, the present invention discloses a method for high threshold voltage and high breakdown gate stack in p-GaN gate e-mode HEMTs and demonstrated AlTiO/ p-GaN integrated gate stack. This innovation enhances VTH while maintaining excellent gate control. The gate stack also reduces gate leakage and improves gate overdrive, resulting in an increased maximum current driving capability.
[0016] In an aspect, the system aims to enhance the performance and reliability of p-GaN gate enhancement-mode high electron mobility transistors (HEMTs). The method focuses on achieving higher threshold voltage (VTH) and improved breakdown voltage (VBR) characteristics in these transistors. The method aims to increase the threshold voltage of the p-GaN gate e-mode HEMTs. This higher threshold voltage helps control the transistor's turn-on behavior and prevents unintended conduction. The method also seeks to enhance the breakdown voltage of the gate stack in the transistors. A higher breakdown voltage ensures that the transistor can be operated at higher gate overdrives, thereby enabling the HEMT to carry large ON-currents.
[0017] In as aspect, a methodology to enhance to improve threshold voltage of the devices by properly tuning gate leakage. Various gate leakage paths have been shown to affect the turnON process of the devices. The devices turnON process mode decides its Vth enhancing capability. 2 different modes have been namely fully depleted mode and partially depleted mode depending on whether the p-GaN doping is low and high, respectively. In the partially depleted mode, it has been revealed that the devices work either in the depletion extension mode or hole accumulation mode, depending on the balance between various leakage paths. It is revealed that devices working in the depletion extension mode have Vth enhancing capability. It may be appreciated by a person skilled in the art that the depletion extension mode is a process mode in which the device turn-on process is governed by p-GaN layer depletion, once the depletion extends to AlGaN barrier layer, device turn-ON process starts, whereas the hole accumulation mode is a process mode in which the device turn-on process is governed by the hole accumulation at the p-GaN/AlGaN interface and p-GaN depletion do not change.
[0018] In an aspect, with leakage balance as a goal, AlTiO/p-GaN integration has been been employed to enhance Vth and gate breakdown of the devices. Nature of AlTiO particularly w.r.t. to its leakage, dielctric constant, doping, crystalline quality, are some of the factors which through proper tuning enhance Vth.
[0019] In an aspect, the methodology is not limited to AlTiO/p-GaN only, any dielctric with the specified properties which can provide an appropriate balance of leakages and enable the gate stack to operate in the depletion extension mode, is capable of of enhancing Vth.
[0020] In an aspect, the improved device robustness is a oal. By refining the gate stack design, the transistors become more resistant to electrical stress, thermal effects, and environmental factors that can degrade their long-term performance. The method targets minimizing leakage currents when the transistor is in the off-state. This reduction is essential for power efficiency and preventing unnecessary energy consumption. The ultimate objective is to enable the utilization of p-GaN gate e-mode HEMTs in high-performance applications such as power electronics, high-frequency amplifiers, and RF devices. Enhanced threshold and breakdown voltage characteristics expand their applicability. The method aims to develop a gate stack fabrication approach that integrates seamlessly with existing semiconductor manufacturing processes. This ensures smooth incorporation of the improved gate stack into current production methods.
[0021] In an aspect, the system aims at achieving improvements in a cost-effective manner is a consideration. The method optimizes material usage, processing steps, and equipment requirements to minimize production costs and achieving desired performance enhancements. The method also contributes to the progress of semiconductor device technology by exploring novel materials, design concepts, or fabrication techniques that could lead to significant advancements in transistor performance. In essence, the system aims to elevate the electrical characteristics and overall performance of p-GaN gate e-mode HEMTs, enhancing their suitability for specific high-power, high-voltage, and high-frequency applications.
[0022] Various objects, features, aspects, and advantages of the inventive subject matter will become apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[0023] The specifications of the present disclosure are accompanied with drawings of the system and method to aid in better understanding of the said invention. The drawings are in no way limitations of the present disclosure, rather are meant to illustrate the ideal embodiments of the said disclosure.
[0024] In the figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label with a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
[0025] FIG. 1A and FIG. 1C illustrate a schematic diagram of the device cross-section based on AlTiO/p-GaN integration, in accordance with an embodiment of the present disclosure.
[0026] FIG. 1B illustrate a flow chart illustrating the fabrication process steps enabling AlTiO/p-GaN integration, in accordance with an embodiment of the present disclosure.
[0027] FIGs. 2A-2C illustrate a graphical representation of the transfer characteristics of conventional Schottky metal/p-GaN (75nm) gated HEMT (sample P) and Schottky metal/p- AlXTi1-xO (10nm)/p-GaN (75nm) HEMT (sample PA) in (a) linear, and (b) semi-log scale in accordance with an embodiment of the present disclosure.
[0028] FIG. 2C illustrates statistical distribution of VTH and transconductance (gm) showing gate control to improve with p-GaN/AlTiO integration in addition to a positive VTH.
[0029] FIGs. 3A-3D illustrate the thermal equilibrium energy band diagram for the p-GaN/AlGaN/GaN stack with varying p-GaN thicknesses and its implications on devices characteristics, in accordance with an embodiment of the present disclosure.
[0030] FIG. 4A illustrates the distribution of gate leakage and maximum allowable gate overdrive for samples P, PE, PA, and PAE, in accordance with an embodiment of the present disclosure.
[0031] FIG. 4B illustrates dynamic instability in VTH in accordance with an embodiment of the present disclosure.
[0032] FIG. 5 illustrates a Comparison of device characteristics for devices with thermal activation. Conductivity measurements using special test structures (inset) with 10 µm spaced metal/p-GaN junctions confirmed improved Mg activation in annealed samples. This results in higher conductivity and significantly increased gate leakage with comparable VTH. The figure also compares devices with varying p-GaN thickness, showing comparable VTH and ON-state leakages. Increased gate leakage is attributed to the thinner metal/p-GaN barrier, causing higher tunneling current from the gate.
[0033] FIG. 6 illustrates P-GaN equilibrium depletion width as a function of p-GaN doping and metal work function. For a given p-GaN thickness and metal work function,p-GaN may be either fully depleted or partially depleted. (b) p-GaN depletion scenarios: fully depleted for low doping and partially depleted for high doping. (c) Schematic band diagram of metal/p-GaN gate stack showing potential variations and charge flow due to leakage routes, with hole supply from the gate and p-GaN depletion towards the p-GaN/AlGaN interface, where holes may accumulate or leak through the barrier via trap-assisted recombination. The schematic forms the base for model developed given above.
[0034] FIG. 7(a) illustrates STEM image of the device cross-section, and FIG. 7(b) illustrates a schematic of leakage routes in the p-GaN gate stack, including through the gate/pGaN, p-GaN sidewall, and AlGaN barrier, in accordance with an embodiment of the present disclosure.
[0035] FIGs. 8(a)-8(b) illustrates an impact of AlGaN barrier leakage on device characteristics using a well-calibrated computational framework, in accordance with an embodiment of the present disclosure.
[0036] FIG. 9(a) illustrates temporal change in AlGaN surface potential with incoming hole supply, showing accelerated accumulation at the p-GaN/AlGaN interface and subsequent 2DEG formation, and FIG. 9(b) illustrates a contrast with a leaky barrier, exhibiting no hole buildup or surface potential variation, preventing 2DEG formation, in accordance with an embodiment of the present disclosure.
[0037] FIG. 10 illustrates (a) Comparison of AlGaN surface potential and 2DEG formation across gate voltage in fully and partially depleted modes, highlighting predictive accuracy of the model. Band diagrams along the gate stack demonstrate (b) direct control over the AlGaN surface potential in the fully depleted case. (c) a parallel shift of the bands due to hole accumulation, resulting in ?Vg ~ ?Vfi, which maintains a consistent depletion. (d) In the h-depletion mode, the depletion extends due to minimal changes in ?Vfi, in accordance with an embodiment of the present disclosure.
[0038] FIGs. 11(a)-11(b) illustrates device's turn-on process varies with incoming hole supply, showing that suppressed hole injection can enhance VTH without sacrificing subthreshold performance. However, higher p-GaN doping may limit VTH potential due to increased hole injection from the gate, indicating that inserting a gate dielectric could optimize VTH, in accordance with an embodiment of the present disclosure.
[0039] FIG. 12 illustrates (a) Transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN activated doping. (b) Equilibrium band diagrams showing s higher doping shrinks the p-GaN depletion width, therefore a complete p-GaN depletion is delayed to turn on the device giving high Vth, in accordance with an embodiment of the present disclosure.
[0040] FIG. 13 illustrates (a) Transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN thickness. (b) Equilibrium band diagrams showing higher ease of thinner p-GaN for complete depletion to turn on the device, therefore giving lower Vth for thinner p-GaN devices, in accordance with an embodiment of the present disclosure.
[0041] FIG. 14 illustrates (a) AlTiO/p-GaN integrated gate stack with varying crystalline quality. (b) Process A shows moderate disorder. (c) Process B has grain boundaries and higher disorder. (d) Process C exhibits more uniform quality. (e) AlTiO composition with VBE and bandgap values from UPS and UV-Vis spectroscopy for calibrated computations. (f) Process A devices show a moderate VTH shift, while Process B devices show a significantly higher VTH with similar ON/OFF ratios despite being integrated on thinner p-GaN. (g) Process C devices have a lower VTH due to increased gate leakage, indicating hole accumulation mode, in contrast to Process B, which operates in hole depletion mode with suppressed leakage. (h) Comparison of gate leakage and VTH shows Process B devices with maximum VTH and suppressed leakage., in accordance with an embodiment of the present disclosure.
[0042] FIG. 15 illustrates (a) Transfer characteristics of the devices with non-leaky and leaky dielctric. It can be observed that the devices with a leaky dielctric show a low Vth, whereas devices with non-leaky dielctric show a higher Vth. (b) devices turns on through hole accumulation mode in a leaky dielctric case (c) devices turns on in the hole depletion mode in a non-leaky dielctric case, in accordance with an embodiment of the present disclosure.
[0043] FIG. 16 illustrates (a) Gate capacitance measurements reveal a difference in VTH between devices from processes A and B, despite similar ON-state capacitance. The thicker p-GaN in process A suggests lower capacitance, indicating a possible alteration in the AlTiO dielectric constant due to varying crystalline quality—more disorder results in a lower dielectric constant (K) and delayed depletion (c). (b) Device characteristics show consistent VTH aligned with model extracted K-values, in accordance with an embodiment of the present disclosure.
[0044] FIG. 17 illustrates (a) shows Vth dependence on the energy bandgap of the gate dielctric showing higher Vth for wider bandgap dielctric (b) Initial band diagram showing the increase is Vth can be attributed to the delayed p-GaN depletion effect, in accordance with an embodiment of the present disclosure.
[0045] FIG. 18 illustrates (a) Vth dependence on the electron affinity of the gate dielctric showing higher Vth for dielectric with high electron affinity (b) Initial band diagram showing the increase is Vth can be attributed to the delayed p-GaN depletion effect, in accordance with an embodiment of the present disclosure.
[0046] FIG. 19 illustrates Vth relationship of proposed high Vth devices as a function of Vth of ohmic device. Equation shows an inverse relationship between gate dielctric capacitance and device’s Vth, in accordance with an embodiment of the present disclosure.
[0047] FIG. 20 illustrates (a) Dynamic instability in VTH due to 6V DC stress shows that AlTiO/pGaN samples (A, B) have lower ?VTH than those without AlTiO (b) Comparison of VG, Max versus VTH in this work with the state-of-the-art p-GaN gated HEMTs showing superior gate performance of demonstrated devices, in accordance with an embodiment of the present disclosure.
[0048] FIG. 21 illustrates exemplary variation of the semiconductor devices that may be without the passivation layer or may comprise any one or a combination of a passivation layer, a source or gate connected field plate , a spacer and a drain field plate, in accordance with an embodiment of the present disclosure.
[0049] FIG. 22 illustrates exemplary variation of the semiconductor devices that may be without the cap layer or may comprise cap layer may be introduced either fully extended to the source and drain or only on the gate side and partially or fully extended towards gate, in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0050] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0051] In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without some of these specific details.
[0052] If the specification states a component or feature “may”,”can”,”could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have that characteristic.
[0053] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[0054] The present invention relates to the field of semiconductor device technology and microelectronics. Specifically, it is related to high electron mobility transistors (HEMTs) based on p-type gallium nitride (p-GaN) material. HEMTs are a type of field-effect transistor (FET) that are widely used in high-frequency and high-power applications due to their excellent electronic properties.
[0055] In an embodiment of the present disclosure, a methodology to enhance threshold voltage through careful careful balance of leakage through different patheway. Depending on the leakage balance, the device may work either either in hole accumulation mode or hole depletion mode. Devices working in hole depletion mode have VTH enhancing capability. The present invention demonstrates. high-electron mobility transistor (HEMT) device is included which proposes and demonstrates that the devices work Devices comprises a AlTiO and p-GaN gate stack to push a VTH to higher values, reduce gate leakage, and improve gate overdrive and stability. The VTH enhancement capability was also shown to be tuned by adjusting the crystalline quality, leakage, and dielectric constant, nature and concentration of doping of AlTiO(114). The methodology is not limited to AlTiO/p-GaN integration only, any dielctric with the specified properties which can provide an appropriate balance of leakages and enable the gate stack to operate in the depletion extension mode, is capable of of enhancing Vth.
[0056] FIGs. 1A and 1C illustrate a schematic diagram 100 of the device cross-section based on AlTiO/p-GaN integration, in accordance with an embodiment of the present disclosure.
[0057] Referring to FIG. 1A, a schematic diagram of the device cross-section based on p-AlTiO /p-GaN integration is disclosed. It also indicates a flow chart illustrating the fabrication process steps enabling AlTiO/p-GaN integration. The integration of dielectric materials like p-AlTiO (p-type aluminium titanium oxide) with p-GaN is employed to improve the gate stack performance in semiconductor devices, such as transistors. The bottom layer can be a substrate made of materials like Silicon (Si), Silicon Carbide (SiC) or sapphire, depending on specific applications. Above the substrate, there may be a buffer layer to accommodate the lattice mismatch between the substrate and subsequent layers for improved quality of the epitaxial layers. On top of the buffer layer, there is a UID channel , barrier layer and a layer of p-type gallium nitride (p-GaN). The UID GaN channel region is the active region of the transistor where the current flows. For normally-Off operation, p-GaN is grown on AlGaN/GaN epistack. Above the p-GaN layer, there's a layer of dielectric material, which in this case is p-type AlTiO (p-AlTiO). materials have a higher dielectric constant compared to traditional materials like silicon dioxide (SiO2). This layer serves as the gate dielectric and controls the flow of current through the transistor. Finally, on top of the dielectric layer, the gate electrode is used to apply a voltage to the gate dielectric, creating an electric field controlling the flow of current between source and drain regions in the p-GaN layer and the top gate metal can be Ti/TiN.
[0058] In an embodiment, High Electron Mobility Transistors (HEMTs) are a type of field-effect transistor (FET) that offer exceptional electron mobility, making them suitable for high-frequency and high-speed electronic applications. HEMTs are designed to take advantage of materials with high electron mobility, such as compound semiconductors like gallium nitride (GaN) and indium phosphide (InP). The high mobility of electrons allows for faster charge carrier movement and higher electron velocities, resulting in excellent high-frequency performance. HEMTs typically have a heterostructure design, which means they consist of layers of different semiconductor materials with varying energy bandgaps. This design enhances carrier confinement, improves current saturation, and reduces power dissipation. The unique feature of HEMTs is the presence of a two-dimensional electron gas (2DEG) layer at the interface between two semiconductor materials. This 2DEG forms due to the modulation doping technique, where donor impurities are placed in one layer to create a concentration gradient that channels electrons to the 2DEG layer. This layer allows for efficient electron transport and high carrier concentrations.
[0059] In an embodiment, AlTiO /p-GaN refers to a heterostructure or a combination of layers composed of aluminium titanium oxide (AlTiO) and p-type gallium nitride (p-GaN) materials. In high-electron mobility transistors (HEMTs), the gate dielectric is a crucial component that separates the gate electrode from the semiconductor channel (p-GaN). Using AlTiO as the gate dielectric on p-GaN can offer advantages like a tunable dielectric properties and tailored electrical properties, which influence the transistor's performance, threshold voltage, and other characteristics. AlTiO could also serve as a passivation layer on top of p-GaN. Passivation layers protect the semiconductor material from surface states, contaminants, and other factors that can degrade device performance over time. The combination of AlTiO and p-GaN might also be used in power switching applications, optoelectronic devices like light-emitting diodes (LEDs) or photodetectors. In such cases, the specific arrangement and properties of the layers would be tailored to the desired light-emitting or light-sensing functionality. The combination can have applications in other electronic or semiconductor devices, depending on the desired characteristics and functionality of the heterostructure.
[0060] In an embodiment, the present invention relates to a semiconductor device (100). The semiconductor device (100) includes a substrate (102), a gallium nitride (GaN) buffer layer (104) formed on the substrate, a unintentionally doped (UID) GaN channel layer (106) positioned on the GaN buffer layer (104), an aluminium nitride (AlN) barrier layer (108) formed on the UID GaN channel layer (106), an aluminium gallium nitride (AlGaN) barrier layer (110) positioned on the AlN barrier layer (108), a p-type gallium nitride (p-GaN) layer (112) positioned on the AlGaN barrier layer (110), an aluminium titanium oxide (AlTiO) gate dielectric layer (114) positioned on the p-GaN layer (112), and a titanium Ti/ titanium nitride (TiN) gate metal layer (116) positioned on the AlTiO gate dielectric layer (114).
[0061] The AlGaN barrier layer enables a formation of a two-dimensional electron gas (2DEG) at an interface between the UID GaN channel layer and the AlGaN barrier layer.
[0062] In an exemplary embodiment, the AlTiO gate dielectric layer comprises a thickness between 8-12 nm, the AlN barrier layer comprises a thickness between 0.5 - 3 nm, the AlGaN barrier layer comprises a thickness between 9-14 nm, and the GaN buffer layer comprises a thickness between 3-6 µm.
[0063] In an exemplary embodiment, the p-GaN layer is a p-type doped and is positioned between the AlGaN barrier layer and the AlTiO gate dielectric layer.
[0064] In an embodiment, the present invention relates to semiconductor device (100) that includes a gate dielectric layer (114) positioned directly below a gate metal layer (116), and a gallium nitride (GaN) layer (112) positioned below the gate dielectric layer (114) and above a barrier layer (110).
[0065] The AlTiO gate dielectric layer has a thickness of approximately 10 nm and serves as a dielectric material, providing enhanced gate capacitance and reduced gate leakage.
[0066] The Ti/TiN gate metal layer has a low work function, enabling the device to achieve a lower threshold voltage and supporting normally-off operation by effectively modulating the 2DEG.
[0067] The p-GaN layer is p-type doped and is positioned between the AlGaN barrier layer and the AlTiO gate dielectric layer, serving as a gate barrier that depletes the 2DEG in the absence of an applied gate voltage, thereby enabling normally-off operation.
[0068] The AlN barrier layer has a thickness of approximately 1 nm, and the AlGaN barrier layer has a thickness of approximately 12 nm, collectively enhancing the polarization-induced electric field to increase electron mobility in the 2DEG formed at the interface between the UID GaN channel layer and the AlGaN barrier layer.
[0069] The substrate comprises silicon, and the GaN buffer layer has a thickness of approximately 5 µm, enabling the integration of the GaN-based device on a silicon substrate for cost-effective manufacturing.
[0070] The Ti/TiN gate metal layer, AlTiO gate dielectric layer, and p-GaN layer are configured to facilitate high-efficiency power switching by providing low on-resistance, reduced gate leakage, and rapid switching speeds.
[0071] The combination of the Ti/TiN gate metal layer, AlTiO gate dielectric layer, and p-GaN layer enhances the breakdown voltage characteristics of the device by optimizing the electric field distribution across the gate region.
[0072] The materials used in the Ti/TiN gate metal layer, AlTiO gate dielectric layer, and p-GaN layer are selected for their thermal stability, allowing the device to operate reliably in high-temperature environments.
[0073] The AlTiO gate dielectric layer and the p-GaN layer are configured to provide precise modulation of the 2DEG formed at the interface between the UID GaN channel layer and the AlGaN barrier layer, enabling fine-tuned control over the device's conduction properties.
[0074] In an exemplary embodiment, the the gate dielectric layer is an aluminium titanium oxide (AlTiO) layer, the GaN layer is a p-type gallium nitride (p-GaN) layer, and the barrier layer is an aluminium gallium nitride (AlGaN) layer.
[0075] The semiconductor device comprises a gate dielectric layer made of aluminum titanium oxide (AlTiO), positioned directly below the gate metal. This dielectric material reduces gate leakage and enhances gate control by providing a high dielectric constant, which increases the gate capacitance and ensures efficient modulation of the 2DEG channel.
[0076] The semiconductor device utilizes a Ti/TiN gate metal, which has a low work function, placed above the AlTiO gate dielectric. This configuration helps in achieving a lower threshold voltage, enabling normally-off operation of the device while maintaining high electron mobility in the 2DEG.
[0077] The semiconductor device features a p-type gallium nitride (p-GaN) layer positioned below the AlTiO gate dielectric and above the AlGaN barrier. The p-GaN layer serves as a gate barrier, enabling normally-off operation by depleting the 2DEG in the absence of gate voltage and allowing for its restoration upon application of a positive gate voltage.
[0078] The semiconductor device incorporates a p-GaN layer in conjunction with an AlTiO dielectric layer, facilitating enhanced control over the 2D electron gas (2DEG) formed at the interface between the GaN channel and the AlGaN barrier. This configuration allows precise modulation of the 2DEG density, leading to improved device performance in high-power and high-frequency applications.
[0079] The semiconductor device, featuring a Ti/TiN gate metal over an AlTiO dielectric and a p-GaN layer above the AlGaN barrier, demonstrates improved breakdown voltage characteristics. This configuration, with the combination of low work function gate metal and dielectric, enhances the electric field distribution and increases the device’s ability to withstand higher voltages without breakdown.
[0080] The semiconductor device is designed for high-efficiency power switching applications, where the Ti/TiN gate metal, AlTiO gate dielectric, and p-GaN layer collectively contribute to reduced gate leakage, lower on-resistance, and faster switching speeds. The configuration ensures minimal power loss and high efficiency in power electronics circuits.
[0081] The semiconductor device exhibits enhanced thermal stability due to the integration of AlTiO as the gate dielectric, Ti/TiN as the gate metal, and p-GaN as the gate barrier. These materials collectively provide high-temperature performance, making the device suitable for harsh operating environments.
[0082] The semiconductor device structure, utilizing a Ti/TiN gate metal, AlTiO dielectric, and p-GaN layer, is compatible with existing silicon manufacturing processes. This allows for cost-effective fabrication of high-performance GaN devices on silicon substrates, making it suitable for large-scale production.
[0083] Referring to FIG. 1B, the flowchart related to an Atomic Layer Deposition (ALD) of AlTiO referring to a thin film deposition technique is disclosed. It is used in the initial steps to create a film composed of aluminium and titanium oxides in a specific ratio. The first step is the atomic layer etching of pGaN (where tp = 60-80 nm) and p-GaN annealing at approximately 800 degrees Celsius for 10 minutes to reduce etching demage and improve p-GaN activation. According to the defect chemistry, aluminium oxide introduction in titanium oxide creates positively charged oxygen vacancies and negatively charged Al fixed charges occupying Ti sites. The positively charged oxygen vacancies result in neutral oxygen vacancies and introduce holes in the Al-Ti-O system infusing p-type character to the oxide. The extent of p-type nature of the oxide is thus a function of Al% incorporated in the oxide, with maximum p-type nature corresponding to aluminium and titanium oxides in a specific ratio of. The gate metal deposition involves the Ti/TiN metal stack and the self-aligned pGaN etch uses the Ti/TiN metal stack as the hard mask. Depending on the surface conditions of the top surface, AlTiO crystalline quality may be tailored to change its dielctric and electrical properties.
[0084] In another embodiment, for the ALD process, the substrate on which the film is deposited can be cleaned thoroughly to remove contaminants, ensuring proper adhesion of the deposited film. In the ALD chamber, the substrate can be exposed to a precursor containing aluminium. This precursor reacts with the surface, binding aluminium atoms to it. Excess precursor can be purged to remove any unreacted molecules. Oxygen or an oxygen-containing compound is introduced into the chamber. It reacts with the aluminium atoms on the surface, forming a layer of aluminium oxide (Al2O3). The excess oxygen source is purged. A titanium-containing precursor is introduced in the chamber, reacting with the aluminium oxide surface to form a layer of aluminium titanium oxide. The excess titanium precursor is also purged. Oxygen is introduced again, reacting with the titanium atoms to form titanium oxide (TiO2). Excess oxygen can be purged and to achieve the desired film thickness and composition, these steps can be repeated for a number of cycles. The result of these sequential reactions is the controlled growth of a thin film with a specific stoichiometry of AlxTi1-xO. The self-limiting nature of the reactions ensures precise control over film thickness, and complex and high-aspect-ratio structures.
[0085] In an embodiment, the devices in the system were fabricated on a commercial grade 600-V E- mode MOCVD-grown 6-inch GaN-on-Si wafer. The epistructure features 75nm p-GaN with 2-3×1017 cm-3 electrically activated Mg-doping, 14nm Al0.2Ga0.8N barrier, 1nm AlN spacer, 175nm GaN channel and 5.5µm GaN buffer on p-Si (111). FIG. 1 depicts a brief process flow with the cross-sectional schematic of the devices. For AlTiO/p-GaN gated devices, the fabrication process began with the blanket Atomic Layer Etching (ALE) of p-GaN using O2/BCl3 plasma followed by annealing at 800°C 10min in N2 to recover damage due to annealing and improve Mg activation in p-GaN. AlTiO was deposited using thermal atomic layer deposition (ALD) with a well-optimized process.
[0086] Referring to FIG. 1B, the flowchart further indicates enabling AlTiO/pGaN integration. After the initial steps of substrate preparation, AlTiO deposition and annealing, MESA etching, which is a semiconductor manufacturing process used to define isolation regions or boundaries for device-device isolation is carried out. Next, etching the ohmic contact formation comprises a deposition of a metal stack (e.g., Ni/Au) for ohmic contact formation on the pGaN. There is annealing to ensure low-resistance electrical contacts. A bilayer passivation deposition involves depositing a bilayer passivation (SiO2/AlTiO) over the entire structure using techniques like ICPCVD and ALD. The passivation opening and patterning includes applying photolithography to define areas for contact pads and openings in the passivation layers. There are also etch openings in the passivation layers down to the ohmic contacts. The S/D Metal thickening process involves depositing metal (e.g., Ti/Al/Ni/Au) for source and drain (S/D) contacts using techniques like evaporation or sputtering. This step thickens the metal in the S/D regions and the post metallization anneal involves annealing the structure to improve metal-semiconductor contacts and overall device performance.
[0087] In an embodiment, considering an example, the system can design a gate stack for p-GaN gate E-mode HEMTs with high threshold voltage and high breakdown voltage characteristics. For this, the user chooses suitable dielectric materials that have a high dielectric constant (?) to increase the gate capacitance and enable a higher threshold voltage (VTH). These materials might include AlTiO or other advanced dielectrics. It can also utilize a multilayer gate stack design that consists of several distinct layers. For example: A buffer layer to provide proper interface with the p-GaN layer, an insulating dielectric layer, such as AlTiO, to increase gate capacitance, and a passivation layer to protect the dielectric and gate stack. The system chooses a suitable gate electrode material that complements the dielectric and p-GaN layers. Common choices include metals like TiN, Ti/TiN that provide good electrical contact and thermal stability. The system can adjust the thickness and composition of the dielectric layer to achieve the desired threshold voltage (VTH). A thicker dielectric can increase Vth and properly engineer the interfaces between different layers to minimize defects and leakage currents. The system can also employ advanced semiconductor fabrication techniques, such as atomic layer deposition (ALD) or molecular beam epitaxy (MBE), to precisely deposit and control the thickness of each layer.
[0088] To elaborate the steps as shown in FIG. 1B, The method steps provided outline a process for fabricating a GaN-based high-electron-mobility transistor (HEMT) with specific material layers and treatment processes. Here’s an elaboration on each step:
[0089] Atomic Layer Etching of p-GaN (thickness = 60-80 nm):
[0090] Process: Atomic Layer Etching (ALE) is a highly precise etching technique that allows for the controlled removal of material layers with atomic-scale accuracy. In this step, the p-type GaN (p-GaN) layer, with a thickness between 60-80 nm, is etched to achieve the desired thickness and surface quality.
[0091] Purpose:This etching process ensures the precise thinning of the p-GaN layer, which is critical for achieving the desired electrical characteristics of the HEMT device. The accuracy of ALE minimizes damage and roughness, which is important for the subsequent steps.
[0092] p-GaN Annealing @ 800°C, N2 ambient, 10 minutes:
[0093] Process Annealing involves heating the p-GaN layer to 800°C in a nitrogen (N2) ambient environment for 10 minutes.
[0094] Purpose: The annealing process is used to repair any defects or damage introduced during the etching process. It can also activate dopants in the p-GaN layer, improving the electrical properties of the material, such as reducing resistivity and enhancing carrier concentration.
[0095] Atomic Layer Deposition of Al2Ti05 (gate dielectric, thickness = 10 nm):
[0096] Process: Atomic Layer Deposition (ALD) is a thin-film deposition technique that provides excellent control over film thickness and uniformity. In this step, a 10 nm layer of aluminium titanium oxide (AlxTi1-xO) is deposited as the gate dielectric.
[0097] Purpose: The AlxTi1-xO layer serves as gate leakage barrier layer in the gate stack to obtain a careful balance of leakages and enable threshold voltage enhancement minimizing leakage current and increase gate overdrive.
[0098] Gate Metal Deposition: Ti/TiN Metal Stack:
[0099] Process: This step involves the deposition of a titanium/titanium nitride (Ti/TiN) metal stack to form the gate electrode.
[0100] Purpose: Ti/TiN is chosen for its low work function, which helps achieve the desired threshold voltage for the HEMT. The metal stack also provides good adhesion and electrical contact with the underlying gate dielectric.
[0101] Self-Aligned p-GaN Etch Using Ti/TiN as Hard Mask:
[0102] Process: In this step, the p-GaN layer is etched in a self-aligned manner, using the Ti/TiN gate metal as a hard mask.
[0103] Purpose: The self-aligned etch ensures that the p-GaN layer is only removed in regions where the gate metal does not cover it, which is crucial for defining the active region of the device. This step helps in accurately aligning the gate with the underlying layers, reducing parasitic capacitance and resistance.
[0104] MESA Etching for Device-to-Device Isolation:
[0105] Process: MESA etching involves etching away material to create a physical separation (MESA) between individual devices on the same wafer.
[0106] Purpose: This etching step isolates each device from its neighbors, preventing electrical interference and crosstalk, which is essential for the proper functioning of each device within an integrated circuit.
[0107] Ohmic Contact Formation: Ti/Ni/Al/Au Metal Stack:
[0108] Process: Ohmic contacts are formed by depositing a metal stack of titanium (Ti), nickel (Ni), aluminium (Al), and gold (Au) on the source and drain regions.
[0109] Purpose: The metal stack is chosen to form low-resistance, non-rectifying (ohmic) contacts with the GaN material. The metals are often annealed after deposition to enhance alloying and improve contact properties, ensuring efficient current flow between the metal and the semiconductor.
[0110] Bilayer Passivation Deposition: ICPCVD SiOx/ALD AlxTi1-xO:
[0111] Process: A bilayer passivation is applied to the device, consisting of silicon dioxide (SiO2) deposited using Inductively Coupled Plasma Chemical Vapor Deposition (ICPCVD) and a layer of Al2Ti05 deposited using Atomic Layer Deposition (ALD).
[0112] Purpose: Passivation layers protect the device surface from environmental contaminants, moisture, and mechanical damage. The SiO2/Al2Ti05 combination provides excellent electrical insulation, reduces surface states, and enhances the device's long-term stability.
[0113] Passivation Opening and Patterning:
[0114] Process: After passivation, specific regions of the passivation layer are selectively etched away (opened) and patterned to expose underlying contacts (e.g., source, drain, and gate regions) for further processing or interconnections.
[0115] Purpose: This step prepares the device for subsequent metallization or interconnect formation, allowing access to the underlying layers without compromising the protective passivation.
[0116] Source/Drain Metal Thickening and Post Metallization Anneal: Process: The source and drain metal contacts are thickened by additional metal deposition, followed by a post-metallization anneal.
[0117] Purpose: Thickening the metal layers reduces the contact resistance and enhances current-carrying capacity, which is crucial for high-power applications. The post-metallization anneal further improves the metal-semiconductor interface, reducing contact resistance and enhancing device performance.
[0118] This process sequence describes a detailed fabrication method for a GaN HEMT device with a focus on precision etching, deposition, and annealing steps to achieve a high-performance, normally-off power transistor. Each step is carefully designed to ensure the device's structural integrity, electrical performance, and long-term reliability, making it suitable for high-power and high-frequency applications.
[0119] The method steps are summarized in following steps:
[0120] Step 1002: Atomic Layer Etching (ALE) of a p-type gallium nitride (p-GaN) layer to achieve a thickness of approximately 60-80 nm.
[0121] Step 1004: Annealing the etched p-GaN layer at approximately 800°C in a nitrogen (N2) ambient environment for a duration of 10 minutes.
[0122] Step 1006: Depositing a gate dielectric layer of aluminum titanium oxide (Al2Ti05) to a thickness of approximately 10 nm using atomic layer deposition (ALD).
[0123] Step 1008: Depositing a gate metal stack comprising titanium/titanium nitride (Ti/TiN) onto the gate dielectric layer.
[0124] Step 1010: Etching the p-GaN layer in a self-aligned manner using the Ti/TiN gate metal stack as a hard mask.
[0125] Step 1012: Performing MESA etching to isolate individual devices by removing material between adjacent devices.
[0126] Step 1014: Forming ohmic contacts by depositing a metal stack comprising titanium (Ti), nickel (Ni), aluminum (Al), and gold (Au) on the source and drain regions.
[0127] Step 1016: Depositing a bilayer passivation** comprising silicon dioxide (SiO2) using inductively coupled plasma chemical vapor deposition (ICPCVD) and aluminum titanium oxide (Al2Ti05) using atomic layer deposition (ALD).
[0128] Step 1018: Opening and patterning the passivation layer** to expose underlying regions for electrical connections.
[0129] Step 1020: Thickening the source and drain metal contacts** by additional metal deposition followed by post-metallization annealing.
[0130] Referrng again to FIGs. 1A and 1C illustrates a cross-sectional view of a GaN-based high-electron-mobility transistor (HEMT) structure. This device is widely used in power electronics and high-frequency applications due to the unique properties of GaN (gallium nitride) and the 2D electron gas (2DEG) that forms at the interface between GaN and AlGaN (aluminum gallium nitride). In an impementaiton, following componets/structurs play crucial role:
[0131] Ti/TiN Gate Metal (Top Layer): Titanium/Titanium Nitride: The gate metal controls the flow of current between the source and drain by modulating the 2DEG at the GaN/AlGaN interface. The work function of Ti/TiN influences the threshold voltage of the device.
[0132] AlTiO (p-Dielectric): Aluminum Titanium Oxide: AlTiO is a dielectric material, meaning it has a high dielectric constant, which helps in enhancing the gate capacitance while minimizing gate leakage. This layer is critical in providing an insulating barrier between the gate metal and the underlying p-GaN layer. Preferred thickness, 10 nm.
[0133] p-GaN Layer: p-type Gallium Nitride: The p-GaN layer serves as a gate barrier. Its p-type nature (doped with acceptors) allows for depletion-mode operation in normally-off HEMTs (where the device is off at zero gate voltage). When a positive voltage is applied to the gate, the p-GaN layer is depleted, enabling the 2DEG in the underlying GaN/AlGaN heterostructure.
[0134] AlGaN Barrier: Aluminum Gallium Nitride: The AlGaN barrier layer is crucial for the formation of the 2DEG at its interface with the UID (unintentionally doped) GaN channel. The high polarization difference between AlGaN and GaN creates a strong electric field, leading to the formation of the 2DEG without intentional doping. Preferred thickness, 12 nm.
[0135] AlN Barrier: Aluminum Nitride: The AlN barrier further enhances the 2DEG by increasing the polarization-induced electric field at the GaN/AlGaN interface, leading to higher electron density and mobility in the 2DEG channel. Preferred thickness, 1 nm.
[0136] UID GaN Channel: Unintentionally Doped Gallium Nitride: This is the main channel where current flows. The 2DEG forms at the interface between the GaN channel and the AlGaN barrier, providing a highly conductive path with low resistance for electrons.
[0137] GaN Buffer Layer: Gallium Nitride: The buffer layer is essential for stress management and isolation. It provides a transition layer between the GaN channel and the silicon substrate, managing lattice mismatch and thermal expansion differences. Preferred thickness, ~5 µm.
[0138] Silicon Substrate: Silicon: The entire structure is built on a silicon substrate, which is cost-effective and supports large-scale integration.
[0139] Working Mechanism:
[0140] 2DEG Formation: The 2DEG forms at the interface between the UID GaN channel and the AlGaN barrier due to the polarization fields in the materials. This electron gas provides a conductive channel with very high mobility and low scattering.
[0141] Gate Operation: The Ti/TiN gate metal controls the electron density in the 2DEG. When a positive voltage is applied to the gate, the p-GaN layer depletes, which influences the electron density in the 2DEG channel. The AlTiO layer acts as a dielectric, enhancing gate control while reducing leakage.
[0142] Normally-Off Operation: The p-GaN layer allows the HEMT to operate in a normally-off mode. Without a gate bias, the p-GaN layer depletes the 2DEG, ensuring the device remains off. Applying a gate voltage creates an electric field that modulates the 2DEG, turning the device on.
[0143] The combination of dielectric (AlTiO), p-GaN, and the AlGaN barrier leads to efficient device operation, with low power losses and high electron mobility.
[0144] The combination of dielectric (AlTiO), p-GaN, and the AlGaN barrier leads to efficient device operation, with low power losses and high electron mobility.
[0145] This design is widely used in power electronics, particularly in applications requiring high efficiency, high power density, and high-speed switching.
[0146] FIGs. 2A-2B illustrate a graphical representation of the transfer characteristics of conventional Schottky metal/p-GaN (75nm) gated HEMT (sample P) and Schottky metal/p-Al0.5Ti0.5O (10nm)/p-GaN (75nm) HEMT (sample PA) in (a) linear, and (b) semi-log scale in accordance with an embodiment of the present disclosure.
[0147] Referring to FIGs. 2A-2B, they illustrate transfer characteristics of conventional Schottky metal/p-GaN (75nm) gated HEMT (sample P) and Schottky metal/p-Al 0.5 Ti 0.5 O (10nm)/p-GaN (75nm) HEMT (sample PA) in (a) linear, and (b) semi-log scale. A comparison of the transfer curves reveals p-AlTiO/p-GaN integration to result in a positive shift in V TH. The HEMTs based on both gate stack designs exhibit comparable I ON /I OFF ratio (~10 7). Inset of (b) shows the AlTiO integration results in improved I ON. FIG. 2C illustrates a statistical distribution of V TH (extracted using maximum transconductance method) and gm (extracted in the linear regime at VDS = 1V), measured across 50 devices, shows gate control to improve with p-GaN/AlTiO integration in addition to a positive VTH shift owing to high ? and p-type property of AlTiO. The graphical representations 200 of the ID -V GS characteristics of the conventional p-GaN gated HEMT (device-P) and p-AlTiO/p-GaN gated HEMT (device-PA) are detailed. Compared with the conventional device P, the integrated PA device shows higher VTH and improved gm. More importantly, the ON-current is also significantly increased. This VTH tuning behavior is attributed to the p-type property of AlTiO.
[0148] In an embodiment, the p-GaN layer is a semiconductor material with p-type doping, meaning it contains an excess of positive charge carriers (holes). This layer is the active region of the semiconductor device. The Schottky metal electrode is a metal layer that is in direct contact with the p-GaN layer. The choice of metal is important, as it influences the electrical properties of the resulting Schottky diode. The metal forms a rectifying contact with the semiconductor, resulting in a built-in potential barrier at the interface. The contact between the Schottky metal and the p-GaN forms a rectifying junction called a Schottky barrier. This barrier inhibits the flow of current when a voltage bias is applied in the direction that opposes the built-in potential barrier. However, when the bias is applied in the direction that assists the barrier, the diode allows current to flow. Schottky diodes typically exhibit fast switching characteristics due to their lack of a depletion region (as seen in p-n junction diodes). This makes them useful for high-frequency applications. The Schottky barrier height is a critical parameter that determines the diode's forward voltage drop and its ability to conduct.
[0149] Referring to FIG. 2A, the transfer characteristics of conventional Schottky metal/p-GaN (75nm) gated HEMT (sample P) and Schottky metal/p-Al 0.5 Ti 0.5 O(10nm)/p-GaN (75nm) HEMT (sample PA) in a linear form is disclosed. A comparison of the transfer curves reveals p-AlTiO/p-GaN integration to result in a positive shift in VTH. The HEMTs based on both gate stack designs exhibit comparable ION /IOFF ratio (~107). It also depicts the AlTiO integration results in improved ION. Statistical distribution of V TH (extracted using maximum transconductance method) and gm (extracted in the linear regime at V DS = 1V), measured across 50 devices, shows gate control to improve with p-GaN/AlTiO integration in addition to a positive VTH shift owing to high ? and p-type property of AlTiO.
[0150] Referring to FIG. 2B, the transfer characteristics of conventional Schottky metal/p-GaN (75nm) gated HEMT (sample P) and Schottky metal/p- Al0.5Ti0.5O (10nm)/p-GaN (75nm) HEMT (sample PA) in a semi-log scale is disclosed. The transfer characteristics represent the relationship between the gate-source voltage (VGS) and the drain-source current (ID) of a transistor. In a semi-log scale, one axis (typically the vertical axis) is scaled logarithmically, which helps in visualizing a wide range of values. For both sample P (conventional Schottky metal/p-GaN HEMT) and sample PA (Schottky metal/p- AlxTi1-xO (10nm)/p-GaN HEMT), the transfer characteristics might exhibit similar shapes, but the presence of the AlTiO gate oxide layer in sample PA could lead to some differences. Here, the as VGS becomes more positive (in the forward bias region), ID increases rapidly, indicating the device is turning on. The rate of increase in Id with increasing VGS may decrease at higher VGS due to device saturation. In the reverse bias region (VGS < 0), ID remains very low, indicating the device is off. For sample PA (Schottky metal/p- AlxTi1-xO (10nm)/p-GaN HEMT): the presence of the AlTiO gate oxide layer may introduce a threshold voltage or modify the threshold behavior compared to sample P. As VGS becomes more positive, ID increases, similar to sample P. The oxide layer might affect the subthreshold slope and threshold voltage, possibly leading to improved gate control over the device.
[0151] FIG. 2C illustrates statistical distribution of VTH and transconductance (gm) showing gate control to improve with p-GaN/AlTiO integration in addition to a positive VTH.
[0152] Referring to FIG. 2C, the statistical distribution of VTH (extracted using maximum transconductance method) and gm (extracted in the linear regime at VDS = 1V), measured across 50 devices, shows gate control to improve with p-GaN/AlTiO integration in addition to a positive VTH shift owing to high ? and p-type property of AlTiO is disclosed. The graph represents a conventional Schottky metal/p-GaN HEMT (sample P), and the other is a Schottky metal/p- Al0.5Ti0.5O (10nm)/p-GaN HEMT (sample PA). The x-axis represents the samples (P and PA), and the y-axis represents the threshold voltage (VTH) of the HEMTs. The graph shows the relationship between the different samples and their respective threshold voltages. The threshold voltage for sample P is represented on the graph. This threshold voltage is the gate-source voltage at which the device starts to conduct or turn on. The threshold voltage for sample PA could be relatively higher compared to sample P due to the absence of the additional AlTiO gate oxide layer in sample P. The threshold voltage of P and PA is depicted on the graph. The presence of the AlTiO gate oxide layer may influence the threshold behavior of the device. Sample PA exhibits a higher threshold voltage compared to sample P due to the effect of the gate oxide layer.
[0153] FIGs. 3A-3D illustrate the thermal equilibrium energy band diagram for the p-GaN/AlGaN/GaN stack with varying p-GaN thicknesses and its implications on devices characteristics, in accordance with an embodiment of the present disclosure.
[0154] Referring to FIGs. 3A-3D, they illustrate the thermal equilibrium energy band diagram for the p-GaN/AlGaN/GaN stack with varying p-GaN thicknesses of 75nm (sample P) and 64nm (sample PE). Referring to FIG. 3A, the values correspond to different p-GaN doping concentrations: 1018 cm-3 (high) and 1017 cm-3 (low), respectively. For the high doping case, reducing the p-GaN thickness from 75nm to 64nm eliminates the floating flat-energy region in the 75nm stack, without impacting the channel conditions. In the lightly doped case, decreasing the p-GaN thickness to 64nm brings the conduction band edge closer to the Fermi level, and can potentially reduce V TH. Annealing was performed on the samples to enhance p-GaN activation and enable variable p-GaN thickness.
[0155] Referring to FIG. 3B, the experimental transfer characteristics of sample P, sample PE, and sample PAE (integrating p- Al0.5Ti0.5O with thin p-GaN) are presented. While samples P and PE exhibit similar transfer characteristics, sample PAE demonstrates a significant positive VTH shift, surpassing the integration of p-AlTiO with thicker p-GaN (sample PA).
[0156] Referring to FIGs. 3C and 3D, a comparison of VTH and gm distribution and maximum current driving capability with RON distribution (inset, extracted in the linear regime at VDS = 0.2V and VGS -VTH = 5V) reveals that HEMTs with AlTiO integrated on thinner p-GaN can be driven at a large gate overdrive enabling the HEMT to carry large ON-currents. In FIG. 3C, a VTH and gm distribution indicates variations in device properties from one transistor to another. In the GaN HEMT, in FIG. 3D, as gate-source voltage (VGS) increases, the drain current (ID) (current flowing from drain to source) also increases in the saturation region. GaN HEMTs are known for their high electron mobility and ability to handle high-power and high-frequency signals. The specific shape and behavior of the VGS vs ID curve can vary based on the material composition, device design, and operating conditions of the HEMTs. These graphs provide a general representation of the behavior of HEMTs, but the actual characteristics can differ depending on the specific HEMT structure and parameters.
[0157] In an embodiment, annealing can be performed on the samples to enhance p-GaN activation and enable variable p-GaN thickness. Experimental transfer characteristics of sample P, sample PE, and sample PAE (integrating p- Al0.5Ti0.5 O with thin p-GaN) is carried out. While samples P and PE exhibit similar transfer characteristics, sample PAE demonstrates a significant positive VTH shift, surpassing the integration of p-AlTiO with thicker p-GaN (sample PA). A comparison of (c) VTH and gm distribution and maximum current driving capability with R ON distribution (inset, extracted in the linear regime at V DS = 0.2V and V GS - VTH = 5V reveals that HEMTs with AlTiO integrated on thinner p-GaN can be driven at a large gate overdrive enabling the HEMT to carry large ON-currents.
[0158] In an embodiment, a thinner p-GaN is expected to further improve AlTiO-channel coupling and to allow an improved VTH tunability with AlTiO. However, thinning out p-GaN can affect the VTH of the device. To estimate the possibility of thinning out p-GaN, TCAD (Technology Computer-Aided Design) simulations can be carried out. A flat-energy floating p-GaN region is present in the p-GaN layer for moderate and higher p-GaN doping. The same may be absent in devices with lower p-GaN doping. If the flat energy band region has minimal impact on the gate electrostatics, it represents the possibility of thinning out the p-GaN without affecting the VTH. However, the same can be achieved only if p-GaN doping is sufficiently high. The high-temperature p-GaN anneal step ensures the device samples have improved p-GaN Mg-activation which is supported by improved p-GaN conductivity with the measurement of the annealing process. Experimentation on devices with 20nm p-GaN etch (device-PE) shows the p-GaN etching to have no impact on VTH and the ON current of the device. Integration of AlTiO with this thinner p-GaN (device- PEA) resulted in a further improvement in VTH and also improved gm. Furthermore, the devices can show an improved RON and the integration of AlTiO on p-GaN offers a higher VTH with improved gate control (reflected in high gm) and improved RON.
[0159] In an embodiment, TCAD simulations refer to computational tools and techniques used to model and simulate semiconductor device behavior at a process and device level. The process simulation involves modeling the fabrication steps used to create semiconductor devices. For example, it can help predict how different process parameters affect device characteristics. This includes steps like doping, oxidation, diffusion, etching, and deposition of various materials. Process simulations help optimize device structures and manufacturing processes. The TCAD tool can use the finite element method to solve partial differential equations that describe the physical processes within semiconductor devices. TCAD simulations can also incorporate optical and thermal effects, which are crucial for devices like photodetectors and LEDs.
[0160] FIG. 4A illustrates the distribution of gate leakage and maximum allowable gate overdrive for samples P, PE, PA, and PAE, in accordance with an embodiment of the present disclosure.
[0161] Referring to FIG. 4A, it shows the distribution of gate leakage and maximum allowable gate overdrive for samples P, PE, PA, and PAE. The results indicate that etching p-GaN increases gate leakage, but integrating AlTiO effectively suppresses this increase and improves gate breakdown voltage. Additionally, referring to FIG. 4B, dynamic instability in VTH resulting from ON-state large gate over-drive (6V) DC stress is evaluated. Compared to the reference p-GaN sample (P), the AlTiO/p-GaN samples (PA, PAE) exhibit lower ?V TH. Thus, the integration of AlTiO enables reliable operation at large gate overdrive.
[0162] In an embodiment, it can be found that two-dimensional variable range hopping is responsible for gate leakage current at the reverse gate bias and low forward gate bias in both high-leakage and low-leakage Schottky gate contact devices. At high forward gate bias, in the case of high-leakage Schottky contact, the dominant current conduction mechanism is found to be thermionic field emission while it is Poole-Frenkle emission (PFE) for the case of low-leakage Schottky contact and the activation energy of trap states for PFE current is derived as 0.6 eV. To measure this Gate-Source leakage current of a MOSFET, at first, a short Drain pin and a Source pin is used, and then, maximum allowable voltage is applied on the Gate-Source and the leakage current of Gate- Source is monitored.
[0163] FIG. 4B illustrates dynamic instability in VTH in accordance with an embodiment of the present disclosure.
[0164] Referring to FIG. 4B, the illustration 400 of dynamic instability in the threshold voltage (VTH) of HEMTs is disclosed which can arise due to various factors, including trapping and de-trapping effects wherein charge trapping and de-trapping in the gate and barrier regions of the HEMT can lead to shifts in the threshold voltage over time. Trapped charges can influence the gate control and result in variations in the VTH. Temperature changes can impact the mobility of electrons in the channel, affecting the threshold voltage exhibiting dynamic shifts. Continuous operation of the HEMT under certain bias conditions can cause charge trapping and de-trapping, leading to dynamic changes in the threshold voltage. This effect is particularly relevant in applications where the HEMT operates at elevated bias levels. Power dissipation within the HEMT can lead to localized heating, causing changes in the electron mobility and subsequently affecting the VTH. Variations in the fabrication process can lead to variations in the device characteristics, including threshold voltage. These variations can be exacerbated by temperature changes or bias stress, causing dynamic instability.
[0165] In an embodiment, the system shows typical gate breakdown characteristics for the samples P, PA, PE, and PAE, with FIG. 4A showing the statistical distribution of the gate leakage. It demonstrates that the gate leakage marginally increases after the p-GaN etch. To this end as well, the integration of AlTiO with p-GaN improves the gate leakage irrespective of the p-GaN thickness, offering the best possible gate leakage performance. The gate overdrive achieved for these device variants is also compared. The use of AlTiO in the gate improves the gate overdrive performance and improves the gate overdrive from 7.14V to 9.75V for the 75nm p-GaN (device-PA) and from 7.17V to 9.44V for the 64nm p-GaN (device PAE). To evaluate the dynamic VTH instability of the proposed gate stack, the devices were stressed at a high overdrive voltage of 6V for 50s. The proposed stacks (PA, PAE) showed lower VTH shift as compared to the conventional p-GaN stack (P). The symbols description is summarized in Table 1.

Sample Description
P or Pact-75nm Conventional p-GaN(75nm) stack
PE or Pact-64nm Thinner p-GaN(64nm) stack
PA or A AlTiO/75nm p-GaN stack, AlTiO with moderate disorder
PAE or B AlTiO/64nm p-GaN stack, AlTiO higher disorder and grain boundaries
C AlTiO/64nm p-GaN stack-Leaky and uniform AlTiO
Table 1: Symbols Description
[0166] FIG. 5 illustrates a comparison of device characteristics for devices with thermal activation, in accordance with an embodiment of the present disclosure. As shown, the conductivity measurements using special test structures (inset) with 10 µm spaced metal/p-GaN junctions confirmed improved Mg activation in annealed samples. This results in higher conductivity and significantly increased gate leakage with comparable VTH. The figure also compares devices with varying p-GaN thickness, showing comparable VTH and ON-state leakages. Increased gate leakage is attributed to the thinner metal/p-GaN barrier, causing higher tunneling current from the gate.
[0167] FIGs. 6A-6C illustrates a P-GaN equilibrium depletion width as a function of p-GaN doping and metal work function, in accordance with an embodiment of the present disclosure. As shown, For a given p-GaN thickness and metal work function,p-GaN may be either fully depleted or partially depleted. (b) p-GaN depletion scenarios: fully depleted for low doping and partially depleted for high doping. (c) Schematic band diagram of metal/p-GaN gate stack showing potential variations and charge flow due to leakage routes, with hole supply from the gate and p-GaN depletion towards the p-GaN/AlGaN interface, where holes may accumulate or leak through the barrier via trap-assisted recombination. The schematic forms the base for model developed.
[0168] FIG. 7(a) illustrates STEM image of the device cross-section, and FIG. 7(b) illustrates a schematic of leakage routes in the p-GaN gate stack, including through the gate/pGaN, p-GaN sidewall, and AlGaN barrier, in accordance with an embodiment of the present disclosure. As shown, factors influencing leakage are metal choice, p-GaN/metal interface quality, sidewall quality, passivation nature, barrier Al content and traps, p-GaN doping and thickness, and so on. These leakage paths can alter gate-to-channel coupling and affect the turn-on process.
[0169] FIGs. 8(a)-8(b) illustrates an impact of AlGaN barrier leakage on device characteristics using a well-calibrated computational framework, in accordance with an embodiment of the present disclosure. As shown, FIG.8(a) and (b) illustrate that the devices with low p-GaN doping show comparable VTH with suppressed leakage. For higher p-GaN doping, devices show similar VTH for non-leaky barriers, but higher VTH with leaky barriers, however with degraded subthreshold properties
[0170] FIG. 9(a) illustrates temporal change in AlGaN surface potential with incoming hole supply, showing accelerated accumulation at the p-GaN/AlGaN interface and subsequent 2DEG formation, and FIG. 9(b) illustrates a contrast with a leaky barrier, exhibiting no hole buildup or surface potential variation, preventing 2DEG formation, in accordance with an embodiment of the present disclosure.
[0171] FIG. 10 illustrates (a) Comparison of AlGaN surface potential and 2DEG formation across gate voltage in fully and partially depleted modes, highlighting predictive accuracy of the model. Band diagrams along the gate stack demonstrate (b) direct control over the AlGaN surface potential in the fully depleted case. (c) a parallel shift of the bands due to hole accumulation, resulting in ?Vg ~ ?Vfi, which maintains a consistent depletion. (d) In the h-depletion mode, the depletion extends due to minimal changes in ?Vfi, in accordance with an embodiment of the present disclosure. It can be noted that, when the depletion reaches the p-GaN/AlGaN interface, the device begins its turn-on process.
[0172] FIGs. 11(a)-11(b) illustrates device's turn-on process varies with incoming hole supply, showing that suppressed hole injection can enhance VTH without sacrificing subthreshold performance. However, higher p-GaN doping may limit VTH potential due to increased hole injection from the gate, indicating that inserting a gate dielectric could optimize VTH, in accordance with an embodiment of the present disclosure.
[0173] FIG. 12 illustrates (a) Transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN activated doping. (b) Equilibrium band diagrams showing s higher doping shrinks the p-GaN depletion width, therefore a complete p-GaN depletion is delayed to turn on the device giving high Vth, in accordance with an embodiment of the present disclosure. It may be appreciated by a person skilled in the art that the depletion extension mode is a process mode in which the device turn-on process is governed by p-GaN layer depletion, once the depletion extends to AlGaN barrier layer, device turn-ON process starts.
[0174] FIG. 13 illustrates (a) Transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN thickness. (b) Equilibrium band diagrams showing higher ease of thinner p-GaN for complete depletion to turn on the device, therefore giving lower Vth for thinner p-GaN devices, in accordance with an embodiment of the present disclosure. It may be appreciated by a person skilled in the art that the depletion extension mode is a process mode in which the device turn-on process is governed by p-GaN layer depletion, once the depletion extends to AlGaN barrier layer, device turn-ON process starts.
[0175] FIG. 14 illustrates (a) AlTiO/p-GaN integrated gate stack with varying crystalline quality. (b) Process A shows moderate disorder. (c) Process B has grain boundaries and higher disorder. (d) Process C exhibits more uniform quality. (e) AlTiO composition with VBE and bandgap values from UPS and UV-Vis spectroscopy for calibrated computations. (f) Process A devices show a moderate VTH shift, while Process B devices show a significantly higher VTH with similar ON/OFF ratios despite being integrated on thinner p-GaN. (g) Process C devices have a lower VTH due to increased gate leakage, indicating hole accumulation mode, in contrast to Process B, which operates in hole depletion mode with suppressed leakage. (h) Comparison of gate leakage and VTH shows Process B devices with maximum VTH and suppressed leakage., in accordance with an embodiment of the present disclosure.
[0176] FIG. 15 illustrates (a) Transfer characteristics of the devices with non-leaky and leaky dielctric. It can be observed that the devices with a leaky dielctric show a low Vth, whereas devices with non-leaky dielctric show a higher Vth. (b) devices turns on through hole accumulation mode in a leaky dielctric case (c) devices turns on in the hole depletion mode in a non-leaky dielctric case, in accordance with an embodiment of the present disclosure.
[0177] FIG. 16 illustrates (a) Gate capacitance measurements reveal a difference in VTH between devices from processes A and B, despite similar ON-state capacitance. The thicker p-GaN in process A suggests lower capacitance, indicating a possible alteration in the AlTiO dielectric constant due to varying crystalline quality—more disorder results in a lower dielectric constant (K) and delayed depletion (c). (b) Device characteristics show consistent VTH aligned with model extracted K-values, in accordance with an embodiment of the present disclosure.
[0178] FIG. 17 illustrates (a) shows Vth dependence on the energy bandgap of the gate dielctric showing higher Vth for wider bandgap dielctric (b) Initial band diagram showing the increase is Vth can be attributed to the delayed p-GaN depletion effect, in accordance with an embodiment of the present disclosure.
[0179] FIG. 18 illustrates (a) Vth dependence on the electron affinity of the gate dielctric showing higher Vth for dielectric with high electron affinity (b) Initial band diagram showing the increase is Vth can be attributed to the delayed p-GaN depletion effect, in accordance with an embodiment of the present disclosure.
[0180] FIG. 19 illustrates Vth relationship of proposed high Vth devices as a function of Vth of ohmic device. Equation shows an inverse relationship between gate dielctric capacitance and device’s Vth, in accordance with an embodiment of the present disclosure.
[0181] FIG. 20 illustrates (a) Dynamic instability in VTH due to 6V DC stress shows that AlTiO/pGaN samples (A, B) have lower ?VTH than those without AlTiO (b) Comparison of VG, Max versus VTH in this work with the state-of-the-art p-GaN gated HEMTs showing superior gate performance of demonstrated devices, in accordance with an embodiment of the present disclosure.
[0182] FIG. 21 illustrates exemplary variation of the semiconductor devices that may be without the passivation layer or may comprise any one or a combination of a passivation layer, a source or gate connected field plate, a spacer and a drain field plate, in accordance with an embodiment of the present disclosure.
[0183] FIG. 22 illustrates exemplary variation of the semiconductor devices that may be without the cap layer or may comprise cap layer may be introduced either fully extended to the source and drain or only on the gate side and partially or fully extended towards gate, in accordance with an embodiment of the present disclosure. The susbstrate layer may be a p-type oxide, crystalline or amorphous. Further, cap layer may be introduced either fully extended to the source and drain or only on the gate side and partially or fully extended towards gate. The cap layer may of GaN, p-type or intrinsic, AlON, or AlN and so on.
[0184] To summarize the above:
[0185] A unique relationship between the device turn-on process and leakage balance was identified, showing that turn-on occurs via hole accumulation and depletion modes. Operating in hole depletion mode through careful leakage balance was found to maximize VTH.
[0186] Devices working in hole accumulation mode do not have the potential to improve Vth as AlGaN surface potential is directly controlled by hole accumulation effect.
[0187] Devices working in depletion extension mode have potential to improve Vth. As gate voltage is increased, p-GaN depletion starts to extend, as soon as the depletion reaches the AlGaN, the device turn-on process starts. It may be appreciated by a person skilled in the art that the depletion extension mode is a process mode in which the device turn-on process is governed by p-GaN layer depletion, once the depletion extends to AlGaN barrier layer, device turn-ON process starts.
[0188] Factors such as p-GaN thickness, p-GaN doping., dielctric crystalline quality, dielctric constant, dielctric leakage, dielctric doping, dielctric bandgap and affinity, dielctric thickness are various factors that are revealed to maximize Vth.
[0189] Achieve a record-high VTH of 4.2 V and gate driving/breakdown voltage of 13.6 V. The VTH was also shown to be tuned by adjusting the crystalline quality, leakage, and dielectric, doping properties of dielctric
[0190] It is to be appreciated by a person skilled in the art that while various embodiments of the present disclosure have been elaborated for system for a high threshold voltage and a high breakdown gate stack in p-GaN gate e-mode HEMTs. However, the teachings of the present disclosure are also applicable for other types of applications as well, and all such embodiments are well within the scope of the present disclosure. However, a high threshold voltage and a high breakdown gate stack in p-GaN gate e-mode HEMTs, and all such embodiments are well within the scope of the present disclosure without any limitation.
[0191] Moreover, in interpreting the specification, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc.
[0192] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are comprised to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0193] The proposed invention provides a system for a method for high threshold voltage and high breakdown gate stack in p-GaN gate e-mode HEMTs.
[0194] The proposed invention provides a system that allows for the precise tuning of the threshold voltage (VTH) in p-GaN gate E-mode HEMTs with enhanced control that enables better management of the device's turn-on behavior and helps prevent unintended conduction, resulting in improved circuit stability and reduced power leakage.
[0195] The proposed invention provides a system that optimizes the gate stack design and using appropriate dielectric materials for an improved breakdown voltage characteristic ensures the device's robustness against high voltage levels, making it suitable for high-power applications without suffering from electrical breakdown.
[0196] The proposed invention provides a system that carefully engineers gate stack design contributes to the overall reliability of the p-GaN gate E-mode HEMTs.
[0197] The proposed invention provides a system that can help minimize leakage currents when the transistor is in the off-state as lower leakage currents result in improved power efficiency, preventing unnecessary energy wastage and heat generation.
[0198] The proposed invention provides a system is better suited for high-performance applications such as applications including power electronics, where precise control over the threshold voltage and robustness against high voltage are critical.
[0199] The proposed invention provides a system that is designed to integrate seamlessly with existing semiconductor manufacturing processes as this compatibility ensures that the improved gate stack can be incorporated into current production methods without major disruptions.
[0200] The proposed invention provides a system that aims to achieve these improvements in a cost-effective manner as the optimization of material usage, processing steps, and equipment requirements helps minimize production costs while achieving the desired performance enhancements.

,CLAIMS:1. A semiconductor device (100) comprising:
a dielectric material layer (114) provided on a Gallium nitride (GaN) layer (112), wherein the dielectric material layer comprises any or a combination of a p-type alloyed oxide, a p-type oxide, and a p-type semiconductor capable of being deposited on GaN layer (112).
2. The semiconductor device (100) as claimed in claim 1, wherein the dielectric material layer comprises a material having properties selected from any or a combination of a dielectric constant (?) having value < 50, a valence band energy greater than valence band energy of GaN, amorphous or crystalline, and p-type doping grown on etched or unetched GaN layer(112).
3. The semiconductor device (100) as claimed in claim 1, wherein:
the dielectric material layer comprises an aluminium titanium oxide (AlTiO) material, wherein the ratio between Al and Ti controls the P-type doping of AlTiO;
an alloyed oxide from the p-type alloyed oxide is selected from Al2O3, TiO2, and the like alloyed oxides; and
the GaN layer (112) comprises a semiconductor or oxide material having a p-type doping.
4. The semiconductor device (100) as claimed in claim 1, wherein the dielectric material layer (114) comprises a metal layer (116) positioned thereon, and wherein the metal layer (116) comprises any or a combination of a titanium Ti material, a titanium nitride (TiN) material, or a metal selected from tungsten (W), tantalum (Ta), tantalum nitride (TaN), Scandium (Sc), Nickel (Ni), Chromium (Cr), Gold (Au), and the like.
5. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) further comprising:
a substrate (102), wherein the substrate is made of a material selected from any or a combination of Silicon (Si), Silicon Carbide (SiC), sapphire, Qromis substrate technology (QST) and the like;
a buffer layer (104) formed on the substrate;
an unintentionally doped (UID) channel layer (106) positioned on the buffer layer (104);
a barrier layer (108) formed on the UID channel layer (106); and
the GaN layer (112) provided on the barrier layer (108);
wherein the buffer layer accommodates a lattice mismatch between the substrate and the buffer layer (104) and the UID channel layer (106); and
wherein the barrier layer (108) comprises an aluminium gallium nitride (AlGaN), Indium nitride (InN), Indium aluminium nitride (InAlN), aluminium nitride (AlN) or any combination thereof, barrier layer (110) positioned thereon such that the GaN layer (112) is provided on the AlGaN barrier layer (110), and wherein the AlGaN barrier layer enables a formation of a two-dimensional electron gas (2DEG) at an interface between the UID GaN channel layer and the AlGaN barrier layer.
6. The semiconductor device (100) as claimed in claim 1, wherein the dielectric material layer (114) is integrated with the Gallium nitride (GaN) layer (112).
7. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device is a high-electron-mobility transistor (HEMT) device.
8. The semiconductor device (100) as claimed in claim 1, wherein:
the semiconductor device (100) further comprises any one or a combination of a passivation layer (118), a field plate (FP) (120), a spacer (122), a CAP layer (124) and a drain field plate (DFP) (126).
9. A method for fabricating a semiconductor device, the method comprising the steps of:
performing (1002) an Atomic Layer Etching (ALE) of a p-type gallium nitride (p-GaN) layer;
annealing (1004) the etched p-GaN layer;
depositing (1006) a dielectric material layer of aluminium titanium oxide over the annealed p-GaN layer using atomic layer deposition (ALD);
depositing (1008) a gate metal stack comprising titanium/titanium nitride (Ti/TiN) onto the deposited dielectric material layer;
etching (1010) the p-GaN layer in a self-aligned manner using the Ti/TiN gate metal stack;
forming (1014) ohmic contacts by depositing a metal stack comprising a multilayer stacking of any or a combination of titanium (Ti), tantalum (Ta), a titanium nitride (TiN), aluminium (Al), nickel (Ni), Iridium (Ri), Platinum (Pt), Palladium (Pd), molybdenum (Mo), and gold (Au) on a source region and a drain region;
wherein the method of fabricating enables a p-type gallium nitride (p-GaN) layer positioned on the AlGaN barrier layer, an aluminium titanium oxide (AlTiO) gate dielectric layer positioned on the p-GaN layer, and a titanium Ti/ titanium nitride (TiN) gate metal layer positioned on the AlTiO gate dielectric layer.
10. The method as claimed in claim 10, wherein the method further comprising: performing (1012) MESA etching to isolate individual devices of the metal stack by removing material between adjacent devices;
depositing (1016) a bilayer passivation having silicon dioxide (SiO2) using inductively coupled plasma chemical vapor deposition (ICPCVD), and aluminium titanium oxide (ATiO) using atomic layer deposition (ALD); and
opening and patterning (1018) the passivation layer to expose regions for electrical connections; and
thickening (1020) the source and drain metal contacts by additional metal deposition followed by post-metallization annealing.