FIELD OF THE INVENTION
In aircraft, an ever-increasing amount of information is supplied in
the form of images, this information passes through a complex video
10 system before reaching cockpit and crew displays.
Video systems include: infrared and other wave length sensors,
optical cameras, radar, flight recorders, maplchart systems, synthetic
vision, image fusion systems, heads-up displays and heads-down
multifunction displays, video concentrators, and other subsystems.
15 ARINC 818 is a video interface and protocol standard developed
for high bandwidth, low latency, uncompressed digital video transmission.
It is a point-to-point, 8Bl10B encoded serial protocol for tr'ansmission of
video, audio, and data. The protocol is packetized, but is video-centric
and very flexible, supporting an array of complex video functions including
20 the multiplexing of multiple video streams on a single link or the
transmission of a single stream over a dual link.
The implementation of ARINC818 is tightly coupled- with the
various attributes of Frame Rate, Bit per frame rate, Color Encoding and
Speed .The same in hardware implementation requires IP Core based
25 implementation in Field Programmable Gate Arrays (FPGA1s) fixed to a
particular configuration.
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Annexure I
BACKGROUND OF THE INVENTION
In various data transmission requirement over ARINC818
,requirement to transmit data at variable rate over ARlNC 818 protocol is
35 required.
However, as IP Cores in FPGA are fixedlconfigured to a particular
ICD only, it becomes difficult to provide the. feature of variable data
transfer method during Run time of System.
In order to achieve the variable configurability during Run Time of
40 the system, method for Implementation of Variable ICD at Transmitter.
side in ARINC818 is felt necessary .
The benefits of the same will be:
Capable to execute variable data ratelspecs transmission during
Run Time of System
45 Capable to support real time/ high frequency operation of Systems.
SUMMARY OF PRESENT INVENTION
50 The present invention is about providing a method at Transmitter
side of ARINC818 protocol via which the IP Core of ARINC818
understands a request for change in the ICD and Transmits accordingly
over ARINC818 protocol for variable configuration,
DETAILED DESCRIPTION
ARINC818 Transmit Specifications:
Physical media: Shielded twisted pair, copper, on twinax
differential connector .
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Annexure I
Data rate: 1.0625 Gbls.
Video resolution: 1400 x 1050.
Scan type: progressive.
Video-synchronization: asynchronous video-signal.
Frame rate: 20 Hz at 24 bitlpixel with color encoding 8x8~8;
25 Hz at 16 bittpixel with color encoding 5x6~5.
Impedance: 150 Ohm.
The ARlNC 81 8 Embedded Card Module is a Video Converter Unit
70 which is designed with Cyclone-V GTFPGA, / Video Encoder and Decoder
to provide video interfacing requirements.
The system is responsible for DVI to ARINC818 conversion. The
system'runs on a 5V(nom) supply. It accepts DVI input and FPGA
75 converts it to ARlNC and Vice versa.
AEC supports 2# of DVI receivers and I # of DVI transmitter from
back panel. Similarly, the card accepts I# of ARlNC 818 input and
supports 2# of ARlNC 818 TX from front panel. ARlNC '818 channels
80 support 150-ohm copper channel connected to Transceiver interface of
Cyclone V FPGA.
Cyclone V GT FPGA implements the logic of converting ARlNC to
DVI & DVI to ARlNC with the help of ARlNC 818 IP cores.
Annexure I
FPGA Implementation
DVI to ARINC 818 Convertor
95 ' Description
DVI Receiver: Converts TMDS video signal to Native video signal.
NIOS II Processor: Used for DVI Receiver configuration via 12C.
Transceiver: Intel IP. Set it as in Transmitter Mode with line rate
1.0625 Gbps.
100 ARlNC 818-2 Transmitter: Packetize video streaming in ADVB
channel.
The FPGA is Altera's Cyclone V GT .Its functionality is to
accept the DVI video from the source and convert it to ARINC
video and vice versa.
It has the following interfaces:
a. 2 DVI receiver
b. DVI Encoder
c. ARINC transmitter
d. 2 ARINC receiver
f. UART Interface
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Annexure I
Configuration for Variable ICD Technoloqy: 4
The Block of DVI to ARlNC 818 at transmitter side is provided with
. 115 an external Discrete. The discrete is read in the card and sets a software
ba'sed FlagILogic 'for FPGA to read the logic. Once the flag is read ,the
.FPGA's IP Core is RESET or a frame delay of 15 Frames to 35 frames
(within 02.seconds max) is provided for allowing switching from one ICD
to another ICD.
Discrete Flag for ICD
Configurability
125 (Name of the Inventors)
130 anjeev Verma)
Dy. Manger (Design) Manager (Design)

CLAIMS
Accordingly, the ,description of the present inv.ention is to be
considered as illustrative only and is for the purpose of teaching those skilled
s in the art of the best mode of carrying out the invention. The details may be
varied substantially without departing from the spirit of the invention, and
exclusive use of all modifications which are within the scope of the appended
claims is reserved.
10 We Claim.
Method at Transmitter side of ARINC818 protocol via which the IP
Core of ARINC818 understands a request for change in the ICD and
Transmits accordingly over ARINC818 protocol which ensures Capability to
execute variable 'data ratelspecs transmission during Run Time of System
15 along with Capability to support real time1 high frequency operation of
Systems. It is a concept for variable configuration protocol specially invented
for specific application.