DESC:TECHNICAL FIELD
[0001] The present disclosure relates generally to high-electron mobility transistor (HEMT) devices. In particular, the present disclosure relates to a method of making high robustness E-mode HEMT.

BACKGROUND
[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[0003] Aiming towards fail-safe normally-off operation and simplified gate driver circuitry in power applications, p-gallium nitride (p-GaN) gated Aluminium Gallium Nitride (AlGaN)/GaN high-electron mobility transistors (HEMTs) are preferred. However, p-Gate HEMTs have a low VTH (<2V), leading to false turn-on issues. However, careful performance-reliability includes co-designing of the HEMT to maximize VTH without compromising gate stability and device performance.
[0004] Therefore, there is a need for robust HEMT device that can perform efficiently.

OBJECTS OF THE INVENTION
[0005] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are listed herein below.
[0006] It is an object of the present disclosure to provide a device and a method for a high-electron mobility transistor (HEMT) where (AlTiO) integration on p-gallium nitride (p-GaN) provides an improved gate overdrive.
[0007] It is an object of the present disclosure to provide a device where a gate structure includes the p-GaN structure disposed over a heterojunction structure with a sidewall slope configured with the p-GaN structure.
[0008] It is an object of the present disclosure to provide a device where the gate structure includes a p-type Aluminium Titanium Oxide (AlTiO) layer deposited on the p-GaN structure.
[0009] It is an object of the present disclosure to provide a device where the gate structure includes a metal layer disposed on the p-type AlTiO layer.
[0010] It is an object of the present disclosure to provide a device where a passivation layer is disposed on the heterojunction structure and abuts the gate structure.
[0011] It is an object of the present disclosure to provide a device where the sidewall slope exhibits a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability.

SUMMARY
[0012] This section is provided to introduce certain objects and aspects of the present disclosure in a simplified form that are further described below in the detailed description. This summary is not intended to identify the key features or the scope of the claimed subject matter.
[0013] In an aspect, the present disclosure relates to a High Electron Mobility Transistor (HEMT) device (102). The device (102) includes a gate structure comprising a p-gallium nitride (p-GaN) structure disposed over a heterojunction structure, where a sidewall slope is configured with the p-GaN structure. The gate structure includes a p-type Aluminium Titanium Oxide (AlTiO) layer deposited on the p-GaN structure. The gate structure includes a metal layer disposed on the p-type AlTiO layer. A passivation layer, where the passivation layer is disposed on the heterojunction structure and abuts the gate structure.
[0014] In an embodiment, the metal layer may include a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
[0015] In an embodiment, the passivation layer may include of a layer 1 with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 with an alloyed p-type AlXTi1-XO.
[0016] In an embodiment, the layer 1 may abut the p-GaN structure, the layer 2 may be disposed on an AlGaN barrier layer, which forms a part of the heterojunction structure, and the layer 3 may be disposed on the layer 1 and the layer 2.
[0017] In an embodiment, the sidewall slope may exhibit a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability.
[0018] In an embodiment, the AlTiO layer may include a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure.
[0019] In an embodiment, the heterojunction structure may include a source, a drain, and the gate structure.
[0020] In an aspect, the present disclosure relates to a method for fabricating a HEMT device. The method includes disposing a gate structure with a p-gallium nitride structure disposed over a heterojunction structure and configuring a sidewall slope is configured with the p-GaN structure. The method includes depositing, a p-type Aluminium Titanium Oxide (AlTiO) layer on the p-GaN structure. The method includes disposing, a metal layer on the p-type AlTiO layer. The method includes disposing, a passivation layer on the heterojunction structure which abuts the gate structure.
[0021] In an embodiment, the metal layer may include a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
[0022] In an embodiment, the passivation layer may include a layer 1 with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 with an alloyed p-type AlXTi1-XO.
[0023] In an embodiment, the layer 1 may abut the p-GaN structure, the layer 2 may be disposed on a AlGaN barrier layer, which forms a part of the heterojunction structure, and the layer 3 may be disposed on the layer 1 and the layer 2.
[0024] In an embodiment, the method may include exhibiting, by the sidewall slope, a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability.
[0025] In an embodiment, the p-type AlTiO layer may include a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure.

BRIEF DESCRIPTION OF DRAWINGS
[0026] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0027] FIG. 1A illustrates an exemplary schematic sectional representation (100A) of a high electron mobility transistor (HEMT) device (102), in accordance with an embodiment of the present disclosure.
[0028] FIGs. 1B-1C illustrate exemplary views (100B, 100C) of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0029] FIG. 1D illustrates a schematic representation (100D) of a process of fabrication of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0030] FIG. 2A illustrates an exemplary device characteristics (200A) with thermal activation, in accordance with an embodiment of the present disclosure.
[0031] FIGs. 2B and 2C illustrate exemplary plots (200B, 200C) depicting cross sections of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0032] FIGs. 3A to 3C illustrate exemplary plots (300A, 300B, 300C) of p-GaN equilibrium depletion width as a function of p-GaN doping and metal work function, in accordance with embodiments of the present disclosure.
[0033] FIGs. 4A and 4B illustrate exemplary plots (400A, 400B) depicting impact of AlGaN barrier leakage on the HEMT device (102) characteristics using a well-calibrated computational framework, in accordance with embodiments of the present disclosure.
[0034] FIGs. 5A and 5B illustrate exemplary plots (500A, 500B) depicting surface potential across the p-GaN/AlGaN interface, in accordance with embodiments of the present disclosure.
[0035] FIGs. 6A to 6D illustrate exemplary plots (600A, 600B, 600C, 600D) depicting variations in AlGaN surface potential and 2DEG formation across gate voltage, in accordance with embodiments of the present disclosure.
[0036] FIGs. 7A and 7B illustrate exemplary plots (700A, 700B) depicting a turn-on process of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0037] FIGs. 8A to 8D illustrate exemplary plots (800A, 800B, 800C, 800D) depicting transfer characteristics of HEMT devices working in the depletion extension mode, in accordance with embodiments of the present disclosure.
[0038] FIGs. 9A to 9D illustrate schematic representations (900A, 900B, 900C, 900D) of the AlTiO/p-GaN integrated gate stack with varying surface properties, in accordance with embodiments of the present disclosure.
[0039] FIGs. 10A to 10D illustrate exemplary plots (1000A, 1000B, 1000C, 1000D) of the AlTiO/p-GaN integrated gate stack, in accordance with embodiments of the present disclosure.
[0040] FIGs. 11A to 11C illustrate exemplary plots (1100A, 1100B, 1100C) depicting transfer characteristics of the HEMT devices with non-leaky and leaky dielectric, in accordance with embodiments of the present disclosure.
[0041] FIGs. 12A to 12C illustrate exemplary plots (1200A, 1200B, 1200C) depicting gate characteristics of the HEMT devices, in accordance with embodiments of the present disclosure.
[0042] FIGs. 13A to 13B illustrate exemplary plots (1300A, 1300B) depicting energy bandgap of the gate dielectric, in accordance with embodiments of the present disclosure.
[0043] FIGs. 14A to 14B illustrate exemplary plots (1400A, 1400B) depicting electron affinity of the gate dielectric, in accordance with embodiments of the present disclosure.
[0044] FIGs. 15A to 15B illustrate schematic representations (1500A, 1500B) depicting an inverse relationship between the gate dielectric capacitance and device’s Vth, in accordance with embodiments of the present disclosure.
[0045] FIGs. 16A to 16B illustrate exemplary plots (1600A, 1600B) depicting comparison of the HEMT device (102) with conventional devices, in accordance with embodiments of the present disclosure.
[0046] FIGs. 17A to 17B illustrate exemplary schematic representations (1700A, 1700B) depicting gate metal deposition on the HEMT device (102), in accordance with embodiments of the present disclosure.
[0047] FIGs. 18A to 18G illustrate exemplary schematic representations (1800A, 1800B, 1800C, 1800D, 1800E, 1800F, 1800G) depicting performance characteristics of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0048] FIGs. 19A to 19B illustrate exemplary schematic representations (1900A, 1900B) depicting crossection STEM of the metal p-GaN gate stack with varying Ti thicknesses, in accordance with embodiments of the present disclosure.
[0049] FIGs. 20A to 20B illustrate exemplary plots (2000A, 2000B) depicting atomic fractions of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0050] FIG. 21A illustrates exemplary plot (2100A) depicting variation in the sidewall angles of the sidewall slope to provide gate control, in accordance with an embodiment of the present disclosure.
[0051] FIG. 22A illustrates exemplary plot (2200A) depicting electric field variation along the sidewalls of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0052] FIG. 23A illustrates exemplary plot (2300A) depicting TCAD simulated data gate leakage characteristics, in accordance with an embodiment of the present disclosure.
[0053] FIGs. 24A to 24B illustrate exemplary schematic representations (2400A, 2400B) depicting fabrication of the HEMT device (102) and the HEMT device (102) structure, in accordance with embodiments of the present disclosure.
[0054] FIGs. 25A to 25C illustrate exemplary plots (2500A, 2500B, 2500C) depicting electric field variations of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0055] FIGs. 26A to 26C illustrate exemplary plots (2600A, 2600B, 2600C) depicting performance of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0056] FIGs. 27A to 27C illustrate exemplary plots (2700A, 2700B, 2700C) depicting O2 flow rate variation results with the SiOx passivation stoichiometry, in accordance with embodiments of the present disclosure.
[0057] FIGs. 28A to 28C illustrate exemplary plots (2800A, 2800B, 2800C) depicting performance characteristics of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0058] FIGs. 29A to 29B illustrate exemplary plots (2900A, 2900B) depicting non-stoichiometric single layer passivation of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0059] FIG. 30A illustrates an exemplary block diagram (3000A) of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0060] FIG. 31A illustrates an exemplary method flow diagram (3100A) of proposed HEMT device (102), in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION
[0061] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[0062] The present disclosure provides a high electron mobility transistor (HEMT) device. The device may include a thinner p-gallium nitride (p-GaN) and may further include Aluminium Titanium Oxide (AlTiO) integration on thinner p-GaN to enable improved gate overdrive and higher VTH. Low work function gate metal stack may suppress gate leakage and improve gate stability. Furthermore, the device may include a p-GaN sidewall slope, and a steep profile to improve gate control, ION and gate stability. The silicon dioxide (SiO2) sidewall passivation with optimum charge profile (O2 flow rate ~ 7.2sccm), and access region SiO2 /AlTiO passivation corresponding to 9.8cm may provide improved VBD-RON performance. Some variants of Silicon Dioxide (SiO2) /AlTiO passivation may include AlTiO/ SiO2 stacking, SiO2 /AlTiO/Al2O3, graded charge profile of SiO2 with thickness in different variants; and Graded Al percentage of AlTiO with thickness in different variants.
[0063] The HEMT device includes a p-GaN gate stack and surface passivation to push the performance, stability, and threshold voltage (VTH) beyond earlier disclosed limits. A p-AlTiO/thin p-GaN gate stack is demonstrated, which resulted in record high VTH (4.2 V) with record high gate driving/breakdown (13.6 V). In addition, a technique to tune gate metal work function is demonstrated resulting in increased VTH and reduced leakage when work function was reduced. Furthermore, steeper p-GaN sidewall profiles enhanced the gate stability, achieving a record gate overdrive voltage (11.4V) while also improving RON and gate control. Unique gate sidewall passivation is proposed, which demonstrated gate leakage reduction by ~2 orders of magnitude. Additional passivation schemes to improve the breakdown and dynamic RON have been demonstrated. Finally, based on the findings, an integration scheme is proposed to maximize device performance and gate stability.
[0064] FIG. 1A illustrates an exemplary schematic sectional representation (100A) of a high electron mobility transistor (HEMT) device (102), in accordance with an embodiment of the present disclosure.
[0065] As illustrated in FIG. 1A, in an embodiment, the HEMT device (102) (also known as the device (102) throughout the disclosure) may include a gate structure (104) with a p-gallium nitride (p-GaN) structure (106) disposed over a heterojunction structure. The heterojunction structure comprises a source (108), a drain (110), and the gate structure (104). A sidewall slope (114) may be configured with the p-GaN structure (106). The sidewall slope (114) may exhibit a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability. The gate structure (104) may include a p-type Aluminium Titanium Oxide (AlTiO) layer (116) deposited on the p-GaN structure (106). The AlTiO layer (116) may include a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure (106). The gate structure (104) may include a metal layer (118) disposed on an the p-type AlTiO layer (116). The metal layer (118) may include a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
[0066] In an embodiment, the passivation layer (120-1, 120-2, 120-3) may be disposed on the heterojunction structure which abuts the gate structure (104). The passivation layer (120-1, 120-2, 120-3) may include a layer 1 (120-1) with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 (120-2) with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 (120-3) with an alloyed p-type AlXTi1-XO. The layer 1 may abut the p-GaN structure, the layer 2 may be disposed on AlGaN barrier layer (122), which forms a part of the heterojunction structure, and the layer 3 (120-3) may be disposed on the layer 1 (120-1) and the layer 2 (120-2).
[0067] FIGs. 1B-1C illustrate exemplary views (100B, 100C) of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0068] As illustrated in FIGs 1B-1C, in an embodiment, the HEMT device (102) is shown with different layers.
[0069] FIG. 1D illustrates a schematic representation (100D) of a process of fabrication of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0070] Referring to FIG 1D, in an embodiment, the HEMT device (102) may be fabricated on a substrate. In some embodiments, the substrate may be a commercial grade 600V E-mode GaN-on-Si wafer. To optimize and probe the factors governing VTH, gate overdrive, and leakage, the following design parameters are explored- (a) gate stack, (b) gate metal, and (c) surface passivation. The fabrication of the HEMT device (102) may begin with the blanket atomic layer etching of p- GaN using O2/BCl3 plasma. This may be followed by annealing in N2 ambient at 800°C for about 10min. By annealing, (a) damage due to etching may be recovered, and (b) Mg activation in p-GaN may be enhanced. Subsequently, AlTiO may be deposited using thermal atomic layer deposition with a well-optimized process flow, followed by Ti/TiN based gate metal deposition, self-aligned p-GaN etching, MESA isolation, source/drain ohmic contact formation, and finally SiO2/AlTiO passivation.
[0071] FIG. 2A illustrates an exemplary device characteristics (200A) with thermal activation, in accordance with an embodiment of the present disclosure.
[0072] As illustrated in FIG. 2A, in an embodiment, comparison of device characteristics for devices is shown with thermal activation. Conductivity measurements using special test structures (inset) with 10 µm spaced metal/p-GaN junctions confirmed improved Mg activation in annealed samples. This results in higher conductivity and significantly increased gate leakage with comparable VTH. The figure also compares devices with varying p-GaN thickness, showing comparable VTH and ON-state leakages. Increased gate leakage is attributed to the thinner metal/p-GaN barrier, causing higher tunneling current from the gate.
[0073] FIGs. 2B and 2C illustrate exemplary plots (200B, 200C) depicting cross sections of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0074] As illustrated in FIGs. 2B, in an embodiment, STEM image of the HEMT device (102) cross-section is shown. FIG. 2C shows schematic of leakage routes in the p-GaN gate stack, including through the gate/pGaN, p-GaN sidewall, and AlGaN barrier. Factors influencing leakage are metal choice, p-GaN/metal interface quality, sidewall quality, passivation nature, barrier Al content and traps, p-GaN doping and thickness, and so on. These leakage paths can alter gate-to-channel coupling and affect the turn-on process
[0075] FIGs. 3A to 3C illustrate exemplary plots (300A, 300B, 300C) of p-GaN equilibrium depletion width as a function of p-GaN doping and metal work function, in accordance with embodiments of the present disclosure.
[0076] As illustrated in FIGs. 3A, in an embodiment, p-GaN equilibrium depletion width as a function of p-GaN doping and metal work function. For a given p-GaN thickness and metal work function,p-GaN may be either fully depleted or partially depleted. FIG. 3B represents p-GaN depletion scenarios, where the p-GAaN is fully depleted for low doping and partially depleted for high doping. FIG. 3C represents band diagram of metal/p-GaN gate stack showing potential variations and charge flow due to leakage routes, with hole supply from the gate and p-GaN depletion towards the p-GaN/AlGaN interface, where holes may accumulate or leak through the barrier via trap-assisted recombination. The schematic forms the base for model developed given above.
[0077] FIGs. 4A and 4B illustrate exemplary plots (400A, 400B) depicting impact of AlGaN barrier leakage on the HEMT device (102) characteristics using a well-calibrated computational framework, in accordance with embodiments of the present disclosure.
[0078] As illustrated in FIGs. 4A-4B, in an embodiment, impact of AlGaN barrier leakage on device characteristics using a well-calibrated computational framework is shown. FIGs. 4A-4B illustrate that the devices with low p-GaN doping show comparable VTH with suppressed leakage. For higher p-GaN doping, devices show similar VTH for non-leaky barriers, but higher VTH with leaky barriers, however with degraded subthreshold properties
[0079] FIGs. 5A and 5B illustrate exemplary plots (500A, 500B) depicting surface potential across the p-GaN/AlGaN interface, in accordance with embodiments of the present disclosure.
[0080] In an embodiment, FIG. 5A shows temporal change in AlGaN surface potential with incoming hole supply, showing accelerated accumulation at the p-GaN/AlGaN interface and subsequent 2DEG formation. FIG. 5B shows contrast with a leaky barrier, exhibiting no hole buildup or surface potential variation, preventing 2DEG formation
[0081] FIGs. 6A to 6D illustrate exemplary plots (600A, 600B, 600C, 600D) depicting variations in AlGaN surface potential and 2DEG formation across gate voltage, in accordance with embodiments of the present disclosure.
[0082] In an embodiment, FIG. 6A shows comparison of AlGaN surface potential and 2DEG formation across gate voltage in fully and partially depleted modes, highlighting predictive accuracy of the model. Band diagrams along the gate stack in FIG. 6B represent direct control over the AlGaN surface potential in the fully depleted case. FIG. 6C shows a parallel shift of the bands due to hole accumulation, resulting in ?Vg ~ ?Vfi, which maintains a consistent depletion. In the h-depletion mode, the depletion extends due to minimal changes in ?Vfi. When the depletion reaches the p-GaN/AlGaN interface, the HEMT device (102) begins its turn-on process.
[0083] FIGs. 7A and 7B illustrate exemplary plots (700A, 700B) depicting a turn-on process of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0084] As illustrated in FIG. 7A-7B, in an embodiment, the HEMT device's (102) turn-on process varies with incoming hole supply, showing that suppressed hole injection can enhance VTH without sacrificing subthreshold performance. However, higher p-GaN doping may limit VTH potential due to increased hole injection from the gate, indicating that inserting a gate dielectric could optimize VTH.
[0085] FIGs. 8A to 8D illustrate exemplary plots (800A, 800B, 800C, 800D) depicting transfer characteristics of HEMT devices working in the depletion extension mode, in accordance with embodiments of the present disclosure.
[0086] In an embodiment, FIG.8A shows comparison of AlGaN surface potential and 2DEG formation across gate voltage in fully and partially depleted modes, highlighting predictive accuracy of the model. Band diagrams along the gate stack in FIG. 8B show direct control over the AlGaN surface potential in the fully depleted case. FIG. 8C shows a parallel shift of the bands due to hole accumulation, resulting in ?Vg ~ ?Vfi, which maintains a consistent depletion. Further, FIG. 8C shows, for the h-depletion mode, the depletion extends due to minimal changes in ?Vfi. When the depletion reaches the p-GaN/AlGaN interface, the device begins its turn-on process.
[0087] FIGs. 9A to 9D illustrate schematic representations (900A, 900B, 900C, 900D) of the AlTiO/p-GaN integrated gate stack with varying surface properties, in accordance with embodiments of the present disclosure.
[0088] As illustrated in FIG. 9A, in an embodiment, transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN activated doping. FIG. 9B shows equilibrium band diagrams showing s higher doping shrinks the p-GaN depletion width, therefore a complete p-GaN depletion is delayed to turn on the device giving high Vth.
[0089] As illustrated in FIG. 9C, in an embodiment, shows transfer characteristics of the devices working in the depletion extension mode showing Vth dependence on the p-GaN thickness. FIG. 9D shows equilibrium band diagrams showing higher ease of thinner p-GaN for complete depletion to turn on the device, therefore giving lower Vth for thinner p-GaN devices.
[0090] FIGs. 10A to 10D illustrate exemplary plots (1000A, 1000B, 1000C, 1000D) of the AlTiO/p-GaN integrated gate stack, in accordance with embodiments of the present disclosure.
[0091] In an embodiment, FIG. 10A shows AlTiO composition with VBE and bandgap values from UPS and UV-Vis spectroscopy for calibrated computations. FIG. 10B shows Process A devices with a moderate VTH shift, Process B devices show a significantly higher VTH with similar ON/OFF ratios despite being integrated on thinner p-GaN. FIG. 10C shows Process C devices have a lower VTH due to increased gate leakage, indicating hole accumulation mode, in contrast to Process B, which operates in hole depletion mode with suppressed leakage. FIG. 10D shows comparison of gate leakage and VTH shows Process B devices with maximum VTH and suppressed leakage.
[0092] FIGs. 11A to 11C illustrate exemplary plots (1100A, 1100B, 1100C) depicting transfer characteristics of the HEMT devices with non-leaky and leaky dielectric, in accordance with embodiments of the present disclosure.
[0093] As illustrated, in an embodiment, FIG. 11A shows transfer characteristics of the HEMT devices with non-leaky and leaky dielctric. It can be observed that the devices with a leaky dielctric show a low Vth, whereas devices with non-leaky dielectric show a higher Vth. FIG. 11B shows that devices turns on through hole accumulation mode in a leaky dielectric case, where FIG. 11C shows that devices turns on in the hole depletion mode in a non-leaky dielectric case. These results show the relationship between the leakage behaviour and the Vth of the devices.
[0094] FIGs. 12A to 12C illustrate exemplary plots (1200A, 1200B, 1200C) depicting gate characteristics of the HEMT devices, in accordance with embodiments of the present disclosure.
[0095] As illustrated, in an embodiment, FIG. 12A, gate capacitance measurements reveal a difference in VTH between devices from processes A and B, despite similar ON-state capacitance. The thicker p-GaN in process A suggests lower capacitance, indicating a possible alteration in the AlTiO dielectric constant due to varying crystalline quality, more disorder results in a lower dielectric constant (K) and delayed depletion as shown in FIG. 12B. FIG. 12C shows device characteristics with consistent VTH aligned with model extracted K-values.
[0096] FIGs. 13A to 13B illustrate exemplary plots (1300A, 1300B) depicting energy bandgap of the gate dielectric, in accordance with embodiments of the present disclosure.
[0097] As illustrated, in an embodiment, FIG. 13A shows Vth dependence on the energy bandgap of the gate dielectric showing higher Vth for wider bandgap dielectric. FIG. 13B shows that initial band diagram with increase is Vth can be attributed to the delayed p-GaN depletion effect.
[0098] FIGs. 14A to 14B illustrate exemplary plots (1400A, 1400B) depicting electron affinity of the gate dielectric, in accordance with embodiments of the present disclosure.
[0099] As illustrated, in an embodiment, FIG. 14A shows Vth dependence on the electron affinity of the gate dielectric showing higher Vth for dielectric with high electron affinity. FIG. 14B shows initial band diagram with increase is Vth can be attributed to the delayed p-GaN depletion effect.
[0100] FIGs. 15A to 15B illustrate schematic representations (1500A, 1500B) depicting an inverse relationship between the gate dielectric capacitance and device’s Vth, in accordance with embodiments of the present disclosure.
[0101] As illustrated in FIGs. 15A-15B, in an embodiment, Vth relationship of proposed high Vth devices is shown as a function of Vth of ohmic device. The equation shows an inverse relationship between gate dielectric capacitance and device’s Vth.
[0102] FIGs. 16A to 16B illustrate exemplary plots (1600A, 1600B) depicting comparison of the HEMT device (102) with conventional devices, in accordance with embodiments of the present disclosure.
[0103] As illustrated in FIG. 16A, in an embodiment, dynamic instability in VTH due to 6V DC stress shows that AlTiO/pGaN samples (A, B) have lower ?VTH than those without AlTiO (as shown in FIG. 16B). Further, comparison of VG, Max versus VTH in this work with the state-of-the-art p-GaN gated HEMTs shows superior gate performance of demonstrated devices.
[0104] FIGs. 17A to 17B illustrate exemplary schematic representations (1700A, 1700B) depicting gate metal deposition on the HEMT device (102), in accordance with embodiments of the present disclosure.
[0105] In an embodiment, FIGs. 17A to 17B provide schematic representations (1700A, 1700B) depicting gate metal deposition on the HEMT device (102).
[0106] FIGs. 18A to 18F illustrate exemplary schematic representations (1800A, 1800B, 1800C, 1800D, 1800E, 1800F) depicting performance characteristics of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0107] In an embodiment, FIGs. 18A to 18F schematic representations (1800A, 1800B, 1800C, 1800D, 1800E, 1800F) depicting performance characteristics of the HEMT device (102) is illustrated.
[0108] FIGs. 19A to 19B illustrate exemplary schematic representations (1900A, 1900B) depicting crossection STEM of the metal p-GaN gate stack with varying Ti thicknesses, in accordance with embodiments of the present disclosure.
[0109] As illustrated, FIGs 19A to 19B show, crossection STEM of the metal p-GaN gate stack with varying Ti thickness, showing a higher interdiffusion at the p-GaN/Ti-TiN interface, for thicker Ti. STEM EDX compositional analysis shows a more Ga out diffusion at the interface for thicker Ti films.
[0110] FIGs. 20A to 20B illustrate exemplary plots (2000A, 2000B) depicting atomic fractions of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0111] As illustrated, in an embodiment, FIGs 20A to 20B show Ga vacancies below the contact may act as shallow acceptors, and the Schottky barrier height (SBH) may be decreased, thereby increasing the gate leakage. Also, Ga consumption at the interface results in a thinner p-GaN; which can therefore lower the Vth of the device.
[0112] FIG. 21A illustrates exemplary plot (2100A) depicting variation in the sidewall angles of the sidewall slope to provide gate control, in accordance with an embodiment of the present disclosure.
[0113] As illustrated, in an embodiment, FIG. 21A shows variation in the sidewall angles of the sidewall slope to provide gate control.
[0114] FIG. 22A illustrates exemplary plot (2200A) depicting electric field variation along the sidewalls of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0115] As illustrated, in an embodiment, FIG. 22A shows electric field variation along the sidewalls of the HEMT device (102).
[0116] FIG. 23A illustrates exemplary plot (2300A) depicting TCAD simulated data gate leakage characteristics, in accordance with an embodiment of the present disclosure.
[0117] As illustrated, in an embodiment, FIG. 23A shows TCAD simulated data gate leakage characteristics. This indicates increase in gate leakage as the p-GaN sidewall slope decreases.
[0118] FIGs. 24A to 24B illustrate exemplary schematic representations (2400A, 2400B) depicting fabrication of the HEMT device (102) and the HEMT device (102) structure, in accordance with embodiments of the present disclosure.
[0119] As illustrated, in an embodiment, FIGs. 24A to 24B show schematic representations (2400A, 2400B) depicting fabrication of the HEMT device (102) and the HEMT device (102) structure.
[0120] FIGs. 25A to 25C illustrate exemplary plots (2500A, 2500B, 2500C) depicting electric field variations of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0121] As illustrated, in an embodiment, FIGs. 25A to 25C show electric field variations of the HEMT device (102).
[0122] FIGs. 26A to 26C illustrate exemplary plots (2600A, 2600B, 2600C) depicting performance of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0123] As illustrated, in an embodiment, FIGs. 26A to 26C show performance of the HEMT device (102).
[0124] FIGs. 27A to 27C illustrate exemplary plots (2700A, 2700B, 2700C) depicting O2 flow rate variation results with the SiOx passivation stoichiometry, in accordance with embodiments of the present disclosure.
[0125] As illustrated, in an embodiment, FIGs. 27A to 27C show O2 flow rate variation results in the SiOx passivation stoichiometry, this was confirmed through XPS analysis. The FIGs. 27A to 27C show that O$_2$ flow rates of 4.8 sccm resulted in non-stoichiometric SiO1.37 and 7.2 and 9.8 sccm resulted into close to the stoichiometric (S) SiO1.96 and SiO1.98 layers, respectively.
[0126] FIGs. 28A to 28C illustrate exemplary plots (2800A, 2800B, 2800C) depicting performance characteristics of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0127] As illustrated, in an embodiment, FIGs. 28A to 28C show performance characteristics of the HEMT device (102).
[0128] FIGs. 29A to 29B illustrate exemplary plots (2900A, 2900B) depicting non-stoichiometric single layer passivation of the HEMT device (102), in accordance with embodiments of the present disclosure.
[0129] As illustrated, in an embodiment, FIGs. 29A to 29B show non-stoichiometric single layer passivation is able to suppress dynamic Ron. AlTiO integrated on stoichiometric passivation may also result in the improved dynamic Ron.
[0130] FIG. 30A illustrates an exemplary block diagram (3000A) of the HEMT device (102), in accordance with an embodiment of the present disclosure.
[0131] As illustrated, in an embodiment, FIG. 30A shows the block diagram of the HEMT device (102). The HEMT device (102) may include a gate structure with a p-gallium nitride (p-GaN) structure disposed over a heterojunction structure. The heterojunction structure comprises a source, a drain, and the gate structure. A sidewall slope may be configured with the p-GaN structure. The sidewall slope may exhibit a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability. The gate structure may include a p-type Aluminium Titanium Oxide (AlTiO) layer deposited on the p-GaN structure. The AlTiO layer may include a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure. The gate structure may include a metal layer disposed on an the p-type AlTiO layer. The metal layer may include a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
[0132] In an embodiment, a passivation layer may be disposed on the heterojunction structure which abuts the gate structure. The passivation layer may include a layer 1 with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 with an alloyed p-type AlXTi1-XO. The layer 1 may abut the p-GaN structure, the layer 2 may be disposed on a AlGaN barrier layer, which forms a part of the heterojunction structure, and the layer 3 may be disposed on the layer 1 and the layer 2.
[0133] FIG. 31A illustrates an exemplary method flow diagram (3100A) of proposed HEMT device (102), in accordance with an embodiment of the present disclosure.
[0134] As illustrated in FIG. 31A, the method flow diagram (3100) includes the following steps:
[0135] At step 3102: The method may include disposing a gate structure with a p-gallium nitride structure disposed over a heterojunction structure and configuring a sidewall slope is configured with the p-GaN structure.
[0136] At step 3102: The method may include depositing, a p-type Aluminium Titanium Oxide (AlTiO) layer on the p-GaN structure.
[0137] At step 3104: The method may include disposing, a metal layer on the p-type AlTiO layer.
At step 3104: The method may include disposing a passivation layer on the heterojunction structure which abuts the gate structure.
[0138] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[0139] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions, or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION
[0140] The present disclosure provides a HEMT device where a p-GaN gate stack and surface passivation to push the performance, stability, and threshold voltage (VTH) beyond earlier disclosed limits.
[0141] The present disclosure provides a HEMT device where p-GaN and p-dielectric (AlTiO) integration with optimum p-GaN activated doping, with a p-type nature of dielctric and optimum p-GaN and p-dielctric thicknesses and dielctric constant. The HEMT device provides suppressed leakage, higher bandgap and electron affinity to enable improved gate overdrive and higher VTH.
[0142] The present disclosure provides a low work function gate metal stack to suppress gate leakage and improve gate stability. The Ti/TiN bilayer stack with tunable Ti thickness results in tunable gate Schottky barrier height
[0143] The present disclosure provides a p-GaN sidewall slope with a steep profile that improves gate control, ION and gate stability
[0144] The present disclosure provides SiO2 sidewall passivation with optimum charge profile (O2 flow rate ~ 7.2sccm), which corresponds towards stoichiometric passivation.
[0145] The present disclosure provides access region SiO2/AlTiO passivation corresponding to 9.8sccm for improved VBD-RON performance and dynamic RON performance.
,CLAIMS:1. A High Electron Mobility Transistor (HEMT) device (102) comprising:
a gate structure (104) comprising a p-gallium nitride (p-GaN) structure (106) disposed over a heterojunction structure, wherein a sidewall slope (114) is configured with the p-GaN structure (106);
the gate structure (104) comprising a p-type Aluminium Titanium Oxide (AlTiO) layer (116) deposited on the p-GaN structure (106);
the gate structure (104) comprising a metal layer (118) disposed on an the p-type AlTiO layer (116); and
a passivation layer (120-1, 120-2, 120-3) disposed on the heterojunction structure and abuts the gate structure (104).
2. The HEMT device (102) as claimed in claim 1, wherein the metal layer (118) comprises a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
3. The HEMT device (102) as claimed in claim 1, wherein the passivation layer (120-1, 120-2, 120-3) comprises of a layer 1 (120-1) with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 (120-2) with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 (120-3) with an alloyed p-type AlXTi1-XO.
4. The HEMT device (102) as claimed in claim 3, wherein the layer 1 (120-1) abuts the p-GaN structure, the layer 2 (120-2) is disposed on a AlGaN barrier layer (122), which forms a part of the heterojunction structure, and the layer 3 (120-3) is disposed on the layer 1 (120-1) and the layer 2 (120-2).
5. The HEMT device (102) as claimed in claim 1, wherein the sidewall slope (114) exhibits a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability.
6. The HEMT device (102) as claimed in claim 1, wherein the AlTiO layer (116) comprises a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure (106).
7. The HEMT device (102) as claimed in claim 1, wherein the heterojunction structure comprises a source (108), a drain (110), and the gate structure (104).
8. A method (3100) for fabricating a HEMT device, the method comprising:
disposing (3102) a gate structure (104) comprising a p-gallium nitride structure (106) disposed over a heterojunction structure and configuring a sidewall slope (114) is configured with the p-GaN structure (106);
depositing (3104), a p-type Aluminium Titanium Oxide (AlTiO) layer (116) on the p-GaN structure (106);
disposing (3106), a metal layer (118) on the p-type AlTiO layer (116); and
disposing (3108) a passivation layer (120-1, 120-2, 120-3) on the heterojunction structure which abuts the gate structure (104).
9. The method (3100) as claimed in claim 7, comprising by the metal layer (118), a low work function metal or one or more metal stacks with any or a combination of Titanium/Titanium Nitride (Ti/TiN), Ta, Sc, W, and Au.
10. The method (3100) as claimed in claim 7, comprising by the passivation layer (120-1, 120-2, 120-3), a layer 1 (120-1) with a stoichiometric Silicon Dioxide (SiOx) or a SiNX sidewall passivation, a layer 2 (120-2) with a non-stoichiometric Si-rich SiOx or SiNX passivation, and a layer 3 (120-3) with an alloyed p-type AlXTi1-XO.
11. The method (3100) as claimed in claim 9, the layer 1 abutt the p-GaN structure (106), the layer 2 (120-2) is disposed on a AlGaN barrier layer (122), which forms a part of the heterojunction structure, and the layer 3 (120-3) is disposed on the layer 1 (120-1) and the layer 2 (120-2).
12. The method (3100) as claimed in claim 7, comprising exhibiting, by the sidewall slope (114), a slanted configuration with one or more sidewall angles to suppress gate leakage, provide gate control, and stability.
13. The method (3100) as claimed in claim 7, comprising by the p-type AlTiO layer (116), a p-type semiconductor or a p-type oxide, in crystalline or amorphous form, which is deposited on the p-GaN structure (106).