F0RM2
THE PATENTS ACT, 1970
(39 of 1970)
&
The Patents Rules, 2003
COMPLETE SPECIFICATION
(See section 10; rule 13)
1. Title of the invention:
METHOD TO DETECT CT FAILURE AND BLOCKING OVERCURRENT PROTECTION ELEMENTS
2. Applicant(s):
(a) NAME : LARSEN & TOUBRO LIMITED
(b) NATIONALITY : An Indian Company
(c) ADDRESS : L & T House, Ballard Estate, Mumbai 400 001, State
of Maharashtra, India
3. PREAMBLE TO THE DESCRIPTION
The following specification particularly describes the invention and the manner in which it is to be performed:

TECHNICAL FIELD OF THE INVENTION
This invention relates generally to a method of circuit protection and more particularly, to a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions.
BACKGROUND AND THE PRIOR ART
In a power system, protection relay plays an important role for proper and uninterrupted functioning of the healthy section of the system. The main objective of the protection relay is detection and tripping/blocking of the breaker, depending upon the application, in order to isolate the faulty section of the system from the
healthy part.
The intent of CT supervision feature is to detect if there is any problem in current transformer secondary circuits. It mainly deals with the current circuit supervision. Some of the prior arts in the field of invention are as follows:
JP2005051860 (A) provide a protection relay system for detecting disconnection of a current transformer, capable of avoiding misdetection where CT disconnection is found even though no CT remaining circuit nor CT tertiary coil circuit is disconnected. The system comprises a ground fault accident detecting means which detects a single line ground fault accident when an electrical quantity is inputted from a power system which is to be protected, a current change amount detecting means which detects that the change amount in the current of each phase of a current transformer CT circuit set to be protected is equal to or higher than a predetermined set value, a current small detecting means which detects that the zero-phase current flowing a tertiary coil circuit or a remaining circuit of the current transformer is equal to or smaller than the predetermined set value, and an operation time delay means which generates an

output when the output of the current small detecting means is inputted and the input signal continues for a predetermined set period or longer. A current transformer circuit failure detecting means decides a failure of the current transformer circuit if all outputs from the earth fault accident detecting means, the operation time delay means, and the current change amount detecting means are established.
CN1578038 (A) provides a protective relay to prevent unnecessary operations of a differential protective relay by controlling the operation output of a protective device by performing failure detection at a high speed if CT circuit failure occurs at ordinary operation. This protective relay device protects a protection target such as transmission line or a bus-bar by inputting secondary current information of CT installed on each terminal and using a current differential type, and comprises circuits to for detecting balancing of three-phase current for each terminal; circuits for detecting imbalance of three-phase current for each terminal; a circuit for detecting any other event than the ordinary operation of the system; and difference current detection circuit for detecting that a vector sum of respective terminal currents for each phase is at least a predetermined value.; If balancing of the three-phase current of at least one of the respective terminals is detected, imbalance of the three-phase current of at least one of the respective terminals is detected, any other event than ordinary operation of the system is not detected in the respective terminals, and if it is detected that the vector sum of the respective terminal currents is at least the predetermined value, the CT secondary circuit is determined as being failed.
JP2001103654 (A) provide a bus protective relay which can surely detect the disconnection of a related circuit, including a CT(current transformer) and maintains its protective function as much as possible, even when the CT becomes abnormal. A bus protective relay is provided with a ground fault detecting means 101, which detects a one-line ground fault from the quantity of electricity of a power system, a small-current detecting means which detects that the current of

the remaining circuit or tertiary circuit of a CT installed to a transmission line, bus connecting section, etc., connected to a bus is a preset current value or smaller, and a current variation detecting means which detects that the variation of the each-phase current of the CT is a preset current variation or larger. The relay is also provided with a CT circuit failure detecting means, which detects the failure of a CT circuit including the CT and its related components by using the outputs of the detecting means 101, 102, and 103 and an output control means which controls the output for breaking a circuit breaker installed to the transmission line, bus connecting section, etc., connected to the bus upon receiving information on the failure of a CT circuit detected by the detecting means.
JP2000224755 (A) provide means to prevent generation of malfunction caused by saturation in a current transformer due to an external trouble, by detecting a maximum value of the amount of restraint among past samplings which were stored, and calculating the current sensitivity of heavy-current area properties according to the amplitude of the amount of restraint. A restraint amount detecting means calculates the amount of restraint, which is stored in a data memory. Respective data are read from a prescribed data memory which has stored the values of (n) samplings, and a maximum amount of restraint is detected by a maximum restraint amount detecting means. A current sensitivity calculating means calculates the current sensitivity of heavy-current area properties according to the amplitude of the amount of restraint. It is thus possible to prevent a current differential protection relay from making an unnecessary response to the occurrence of distortion in a light-current area by changing the current sensitivity calculated from the amplitude of the amount of restraint, even if a waveform distortion occurs which is caused by saturation in a current transformer(CT) due to an external failure.
JP9308081 (A) prevent erroneous operation of a current differential relay due to CT saturation completely by discriminating overcurrent by means of an

overcurrent detection element, and locking the current differential relay when it is judged that proportion is lower than a threshold value by means of a percentage detection means. SOLUTION: An overcurrent detection element la discriminates generation of overcurrent if it is in excess of a threshold value. Threshold value is set to a larger value than load current running at the time of ordinary operation. A proportion detection element 1 b judges it as external failure if proportion is in excess of a threshold value and it as internal failure if the proportion is less than the threshold value. External failure is judged by using the proportion detection element lb which detects the proportion of a sum of the magnitude of differential current and those of respective currents for the current running through a system in addition to the overcurrent detection element la; therefore, it can exactly be judged whether or not differential current flows regardless of the magnitude of current. By locking a current differential relay based on the exact judgment, it is possible to prevent erroneous operation of the current differential relay. Although the prior arts provide current circuit protection, the system and method used are complex and lacks accuracy. This invention provides for detection of CT secondary failure and blocks the overcurrent protection elements subsequent to that. This logic is used in a numerical relay as a part of LV/MV switchboards. The algorithm is used as a flow logic into the firmware build or embedded systems of the relay.
OBJECTS OF THE INVENTION
A basic object of the present invention is to overcome the disadvantages/drawbacks of the known art.
Another object of the present invention is to provide a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions.

Other object of the present invention is to provide an alarm to alert for fault
occurrence.
Yet another object of the present invention is to provide protection for Ground fault, Negative sequence overcurrent and broken conductor using a numerical
relay.
These and other advantages of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the present invention. It is not intended to identify the key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concept of the invention in a simplified form as a prelude to a more detailed description of the invention presented later.
There is provided a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions.
According to one embodiment of the present invention, there is provided a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions, said method comprising the steps of: determining the status of CT supervision feature and sending said status to a common logic unit; enabling logic operand bit to high on detection of CT failure, enabling CPU register

containing alarm value to high and blocking the operation of said overcurrent
elements.
Other embodiment of the present invention provides a method of capturing current analog samples per cycle and converting into digitized form using an analog/digital converter; said digitized samples from said analog/digital converter fed to a data acquisition and metering section; output from said data acquisition and metering section further fed to a CPU controller where the protection algorithm logic is processed; said CPU controller further generating the logic operand to block the over-current elements.
BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS
Fig 1 illustrates the transfer of signal among different elements in accordance with the present invention.
Fig 2 illustrates the method steps used in numerical relay to detect fault in accordance with the present invention.
DETAILED DESCRIPTION OF THE ACCOMPANYING DRAWINGS
The following drawings are illustrative of particular examples for enabling methods of the present invention, are descriptive of some of the methods, and are not intended to limit the scope of the invention. The drawings are not to scale (unless so stated) and are intended for use in conjunction with the explanations in the following detailed description.
Reference is first invited to Fig 1 where the transfer of signal among different units in a numerical relay is shown. It shows data acquisition and metering section, CPU controller, analog to digital converter and signal flow between them.

Fig. 2 shows the processing of protection algorithm. It shows different method steps used in detection of the fault and blocking of the overcurrent elements.
The invention is thus a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions.
DETAILED DESCRIPTION OF THE INVENTION
Accordingly the present invention provides a method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions. It provides a novel approach of detecting CT failure condition in one or multiple
phases.
This scheme is related to protection and detection of CT secondary inputs to the protection relay and blocking of the overcurrent protection elements subsequent to that. This logic will be used in a numerical relay as a part of LV/MV switchboards. The algorithm is used as flow logic into the firmware build or embedded systems of the relay. This invention elucidates the application space and concept of CT Supervision and illustrates the HMI settings and the firmware logic to be incorporated to include this feature in New Feeder Protection relay.
The logic implemented here is used for detection of CT phase failure. Figure 1 depicts the flow of the inputs /commands to the corresponding hardware of the numerical relay. There are numerous components in terms of embedded systems (hardware) in the numerical relay of which Data acquisition & metering and CPU controller are the two main sub sections of the relay.
Initially the current transformer secondary inputs i.e. phase currents which are analog inputs are fed to the Analog/Digital (A/D) converter located inside the

relay. The A/D converter captures the current analog samples per cycle and converts into digitized form. 64 samples / cycle are captured by the A/D converter. These digitized samples from A/D converter go into the Data acquisition and metering section of the numerical relay and further to the protection algorithm logic. The protection algorithm logic is installed in the CPU controller, in a coded form, which is embedded inside the relay. Through Data acquisition and metering section, the current advance to CPU controller where the protection algorithm logic is processed.
In CT supervision algorithm the CT (current transformer) condition is checked whether it is in healthy state or not. If the CT is found to be unhealthy then some of the protections, as mentioned further, are blocked and the digital output of the relay (hardware) gets the signal to issue an alarm for user interface.
In case of CT failure in one or multiple phases, faulty information about current flows in the relay leading to mal-operation of main protection functions. The supervision function must be sensitive and fast to detect the condition and prevent unwanted tripping of some sensitive protections. On detection of a CT failure condition, the protection elements which work on derived values (differential, ground fault, negative sequence overcurrent, broken conductor) are blocked. An alarm is generated.
Settings:
The following settings are required on the HMI:-
CT Supervision feature (Enabled/Disabled)
Iinhibit setting (0.1 to 20 times of In)
Ithreshold setting (0.1 to 20 times of In)
di/dt pickup (5% to 75% for a period of 1 cycle)
Time delay (10 ms to 500 seconds in steps of 10 ms)
Inputs:

Status of the CT supervision feature (enabled/disabled) Three Phase currents (la, lb, Ic)
Outputs
The logic operand bit for CT failure goes high. If the alarm is configured, the CPU register containing the alarm value also goes high. On detection of this condition the firmware blocks the operation of the following elements Ground fault, Negative sequence overcurrent and Broken conductor.
Abbreviations used:
CT: current transformer
CPU: central processing unit
HMI: human machine interface
A/D: analog to digital
In: nominal current
Io: zero sequence current
di/dt: current differentiation with respect to time
CT failure conditions in plurality of phases are detected and overcurrent protection elements are blocked using a numerical relay under certain predefined set of conditions. The status of CT supervision feature is determined and status to a common logic unit is sent, logic operand bit is enabled to high on detection of CT failure. CPU register containing alarm value is made high and the operation of said overcurrent elements is further blocked.
Numerical relay takes phase currents as input, and further calculate zero sequence current and compare said zero sequence current to find if value greater than zero set value and send comparison status to a common logic unit. Further phase

current is compared to a predefined current threshold and a current inhibit and comparison status is sent to a common logic unit, di/dt value for a period of one cycle is calculated and compared to a predefined pickup value and further sent to said common logic unit.
Further common logic unit on receiving all high input blocks said overcurrent elements. The common logic unit is AND gate logic unit. A predefined time delay is provided to a timer to monitor time period.
Although the embodiments herein are described with various specific embodiments, it will be obvious for a person skilled in the art to practice the embodiments herein with modifications. However, all such modifications are deemed to be within the scope of the claims.
It is also to be understood that the following claims are intended to cover all of the generic and specific features of the embodiments described herein and all the statements of the scope of the embodiments which as a matter of language might be said to fall there between.

WE CLAIM
1. A method to detect CT failure condition in plurality of phases and/or blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions, said method comprising the steps of: determining the status of CT supervision feature (Enable / Disable), and metering phase currents as input, computing zero sequence current and comparing said zero sequence current to find if value greater than set value, and checking whether the phase current is in-between set value of threshold and inhibit of phase current for a pre-defined period, and calculating rate of change of phase current for a pre defined cycle and comparing with pre set value; and sending said status to a common logic unit in case of satisfying above said conditions; enabling logic operand bit to high on detection of CT failure, enabling CPU register containing alarm value to high and blocking the operation of said overcurrent elements.
2. Method as claimed in claim 1 further comprising steps of capturing current analog samples per cycle and converting into digitized form using an analog/digital converter; said digitized samples from said analog/digital converter fed to a data acquisition and metering section; output from said data acquisition and metering section further fed to a CPU controller where the protection algorithm logic is processed; said CPU controller further generating the logic operand to block the over-current elements.
3. Method as claimed in claim 1 further comprising step wherein said numerical relay taking phase currents as input, calculating zero sequence current and comparing said zero sequence current to find if value greater than set value and sending comparison status to said common logic unit.

4. Method as claimed in claim 1 further comprising step of comparing said phase current to a predefined current threshold and a current inhibit and sending comparison status to said common logic unit.
5. Method as claimed in claim 1 further comprising step of calculating di/dt value for a period of one cycle, comparing said di/dt value to a predefined pickup value and sending comparison status to said common logic unit.
6. Method as claimed in claim 1 further comprising step wherein said common logic unit on receiving all high input blocks said overcurrent
elements.
7. Method as claimed in claim 1 wherein a predefined time delay is provided to a timer to monitor time period.
8. A method to detect CT failure condition in plurality of phases and blocking a plurality of overcurrent protection elements using a numerical relay under certain predefined set of conditions as herein described and illustrated with reference to the accompanying drawings.