Claims:The scope of the invention is defined by the following claims:

Claims:
1. We have invented a special hardware for frame synchronizing the satellite data.
a) This Invention has been implemented and tested using the ALTERA EPLDs. This needs RS232 settings like baud rate, parity, start bits, stop bits, are programmed as per the requirement to test tested using ALTERA EPLDs.
b) VHDL code has been developed for the generation of time in days, hours, minutes, seconds, milliseconds, and microsecond’s structure in a BCD format.
c) This time information is interfaced to the frame synchronization hardware using the UART developed within the ALTERA EPLD.

2. As per claim 1, continuously increment from the start time provided by the computer at an interval of 1micro second is maintained.

3. According to claim 1, the TCG counts the time from the computer/thumb wheel switches time and the updated time information is given to serializer for synchronization and to the HP display device for displaying purpose.

4. According to claim 1, the outputs are provided in BCD format on a 68-pin flat connector, which can be used to ping time information to the data received from the satellites.

5. As per claim 1, the satellite data which is acquired is stored in a disk whenever new systems and new software gets loaded into the serializer. , Description:Field of Invention
The present invention relates to, satellite communication. The satellites acquire information at an altitude of 600 km above earth surface. The visibility of the satellite to the ground station is only limited to 10-15 minutes. For precise processing and framing of the satellite data an accurate time reference source is needed. The time reference is generated by equipment called TIME CODE GENERATOR generates time of the year DDD:HH:MM:SS:MS:MC format. It outputs the generated time both parallel and serial forms. The serial output of the TCG is distributed to various time code translators, which converts the serial time back to parallel form .The parallel BCD time output from the TCT (time code translator) is connected to the input of the front end hardware. The FEH tags each satellite scan line/frame with the time available from the TCT at that instant. Hence it becomes necessary to generate an accurate time with a resolution at least 0.1ms.
Background of the invention
When the phase of the GPS receiver replica code matches the phase of the incoming SV code, there is maximum correlation. When the phase of the replica code is offset by more than 1 chip on either side of the incoming SV code, there is minimum correlation. This is indeed the manner in which a GPS receiver detects the SV signal when acquiring or tracking the SV signal in the code phase dimension. It is important to understand that the GPS receiver must also detect the SV in the carrier phase dimension by replicating the carrier frequency plus Doppler (and usually eventually obtains carrier phase lock with the SV signal by this means). Thus, the GPS signal acquisition and tracking process is a two-dimensional (code and carrier) signal replication process (Ward, et.al., [2006],Understanding GPS: principles and applications, pp.153-241.) .
The satellite signal acquisition and tracking, the locally reproducible ranging code plays an important role. For the newly launched Beidou-3 satellite in China, a method for implementing the B2a signal ranging code generator in FPGA is Invention. Taking the B2a ranging code of Beidou-3 satellite as the research object, the design principle of the B2a ranging code generator is explained in detail, which includes the analysis of the key modules of the Weil code and the Gold code generator. The FPGA is modularly designed to be scalable The B2a ranging code generator module, through the reserved register initialization interface, can realize the ranging code of different PRN satellites, solving the complex problem of generating arbitrary satellite number ranging codes, for the design of Beidou No. 3 navigation receiver Certain reference significance. (Zang, et.al.,[2020], In Journal of Physics: Conference Series (1650( 2), p. 022071). IOP Publishing.),
In the Invention VHDL code has been developed for the generation of time in days, hours, minutes, seconds, milliseconds, microsecond’s structure in a BCD format. Computer will provide the start time. This time will be interfaced to the developed hardware using the UART developed within the ALTERA EPLD. The time increments will be displayed on HP display devices. The developed hardware will continuously increment from the start time provided by the computer at an interval of 1micro second. This Invention has been implemented and tested using the ALTERA EPLDs. This needs RS232 settings like baud rate, parity, start bits, stop bits, etc., must be programmed as per the requirement. The hardware required for this has been implemented on the wire-warp board. From Global Positioning System (GPS) also time can be acquired and tag to the satellite data. The problem with the GPS satellite is time information will be in DDD: HH: MM: SS format that mean that the received time is up to seconds only, which has less time resolution. As NRSC satellites receive data for every 0.35 microsecond. These hardware components require time information in microseconds also. To overcome the above problem a TCG is developed to provide time information to the serializer. The time information is provided to the TCG in two ways.
Remote Mode: In this mode the present time information is provided to the TCG through PC using UART. Local Mode: In this mode using Thumb wheel switches, which are connected to the TCG, provides the time information. The TCG will count up from there and provide that time to the HP display or to the front end hardware. The TCG will count up from there and provide that time to the HP display or to the front end hardware. The QPSK modulated PCM serial stream is captured by receiving antenna system, the received data is down converted into an immediate frequency while preserving the base band data is recovered after demodulating the IF signal. An NRZ-L (non return to zero level) data and clock are recovered through the bit synchronization. The data and clock are fed to the Front End Hardware (FEH). The FEH basically detects the start of each satellite data frame and converts the serial data into parallel form and transfers over the system bus and the data is stored onto a secondary storage (Fossler, et.al., [1984], November,. In Proceedings of the 16th Annual Precise Time and Time Interval Systems and Applications Meeting (pp. 411-418)).
TCG receives time from the computer through UART (Universal Asynchronous Receiver And Transmitter) and counts from that reference time. It outputs the generated time both parallel and serial forms. The serial output of the TCG is distributed to various time code translators, which converts the serial time back to parallel form. The parallel BCD time output from the TCT (Time Code Translator) is connected to the input of the front-end hardware. The FEH tags each satellite scan line/frame with the time available from the TCT at that instant. Hence it becomes necessary to generate an accurate time with a resolution at least 0.1ms. In future it varies up to 0.01ms.
A high-speed remote sensing data receiving and processing equipment[CN101419282B]. When the equipment is used to receive data, satellite downlink serial data are converted into parallel data through serial-parallel conversion and are sent into a frame synchronous processing module for frame synchronous treatment, frame synchronization characters are searched, fault-tolerant parameters are calculated, frame synchronization signals are generated according to the frame length and the frame synchronization characters, and the frame synchronization signals and data frame are sent to a combined decode module. A time frame to be used for establishing a time correlation between the satellite system and a ground station is inserted between the transmission frames at an arbitrary timing[US7139525B2] ground station computes the time at which the data was generated in the satellite system from this time frame and establishes a time correlation with the satellite time by using only this time frame. A method for synchronization in a satellite communications system comprising at least one satellite wherein communication transmissions to the at least one satellite occur via a respective communications link with the satellite [EP3120466B1].
The objective of this invention is to utilize UART and Serializer and time information from GPS. The time information should be from days, hours, minutes, seconds, milli and micro seconds. The second objective is to write the code for days, hours, minutes, seconds, milli and microseconds in VHDL language.

Summary of the invention
The time code format starting from micro seconds to Julian day (micro-seconds, milli-seconds, seconds, minutes, hours and Julian day) were implemented in the ALTERA EPLD EPM7160SLC84-7 and the HDSP 2112 display was interfaced with it. The code for the time code generation, UART and the address generation for HDSP 2112 were written in VHDL. The simulation was carried out with the basic clock of 10 MHz. the simulation results are tested at different phases i.e., at micro-seconds, milli-seconds, seconds, minutes, hours and Julian day. The EPLD is fused using the standalone programmer, testing was carried out on wire wrap board. The output results were captured by connecting TCG to the front end hardware and compared with simulation results and found that they are matched with expected simulation. The seconds, minute’s hours and Julian days are displayed on the HDSP 2112 display. The outputs are provided in BCD format on a 68-pin flat connector, which can be used to ping time information to the data received from the satellites. The input for setting the time is taken from computer/thumb wheel switches the outputs were checked for different conditions.
Detailed description of the invention
Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word that is used to synchronize the sending and receiving units. When a word is given to the UART for Asynchronous transmissions, a bit called the "Start Bit" is added to the beginning of each word that is to be transmitted. The Start Bit is used to alert the receiver that a word of data is about to be sent, and to force the clock in the receiver into synchronization with the clock in the transmitter. These two clocks must be accurate enough to not have the frequency drift by more than 10% during the transmission of the remaining bits in the word.
After the Start Bit, the individual bits of the word of data are sent, with the Least Significant Bit (LSB) being sent first. UART frame format is as shown in figure 2. Each bit in the transmission is transmitted for exactly the same amount of time as all of the other bits, and the receiver “looks” at the wire at approximately halfway through the period assigned to each bit to determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then it will wait two seconds and then examine the value of the next bit, and so on. The sender does not know when the receiver has “looked” at the value of the bit. The sender only knows when the clock says to begin transmitting the next bit of the word. When the entire data word has been sent, the transmitter may add a Parity Bit that the transmitter generates. The receiver to perform simple error checking may use the Parity Bit. The transmitter then sends at least one Stop Bit.
When the receiver has received all of the bits in the data word, it may check for the Parity Bits (both sender and receiver must agree on whether a Parity Bit is to be used), and then the receiver looks for a Stop Bit. If the Stop Bit does not appear when it is supposed to, the UART considers the entire word to be garbled and will report a Framing Error to the host processor when the data word is read. The usual cause of a Framing Error is that the sender and receiver clocks were not running at the same speed, or that the signal was interrupted. Regardless of whether the data was received correctly or not, the UART automatically discards the Start, Parity and Stop bits. If the sender and receiver are configured identically, these bits are not passed to the host. If another word is ready for transmission, the Start Bit for the new word can be sent as soon as the Stop Bit for the previous word has been sent. Because asynchronous data will be “self synchronizes”, if there is no data to transmit, the transmission line can be idle. The computer provides the reference time to the TCG through UART.
Transmission operation is simpler since it is under the control of the transmitting system. As soon as data is deposited in the shift register after completion of the previous character, the UART hardware generates a start bit, shifts the required number of data bits out to the line, generates and appends the parity bit (if used), and appends the stop bits. Since transmission of a single character may take a long time relative to CPU speeds, the UART will maintain a flag showing busy status so that the host system does not deposit a new character for transmission until the previous one has been completed; this may also be done with an interrupt. Since full-duplex operation requires characters to be sent and received at the same time, practical UARTs use two different shift registers for transmitted characters and received characters (Fang, Y.Y. and Chen, X.J., 2011, May,. In [2011] 3rd International Workshop on Intelligent Systems and Applications (pp. 1-4). IEEE.).
All operations of the UART hardware are controlled by a clock signal, which runs at a multiple (say, 16) of the data rate - each data bit is as long as 16 clock pulses (figure 4). The receiver tests the state of the incoming signal on each clock pulse, looking for the beginning of the start bit. If the apparent start bit lasts at least one-half of the bit time, it is valid and signals the start of a new character. If not, the spurious pulse is ignored. After waiting a further bit time, the state of the line is again sampled and the resulting level clocked into a shift register. After the required number of bit periods for the character length (5 to 8 bits, typically) has elapsed, the contents of the shift register are made available (in parallel fashion) to the receiving system. The UART will set a flag indicating new data is available, and may also generate a processor interrupt to request that the host processor transfers the received data. In some common types of UART, a small first-in, first-out FIFO buffer memory is inserted between the receiver shift register and the host system interface. This allows the host processor more time to handle an interrupt from the UART and prevents loss of received data at high rates (Nanda, U. and Pattnaik, S.K., 2016, January. , In [2016] 3rd international conference on advanced computing and communication systems (ICACCS) (Vol. 1, pp. 1-5). IEEE.).
This parallel BCD Time Code Generator uses an external 10MHz crystal controlled oscillator and generates one pulse per second (1 PPS) signal. The 1 PPS signal is further used in deriving the time of the year with 1 sec resolution. Parallel BCD time generation code consists of two counters chains namely Major Chain and Minor Chain. The Minor Chain derives input from 10MHz crystal controlled oscillator. The 10MHz signal is divided by a series of decade counters connected in cascade (7 numbers) to derive a signal. The first stage is generation of microseconds, second stage is generation of millisecond; third stage is generation of second (1sec). The Major Chain consists of nine-decade counters connected in cascade. The first counter is simple decade counter that has to count units of sec. The output of second counter is mod 6 counter that counts from 0-5 it generate the output tens of second. The third counter is simple decade counter that generates units of min. The fourth counter is mod 6 counter that counts from 0-5 it generate the output tens of min. The fifth counter is decade counter who’s output is a unit of hours. In the same way the other counters perform the same operation. The hour’s counters are configured in such a way that when the time is 23:59:59, the units and tens are reset to zero as desired. Counter numbers 7, 8, 9 are configured to count from 1 to 365. The counting is enabled whenever the previous six counters overflow to all zeros.
5 claims & 4 Figures
Brief description of Drawing
In the figures which are illustrated exemplary embodiments of the invention.
Figure 1 System design flow
Figure 2 UART transmitter flow chart
Figure 3 Hardware interface of TCG
Figure 4 Hardware setup of TCG and TCT
Detailed description of the drawing
Figure 1 is the system design flow for the entire Invention work. Initially the time information is obtained from the computer. The micro seconds and milli seconds are incremented. Similarly, minutes, hours and days are incremented.
Figure 2 is the flow chart of the UART transmitter and receiver module. Initially the reset value is set to 1 and the baud rate is fixed to 9600. If the baud rate is 9600 the data is ready for transmit and stored in a temporary register, and if the baud rate is less than 9600 data is not transmitted. If the value is between 0 to 9 data is transmitted serially. If the data is equal to 9 transmitter stops the data.
Figure 3 illustrates the result of hardware interface of TCG and TCT. On the front side of PCB, 3 EPLD and IC’s and HP display units are mounted. On the back of PCB all connections are done using wire.

Figure 4 is the entire hardware setup embedded in a metal box displaying, days, hours, minutes and milliseconds and micro seconds as output results.