DESC:TECHNICAL FIELD
[1] The present disclosure relates generally to high-electron mobility transistor (HEMT) devices. In particular, the present disclosure relates to a semiconductor device incorporating a P-type Gallium Nitride-based enhancement mode high electron mobility transistor (hereinafter “p-GaN e-HEMT”) to tune gate work function and a method thereof.

BACKGROUND
[2] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[3] Normally-off High Electron Mobility Transistors (hereinafter “HEMTs”) with a p-GaN gate have garnered significant interest for their potential applications in power electronics. The metallization of the p-GaN gate electrode is a critical aspect affecting the device's electrical characteristics. The choice of metal gate remains a subject of debate in the scientific community, with studies investigating its effects on the device characteristics. It may be observed that a lower work-function metal gate (WSiN) improved the gate voltage swing and reduced gate leakage current, supported by TCAD simulations showing higher barrier height (FB) and threshold voltage (VTH) with lower leakage current for lower work-function metals. Thus, the work function of metal stacks significantly influences the electrical characteristics of normally-off HEMTs with p-GaN gate, impacting threshold voltage, gate leakage current, and gate voltage swing, thereby crucially affecting device design and optimization for diverse applications.
[4] The discussion above emphasizes the crucial role of metalwork function in determining gate performance. To optimize the gate, the metalwork function needs to be tuned, but this presents challenges, as changing the gate metal affects overall metal properties, adhesion to p-GaN, thermal stability, and process compatibility.
[5] Thus, there exists a dire need in the art, to provide a semiconductor device incorporating a P-type Gallium Nitride-based enhancement mode high electron mobility transistor (p-GaN e-HEMT) to tune gate work function and a method thereof.

OBJECTS OF INVENTION
[6] Some of the objects of the present disclosure, that at least one embodiment herein satisfies are as listed herein below.
[7] It is a general object of the present disclosure to overcome the drawbacks and limitations of the existing e-HEMT devices.
[8] It is a main object of the present disclosure to provide a P-type Gallium Nitride-based enhancement mode high electron mobility transistor to tune gate work function and a method thereof.
[9] It is an object of the present disclosure to provide e-HEMT with a gate metal stack to reduce the gate leakage.
[10] It is another object of the present disclosure to provide a single gate metal stack deposition process with the ability to modulate work function for optimizing gate performance, which is necessary.

SUMMARY
[11] Within the scope of this application, it is expressly envisaged that the various aspects, embodiments, examples, and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. Features described in connection with one embodiment are applicable to all embodiments, unless such features are incompatible.
[12] In a first aspect of the invention, a semiconductor device incorporating a P-type Gallium Nitride enhancement mode high electron mobility transistor (p-GaN e-HEMT) is disclosed. The semiconductor device comprises a gate structure with a Gallium Nitride (GaN) layer sandwiched between a barrier layer and a bi-metal layer. The device can be a High-Electron-Mobility Transistor (HEMT) based on Gallium Nitride (GaN) on Silicon (Si) technology. The GaN layer may be a p-type GaN layer, the barrier layer may be an Aluminum Gallium Nitride (AlGaN) barrier layer with a thickness of between 8-15 nanometers (nm), and the bi-metal layer may be of Titanium (Ti) and Titanium Nitride (TiN). In one embodiment,
the AlGaN layer having a thickness of between 5-30 nanometers (nm).
[13] In a second aspect of the invention, a method of fabricating a P-type Gallium Nitride-based enhancement mode- high electron mobility transistor (p-GaN e-HEMT) is disclosed. The method includes forming a GaN buffer layer on a substrate, depositing a UID GaN channel layer on the buffer layer, forming an AlN barrier layer on the channel layer, depositing an AlGaN barrier layer on the AlN barrier layer, creating a 2DEG region at the interface between the AlGaN barrier layer and the UID GaN channel layer, forming a gate structure comprising a p-GaN layer and a Ti/TiN bi-metal layer on the AlGaN barrier layer, wherein the p-GaN layer is sandwiched between the Ti/TiN bi-metal layer and the AlGaN barrier layer, depositing a SiO2 passivation layer 109 over the gate structure, and applying an Al0.5Ti0.5O passivation layer 108 over the SiO2 passivation layer 109.
[14] One should appreciate that although the present disclosure has been explained with respect to a defined set of functional modules, any other module or set of modules can be added/deleted/modified/combined, and any such changes in the architecture/construction of the proposed system are completely within the scope of the present disclosure. Each module can also be fragmented into one or more functional sub-modules, all of which are also completely within the scope of the present disclosure.
[15] Various objects, features, aspects, and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[16] The accompanying drawings, which are incorporated herein, and constitute a part of this invention, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present invention. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that the invention of such drawings includes the invention of electrical components, electronic components or circuitry commonly used to implement such components.
[17] FIGs. 1 (A-C) illustrates an exemplary schematic sectional representation of a high electron mobility transistor (HEMT) device (FIG. 1A), a schematic representation of a process of fabrication of the HEMT device (FIG. 1B), a schematic representation of the process of deposition used for depositing Ti/TiN bi-metal layer (FIG. 1C), in accordance with an exemplary embodiment of the present disclosure.
[18] FIGs. 2 (A-C) illustrates exemplary plots depicting work function extraction at the gate of the HEMT device (FIGs. 2A and 2B), an exemplary plot depicting a difference in SKPM contact potential difference between two gate stacks of different thicknesses (FIG. 2C), in accordance with an exemplary embodiment of the present disclosure.
[19] FIGs. 3 (A-D) illustrates an exemplary representation of a plot depicting I-V characteristics of the HEMT devices (FIG. 3A), an exemplary plot depicting a comparable ON/OFF ratio and a shift in VTH (FIG. 3B), and an exemplary distribution plot depicting a positive VTH shift for thinner Ti layer (FIG. 3C); and an exemplary plot depicting the distribution of gate leakage and maximum gate overdrive of the HEMT devices (FIG. 3D), in accordance with an exemplary embodiment of the present disclosure.
[20] FIGs. 4 (a-b) illustrates an exemplary representation of the cross-section STEM of the metal p-GaN gate stack with varying Ti thickness, in accordance with an exemplary embodiment of the present disclosure.
[21] FIGs. 5 (a-d) illustrates an exemplary representation of design variations of the semiconductor device, in accordance with an exemplary embodiment of the present disclosure.
[22] FIGs. 6 (a-c) illustrates an exemplary representation of design variations of the semiconductor device, in accordance with an exemplary embodiment of the present disclosure.
[23] Other objects, advantages, and novel features of the invention will become apparent from the following more detailed description of the present embodiment when taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION
[24] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such details as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[25] Accordingly, while example embodiments of the invention are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments of the present invention to the particular forms disclosed. On the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the invention. Like numbers refer to like elements throughout the description of the figures.
[26] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention. As used herein, the term “and/or,” includes any and all combinations of one or more of the associated listed items.
[27] It will be understood that when an element is referred to as being “connected,” or “coupled,” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected,” or “directly coupled,” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between,” versus “directly between,” “adjacent,” versus “directly adjacent,” etc.).
[28] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the terms “and/or” and “at least one of” include any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. If the present disclosure states a component or feature “may”, “can”, “could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.
[29] Thus, for example, it will be appreciated by those of ordinary skill in the art that the diagrams, schematics, illustrations, and the like represent conceptual views or processes illustrating systems and methods embodying this invention. The functions of the various elements shown in the figures may be provided through the use of dedicated hardware as well as hardware capable of executing associated software. Similarly, any switches shown in the figures are conceptual only. Their function may be carried out through the operation of program logic, through dedicated logic, through the interaction of program control and dedicated logic, or even manually, the particular technique being selectable by the entity implementing this invention. Those of ordinary skill in the art further understand that the exemplary hardware, software, processes, methods, and/or operating systems described herein are for illustrative purposes and, thus, are not intended to be limit the present disclosure.
[30] List of reference numerals used:
100- Semiconductor device
101- AIGaN barrier layers / Plurality of barrier layers
101-1- AlN barrier layer
102- P-type doped layer/ Gallium Nitride (GaN) layer
103- Gate structure/ Gate metal stack
103-1- Bi-metal layer/ Ti/TiN bi-metal layer/ Metal layer
104- substrate
104-1- Buffer layer
105- Channel layer
106- Source/ Source contact
107- Drain/ Drain contact
108- First passivation layer/ Al0.5Ti0.5O passivation layer
109- Second passivation layerlayer/ SiO2 passivation layer
110- Two-dimensional electron gas (2DEG) region
111- Field plate
112- Spacer
113- Drain field plate
114- Cap layer
800- Method
[31] The present disclosure provides a bilayer gate metal stack based on Ti/TiN, which exhibits distinct properties. A key finding of this disclosure may be the unique role of the Ti layer thickness in modulating the gate stack work function in e-mode AlGaN/GaN HEMTs. Notably, reducing the Ti layer thickness may lead to a decreasing trend in the work function of the gate metal stack. Additionally, the technique employed to tune the gate metal stack's work function shows its potential for achieving low work gate metal stacks in p-GaN gated HEMTs. Consequently, such gate configurations offer significant advantages, including higher threshold voltage (VTH), reduced gate leakage, and improved maximum gate overdrive. The demonstrated technique for tuning the gate metal work function therefore provides a practical means to enhance performance characteristics of e-mode AlGaN/GaN HEMTs.
[32] In a first embodiment of the present disclosure, an enhancement mode high electron mobility transistor (e-HEMT) device 100 (hereinafter the term “device”, “semiconductor device”, “e-HEMT device”, “p-GaNe-HEMT” used interchangeably) may be provided. The device 100 may include a bilayer gate metal stack with work function tuning ability. In some embodiments, the bilayer gate metal stack may include a Ti and TiN bilayer metal stack with Ti thickness variation to tune the metal stack work function. Further, in device 100, it may be possible to tune VTH with gate metal stack variation. Gate leakage suppression may be possible corresponding to lower work function gate metal stacks. Furthermore, the e-HEMT device 100 may facilitate maximizing gate performance and stability by tuning with gate metal work function.
[33] In an exemplary implementation of the first embodiment, the gate structure 103 having a bi-metal layer 103-1. The gate structure 103 is disposed on a Gallium Nitride (GaN) layer 102.
[34] In an exemplary implementation of the first embodiment, the first passivation layer 108 is made aluminium Oxide (Al0.5Ti0.5O), Silicon Oxide (SiO), Silicon Nitride (SiN), or any other alloyed oxide thereof, or any staking thereof, in crystalline or amorphous form.
[35] In an exemplary implementation of the first embodiment, a cap layer 114 formed on the aluminium Nitride (AlN) barrier layer 101 by fully extending to the source contact 106 and the drain contact 107, or only on the gate side and partially or fully extended towards gate. The cap layer 114 is made of any, or combination of Gallium Nitride (GaN), p-type or intrinsic GaN, Aluminum Oxynitride (AlON), or Aluminum Nitride (AlN).
[36] In these embodiments, the thickness of titanium (Ti) in the bi-metal layer 103-1 is adjustable. In one embodiment, the thickness of the titanium ranges between 2-50 nanometers (nm). In another embodiment, the thickness of the titanium ranges between 1 -50 naometers (nm).
[37] In these embodiments, the barrier height of the bi-metal layer 103-1 is increased and/or decreased, thereby improves characteristics of the semiconductor device 100.
[38] In these embodiments, the semiconductor device (100) further comprising any one or a combination of the first passivation layer (108) with a field plate (111), a spacer (112) and a drain field plate (113).
[39] FIG. 1A illustrates an exemplary schematic sectional representation of a high electron mobility transistor (HEMT) device 100.
[40] FIG. 1B illustrates a schematic representation 120 of the process of fabrication of the HEMT device 100.
[41] FIG. 1C illustrates a schematic representation 130 of the process of deposition used for depositing Ti/TiN bi-metal layer 103-1.
[42] Referring to FIGs. 1A to 1C, in one embodiment, the HEMT device 100 may be fabricated on a suitable substrate 104. In some examples, the substrate 104 may be a grade 600V GaN on a Si wafer. The gate metal stack may be nitride-bases. In some examples, the gate metal stack may include Ti/TiN. Further, the thickness of the titanium layer may be varied as per requirement. The metal stack may be deposited on the device 100 using a DC reactive magnetron sputtering. The chart is illustrated in FIG. 1C provides an exemplary set of parameters used for an instance of DC magnetron sputtering of the gate metal stack. For example, the sputtering source may be a 5 mm thick water-cooled solid Ti target (99.999% purity) with a diameter of about 60 mm. The target-to-substrate distance may be set at about 93 mm. Prior to the deposition, the sputtering chamber may be evacuated to a base pressure of 5×10-7mbar. To eliminate oxide layers on the target, Ti pre-sputtering may be performed in 3 consecutive sub-steps, gradually decreasing power from about 250W to about 150W, each lasting about 500 s. After the pre-sputtering process, a gettering process may be carried out by Ti sputtering on a dummy sample to remove any trace oxygen in the sputtering chamber. As a result, the pressure and oxygen content in the chamber may be lowered still. Subsequently, Ti sputtering may be performed on the actual samples, held just above the target, at a deposition rate of about 0.5nm/s. The deposition time may be varied to achieve Ti thicknesses of about 7nm and 15nm. Following the Ti deposition, the magnetron may be turned off for about 20 minutes to cool down. To establish a TiN ambient before actual deposition, a gas mixture of Ar and N2 may be introduced into the chamber, and TiN pre-sputtering may be conducted for 15 minutes. Subsequently, the actual TiN reactive sputtering may be performed, resulting in about a 100nm film with a controlled deposition rate of about 4.5nm/min. Following the deposition of the Ti/TiN gate stack, the process may be continued with self-aligned p-GaN etching, subsequent MESA isolation, formation of source/drain ohmic contacts (106, 107), and, ultimately, passivation.
[43] In a second embodiment of the present invention, the semiconductor device 100 is disclosed. The device 100 comprises a gate structure 103 that includes a Gallium Nitride (GaN) layer 102 sandwiched between a barrier layer 101 and a bi-metal layer 103-1. The GaN layer 102 can be a p-type GaN layer 102 with a thickness ranging from 70 to 85 nanometers (nm). In one embodiment, the GaN layer (102) having a thickness of between 50-150 nanometers (nm).
[44] The barrier layer 101 is an Aluminum Gallium Nitride (AlGaN) barrier layer with a thickness ranging from 8 to 15 nanometers (nm). The bi-metal layer 103-1 is composed of Titanium (Ti) and Titanium Nitride (TiN).
[45] In these embodiments, the semiconductor device 100 can be a High-Electron-Mobility Transistor (HEMT) based on Gallium Nitride (GaN) on Silicon (Si) technology. In one embodiment, the device 100 includes a substrate 104, a buffer layer 104-1 of Gallium Nitride (GaN) formed on the substrate 104, a channel layer 105 of unintentionally doped (UID) GaN formed on the buffer layer 104-1, an aluminum Nitride (AlN) barrier layer 101-1 formed on the channel layer 105, an aluminum Gallium Nitride (AlGaN) barrier layer 101 formed on the AlN barrier layer 101-1, and a two-dimensional electron gas (2DEG) region 110 formed at the interface between the AlGaN barrier layer 101 and the UID GaN channel layer 105.
[46] In these embodiments, the gate structure 103 includes a p-type Gallium Nitride (p-GaN) layer 102 formed on the AlGaN barrier layer 101 and a bi-metal layer 103-1 of Titanium (Ti) and Titanium Nitride (TiN) formed on the p-GaN layer 102. Additionally, a second passivation layer 109 of Silicon Dioxide (SiO2) covers the gate structure 103, and a first passivation layer 108 of aluminum Oxide (Al0.5Ti0.5O) covers the second passivation layer 109.
[47] In these embodiments, the semiconductor device 100 may further include a source contact 106 and a drain contact 107 formed on the GaN channel layer 105. These contacts facilitate current flow across the 2DEG region under an applied voltage. The second passivation layer 109 serves as a gate insulator, providing electrical isolation between the gate structure 103 and the source contact 106, and the drain contact 107.
[48] In these embodiments, the buffer layer 104-1 can be a multi-layer stack designed to minimize lattice mismatch between the GaN and Si substrate 104. The AIN barrier layer 101-1 may have a thickness ranging from 0.5 to 2.0 nanometers (nm), the channel layer 105 may have a thickness ranging from 170 to 180 nanometers (nm), the first passivation layer 108 may have a thickness ranging from 7 to 12 nanometers (nm), and the second passivation layer 109 may have a thickness ranging from 95 to 105 nanometers (nm).
[49] In another embodiment, the AIN barrier layer (101-1) having a thickness of between 0.5-2.0 nanometers (nm). The channel layer (105) having a thickness of between 100- 300 nanometers (nm). The first passivation layer (108) having a thickness of between 7- 12 nanometers (nm). The first passivation layer (108) having a thickness of between 50- 200 nanometers (nm).
[50] In these embodiments, the buffer layer (104-1) is a multi-layer stack designed to minimize lattice mismatch between the GaN and Si substrate (104).
[51] In these embodiments, the semiconductor device 100 can be a High-Electron-Mobility Transistor (HEMT) based on Gallium Nitride (GaN) on Silicon (Si) technology.
[52] In a third embodiment of the invention, a P-type Gallium Nitride-based enhancement mode high electron mobility transistor (p-GaNe-HEMT) 100 is illustrated. The p-GaN e-HEMT 100 includes a plurality of barrier layers 101, 101-1 comprising a first material and a second material. Above the barrier layers 101, a p-type doped layer 102 comprising a third material is disposed to provide a current flow path. A gate metal stack 103 comprising a fourth material is placed on the p-type doped layer 102 to reduce gate leakage current. The thickness of titanium (Ti) in the gate metal stack 103 is adjusted up to a predetermined threshold to tune the gate work function. Further, the first passivation layer 108 and the second passivation layer 109 are disposed on the plurality of barrier layers 101, 101-1, the first passivation layer 108 comprising a fifth material is aluminum Oxide (Al0yTi1-yO), and the second passivation layer 109 having a sixth material i.e. Silicon Dioxide (SiO2).
[53] In an exemplary implementation of the third embodiment, the p-GaN e-HEMT 100 further includes a substrate 104 made of a grade 600V gallium nitride (GaN) on a silicon (Si) wafer. In one embodiment, the substrate 104 may be made of GaN on Si, AI2O3, Sapphire, or QST.
[54] A channel layer 105 made of ultra-wide bandgap gallium nitride (UID GaN) is disposed of on the substrate 104. A source contact 106 and a drain contact 107 are placed on the channel layer 105 and separated by a predefined first distance (d1), forming a channel. The plurality of barrier layers 101, 101-1, the p-type doped layer 102, and the gate metal stack 103 are further disposed of within the channel layer 105.
[55] In the exemplary implementation of the third embodiment, the plurality of barrier layers 101, 101-1 is disposed on the channel layer 105 to form a barrier between the channel layer 105 and the gate metal stack 103.
[56] In the exemplary implementation of the third embodiment, the gate metal stack 103 is deposited on the p-type doped layer 102 using a DC reactive magnetron sputtering process. The thickness of titanium (Ti) in the gate metal stack (103) is adjusted using an atomic force microscopy technique.
[57] In the exemplary implementation of the third embodiment, the first material includes aluminum nitride (AlN), the second material includes aluminum gallium nitride (AlGaN), the third material includes p-type gallium nitride (p-GaN), and the fourth material includes titanium (Ti) or titanium nitride (TiN). The fifth material includes aluminum titanium Oxide (AIyTi1-yO), and the sixth material includes silicon dioxide (SiO2).
[58] In the exemplary implementation of the third embodiment, the predetermined threshold of the thickness of titanium (Ti) in the gate metal stack (103) is adjusted between 7 nanometers (nm) and 15 nanometers (nm).
[59] In a fourth embodiment of the invention, atomic force microscopy may be employed to calibrate the thickness of the Ti/TiN film. Ultraviolet photoelectron spectroscopy (UPS) may be employed to measure the work function of test p-GaN samples with a blanket Ti(7,15nm)/TiN layer. An unfiltered He I (21.22 eV) gas discharge lamp may be used for this purpose. The samples followed similar steps as the actual device samples, with a 10nm gate metal stack etched before UPS measurement to determine the work function near the metal/p-GaN interface. To establish a common reference point at the Fermi level (0eV), Fermi edge calibration may be performed using a sputter-cleaned Ag standard. The work function may be determined by subtracting the total width of the spectrum |KEmax ? KEmin| from the He I radiation energy of 21.2 eV, according to the equation:

[60] Further, room temperature scanning Kelvin probe microscopy (SKPM) may be carried out on the UPS samples using with Vtip (1.5V) > Vsample(0V), to offer additional validation for the work function measurements. While SKPM may not yield the absolute value of the work function due to the absence of a controlled environment during measurements, it is capable of capturing any discernible trend in the work function w.r.t. the thickness of Ti.
[61] In a fifth embodiment of the invention, a method 800 of fabricating a P-type Gallium Nitride-based enhancement mode high electron mobility transistor (p-GaNe-HEMT) device 100 is illustrated. The method 800 includes the following steps: i. depositing 201 a plurality of barrier layers 101 on a substrate 104, wherein the plurality of barrier layers 101, 101-1 comprises a first material and a second material, ii. forming 202 a p-type doped layer 102 on the plurality of barrier layers 101, 101-1, wherein the p-type doped layer 102 comprises a third material and provides a path for current flow, iii. depositing 203 a gate metal stack 103 on the p-type doped layer 102, wherein the gate metal stack 103 comprises a fourth material and is configured to reduce gate leakage current, iv. adjusting 204 the thickness of titanium (Ti) in the gate metal stack 103 up to a predetermined threshold, thereby tuning the gate work function of the p-GaN e-HEMT (100).
[62] In an exemplary implementation of the fifth embodiment, the plurality of barrier layers 101, 101-1 comprises Aluminium Gallium Nitride (AlGaN) barrier layer 101, and AlN barrier layer 101-1 respectively.
[63] In an exemplary implementation of the fifth embodiment, the material used in the various layers mentioned above is illustrated. The first material is aluminum nitride (AlN). The second material is aluminum gallium nitride (AlGaN). The third material is p-type gallium nitride (p-GaN). The fourth material is a bilayer metal stack comprising titanium (Ti) and titanium nitride (TiN).
[64] In the exemplary implementation of the fifth embodiment, the method 800 further includes adjusting the thickness of the titanium (Ti) layer in the gate metal stack 103 using a technique such as atomic force microscopy (AFM) or sputtering process.
[65] In the exemplary implementation of the fifth embodiment, the predetermined threshold of the thickness of titanium (Ti) in the gate metal stack (103) is adjusted between 7 nanometers (nm) and 15 nanometers (nm).
[66] FIGs. 2A 200 and 2B 210 illustrate exemplary plots depicting work function extraction at the gate of the HEMT device 100, in accordance with an exemplary embodiment of the present disclosure.
[67] FIG. 2C 220 illustrates an exemplary plot depicting a difference in SKPM contact potential difference between two gate stacks of different thicknesses 100, in accordance with an exemplary embodiment of the present disclosure.
[68] Referring now to FIGs. 2A to 2C, specifically, FIG. 2A illustrates the UPS spectrum, indicating a significant difference in spectrum width for Ti thicknesses of 7nm and 15nm. Using the equation given above with Ag as a reference having a work function (WF) of 4.6eV, it may be seen that the work function exhibits a decreasing trend as Ti thickness decreases. The correlation between lower Ti thickness and a reduced work function may be further supported by the difference in SKPM contact potential difference (CPD) between the two stacks. The relationship between the sample work function (Fsample) and Ftip, along with the CPD may be given by,

[69] The Ti/TiN stack with a Ti thickness of 15nm displays a higher CPD, indicating a higher work function.
[70] In a sixth embodiment of the present invention, a method 800 of fabricating a semiconductor device 100 is disclosed. The method 800 includes the following steps:
[71] At block 201, the method 201 begins by forming a Gallium Nitride (GaN) buffer layer 104-1 on a silicon substrate 104. The buffer layer 104-1 serves as a foundation for the subsequent layers and helps to mitigate the lattice mismatch between the GaN and Si substrate 104, improving the overall device 100 performance and reducing defects. The buffer layer 104-1 can be formed using various techniques, such as molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD).
[72] At block 202, an unintentionally doped (UID) GaN channel layer 105 is deposited on the buffer layer 104-1. The channel layer 105 is where the active carrier flow occurs in the device 100. The UID GaN ensures that the channel layer 105 has a high electron mobility, which is essential for efficient device 100 operation. The deposition of the channel layer 105 can also be performed using MBE or MOCVD.
[73] At block 203, an Aluminum Nitride (AlN) barrier layer is then formed on the channel layer 105. The AlN barrier layer acts as a potential barrier, creating a depletion region at the interface with the channel layer 105. This depletion region is crucial for the formation of the two-dimensional electron gas (2DEG) at the interface between the AlGaN barrier layer and the UID GaN channel layer 105. The AlN barrier layer can be deposited using techniques like MBE or pulsed laser deposition (PLD).
[74] At block 204, an Aluminum Gallium Nitride (AlGaN) barrier layer is subsequently deposited on the AlN barrier layer. The AlGaN barrier layer has a higher bandgap than the GaN channel layer 105, which further enhances the formation of the 2DEG. The composition of the AlGaN barrier layer can be adjusted to control the properties of the 2DEG, such as its electron density and mobility. The AlGaN barrier layer can be deposited using MBE or MOCVD.
[75] At block 205, at the interface between the AlGaN barrier layer and the UID GaN channel layer 105, a two-dimensional electron gas (2DEG) region 110 is formed. The 2DEG is a highly mobile layer of electrons that is confined to a narrow region at the interface. The 2DEG is responsible for the high-speed and low-noise operation of the semiconductor device 100.
[76] At block 206, a gate structure 103 is then formed on the AlGaN barrier layer. The gate structure 103 consists of a p-type GaN layer 102 sandwiched between a Ti/TiN bi-metal layer 103-1 and the AlGaN barrier layer. The p-GaN layer 102 acts as a gate insulator, while the Ti/TiN bi-metal layer 103-1 serves as the gate electrode. The gate structure 103 controls the flow of current through the 2DEG region.
[77] At block 207, a Silicon Dioxide (SiO2) second passivation layer 109 is deposited over the gate structure 103. The SiO2 second passivation layer 109 provides electrical insulation between the gate electrode and the underlying layers of the device 100. It also helps to protect the device from environmental factors.
[78] Finally, at block 208, an Al0.5Ti0.5O first passivation layer 108 is applied over the SiO2 passivation layer 109. The first passivation layer 108 acts as a protective coating, preventing the device 100 from degradation due to exposure to moisture, oxygen, and other contaminants. It also helps to improve the device's reliability and long-term performance.
[79] To summarise, the high-quality semiconductor device 100 can be fabricated by using the disclosed method 800. The specific deposition techniques and layer thicknesses can be optimized to achieve the desired device characteristics.
[80] FIGs. 3 (A-D) illustrates an exemplary representation of a plot depicting I-V characteristics of the HEMT devices 300 (FIG. 3A), an exemplary plot depicting a comparable ON/OFF ratio and a shift in VTH 310 (FIG. 3B), and an exemplary distribution plot depicting a positive VTH shift for thinner Ti layer 320 (FIG. 3C); and an exemplary plot depicting the distribution of gate leakage and maximum gate overdrive of the HEMT devices 330 (FIG. 3D), in accordance with an exemplary embodiment of the present disclosure.
[81] FIG. 3A 300 illustrates an exemplary plot depicting I-V characteristics of the HEMT devices 100;
[82] FIG. 3B 310 illustrates an exemplary plot depicting a comparable ON/OFF ratio and a shift in VTH;
[83] FIG. 3C 320 illustrates an exemplary distribution plot depicting a positive VTH shift for a thinner Ti layer; and
[84] FIG. 3D 330 illustrates an exemplary plot depicting the distribution of gate leakage and maximum gate overdrive of the HEMT devices 100, in accordance with an exemplary embodiment of the present disclosure.
[85] Referring now to FIGs. 3A to 3D (300-330), the characteristics of the HEMT devices for both stacks may exhibit similar ON-OFF ratios, while those with a lower work function may exhibit an improved threshold voltage (VTH). Moreover, the gate characteristics reveal a ~1 order reduction in ON-state gate leakage as the work function is lowered by adjusting Ti thickness from 15nm to 7nm. Additionally, a further comparison of the gate overdrive characteristics for the two stacks, may indicate an approximately 1.9V gate overdrive improvement for the lower work function corresponding to Ti thickness of ~7nm. These improvements may be attributed to increased effective Schottky barrier height at the Metal/p-GaN interface. Based on these findings, low-work function gate metal stacks may be used to enhance gate stack performance.
[86] FIGs. 4 (a-b) illustrates an exemplary representation 400 of the cross-section STEM of the metal p-GaN gate stack with varying Ti thickness, in accordance with an exemplary embodiment of the present disclosure.
[87] Referring to FIGs. 4, cross-section STEM of the metal p-GaN gate stack with varying Ti thickness is illustrated. Graph (a) shows a higher interdiffusion at the p-GaN/Ti-TiN interface, for thicker Ti. The STEM EDX compositional analysis in graph (b) shows a more Ga out diffusion at the interface for thicker Ti films. The remaining Ga vacancies below the contact may act as shallow acceptors, and the Schottky barrier height (SBH) may be decreased, thereby increasing the gate leakage. Also, Ga consumption at the interface results in a thinner p-GaN, which can lower the Vth of the device accordingly.
[88] FIGs. 5 (a-d) illustrates an exemplary representation 500 of design variations of the semiconductor device 100, in accordance with an exemplary embodiment of the present disclosure.
[89] Referring to FIGs. 5, in an embodiment, the bimetal layer 103-1 is un-passivated i.e. nothing is disposed on the AIGaN barrier layer 106. In another embodiment, the bimetal layer 103-1 having the passivation of SiOx, AlOx, SiN, AlTiO in single layer or multi-layer forms, in amorphous or in crystalline form.
[90] FIGs. 6 (a-c) illustrates an exemplary representation of design variations of the semiconductor device 100, in accordance with an exemplary embodiment of the present disclosure.
[91] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. Where the specification claims refer to at least one of something selected from the group consisting of A, B, C ….and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.
[92] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions, or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.
[93] Further, elements and/or features of different example embodiments may be combined with each other and/or substituted for each other within the scope of this disclosure and appended claims.
[0094] Example embodiments being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the scope of the present invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

ADVANTAGES OF THE INVENTION:
[95] The present disclosure provides a system and a method for tuning the gate work function of a HEMT device using Ti/TiN gate metal stack.
[96] The present disclosure provides a device with Ti/TiN gate metal stack that offers advantages such as thermal stability, enabling gate-first processes.
[97] The present disclosure provides a device having Ti/TiN gate metal stack that reduces p-GaN HEMTs process complexity.
[98] The present disclosure provides a device that improves gate properties, including higher VTH and reduces leakage associated with lower work functions.
[99] The present disclosure provides a comprehensive solution that offers advantages such as higher threshold voltage (VTH), reduced gate leakage and improved maximum gate overdrive.
,CLAIMS:1. A semiconductor device (100) comprising:
a gate structure (103) having a bi-metal layer (103-1) wherein the bi-metal layer (103) is of Titanium (Ti) and Titanium Nitride (TiN), wherein the gate structure (103) is disposed on a Gallium Nitride (GaN) layer (102).
2. The semiconductor device (100) as claimed in claim 1, wherein:
a thickness of the titanium (Ti) is a pre-determined and adjustable;
the Gallium Nitride (GaN) layer (102) is a p-type, p-type oxide or semiconductor, crystalline, or amorphous; and
the barrier layer is an Aluminum Gallium Nitride (AlGaN) barrier layer, AIN, Indium AlN.
3. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) is a High-Electron-Mobility Transistor (HEMT) based on Gallium Nitride (GaN) on Silicon (Si) technology.
4. A semiconductor device (100) comprising:
a substrate (104);
a buffer layer (104-1) of Gallium Nitride (GaN) formed on the Si substrate (104);
a channel layer (105) of unintentionally doped (UID) GaN formed on the buffer layer 104-1;
an aluminium Nitride (AlN) barrier layer (101-1) formed on the channel layer (105);
an aluminium Gallium Nitride (AlGaN) barrier layer (101) formed on the AlN barrier layer (101-1);
a two-dimensional electron gas (2DEG) region (110) formed at the interface between the AlN barrier layer (101-1) and the UID GaN channel layer (105);
wherein the semiconductor device (100) comprises:
a gate structure (103) having a bi-metal layer (103-1) wherein the bi-metal layer (103) is of Titanium (Ti) and Titanium Nitride (TiN), wherein the gate structure (103) is disposed on a Gallium Nitride (GaN) layer (102);
a first passivation layer (108) is a or multilayer stack of (108) disposed on the second passivation layer (109) at least one other passivation layer, wherein the first passivation layer (108) is made of aluminium oxide (AlyTi1-yO), silicon oxide (SiOX), silicon nitride (SiNX), TiO2, Al2O3, or any alloyed oxide; and
the second passivation layer (109) is of aluminium oxide (AlyTi1-yO) silicon oxide (SiOX), silicon nitride (SiNX), TiO2, Al2O3, or any alloyed oxide.
5. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) further comprising a source contact (106) and a drain contact (107) formed on the GaN channel layer (105), configured to facilitate current flow across the 2DEG region under an applied voltage, and wherein the second passivation layer (109) operates as a gate insulator, providing electrical isolation between the gate structure (103) and source contact (106) and a drain contact (107).
6. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) further comprising a cap layer (114) formed on the aluminium gallium Nitride (AlGaN) barrier layer (101) by fully extending to the source contact (106) and the drain contact (107), or only on the gate side and partially or fully extended towards drain, wherein the cap layer is made of any, or combination of Gallium Nitride (GaN), p-type or intrinsic GaN, Aluminum Oxynitride (AlON), or Aluminum Nitride (AlN).
7. The semiconductor device (100) as claimed in claim 1, wherein the semiconductor device (100) further comprising any one or a combination of the second passivation layer (109) with a field plate (111), a spacer (112) and a drain field plate (113).
8. A method (800) of fabricating a semiconductor device (100), the method (800) comprising:
forming (201) a GaN buffer layer (104-1) on a substrate (104);
depositing (202) a UID GaN channel layer (105) on the buffer layer (104-1);
forming (203) an AlN barrier layer on the channel layer (105);
depositing (204) an AlGaN barrier layer on the AlN barrier layer;
creating (205) a 2DEG region at the interface between the AlGaN barrier layer and the UID GaN channel layer (105);
forming (206) a gate structure (103) comprising a p-GaN layer (102) and a bi-metal layer (103-1) on the AlGaN barrier layer, wherein the p-GaN layer (102) is sandwiched between the bi-metal layer (103-1) and the AlGaN barrier layer;
depositing (207) a SiO2 second passivation layer (109) over the gate structure (103); and
applying (208) an Al0.5Ti0.5O first passivation layer (108) over the SiO2 second passivation layer (109).
9. The method (800) as claimed in claim 8, wherein the semiconductor device (100) is a High-Electron-Mobility Transistor (HEMT) based on Gallium Nitride (GaN) on Silicon (Si) technology.
10. The method (800) as claimed in claim 8, wherein the semiconductor device (100) further comprising any one or a combination of the second passivation layer (109) with a field plate (111), a spacer (112) and a drain field plate (113).