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Methods And Apparatus For Fusing Instructions To Provide Or Test And And Test Functionality On Multiple Test Sources
Abstract: Methods and apparatus are disclosed for fusing instructions to provide OR-test and AND-test functionality on multiple test sources. Some embodiments include fetching instructions, said instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition. A portion of the plurality of instructions are fused into a single micro-operation, the portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction. Some embodiments generate a novel test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the novel test instruction through a just-in-time compiler. Some embodiments also fuse the novel test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
Notices, Deadlines & Correspondence
Patent Information
Applicants
INTEL CORPORATION
Inventors
1. LOKTYUKHIN, Maxim
2. VALENTINE, Robert
3. HORN, Julian C.
4. CHARNEY, Mark J.
Specification
CLIAMS:1. A method for fusing instructions in a processor comprising:
fetching a plurality of instructions, said plurality of instructions including a first instruction specifying a first operand destination, a second instruction specifying a second operand source, and a third instruction specifying a branch condition; and
fusing a portion of the plurality of instructions into a single micro-operation, said portion including both the first and second instructions if said first operand destination and said second operand source are the same, and said branch condition is dependent upon the second instruction.
,TagSPECI:FIELD OF THE DISCLOSURE
The present disclosure pertains to the field of processing logic, microprocessors, and associated instruction set architecture that, when executed by the processor or other processing logic, perform logical, mathematical, or other functional operations. In particular, the disclosure relates to methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources.
Documents
Application Documents
| # | Name | Date |
|---|---|---|
| 1 | IPO drawing INTL-392-IN.pdf | 2014-02-25 |
| 2 | FORM 2 INTL-392-IN.pdf | 2014-02-25 |
| 3 | Form-18(Online).pdf | 2014-03-17 |
| 4 | 859-CHE-2014 CORRESPONDENCE OTHERS 18-03-2014.pdf | 2014-03-18 |
| 5 | 859-CHE-2014 CORRESPONDENCE OTHERS 18-03-2014,.pdf | 2014-03-18 |
| 6 | 859-CHE-2014 POWER OF ATTORNEY 08-04-2014.pdf | 2014-04-08 |
| 7 | 859-CHE-2014 CORRESPONDENCE OTHERS 08-04-2014.pdf | 2014-04-08 |
| 8 | 859-CHE-2014-FER.pdf | 2019-03-29 |
| 9 | 859-CHE-2014-AbandonedLetter.pdf | 2019-10-04 |
Search Strategy
| 1 | SEARCHIN_28-03-2019.pdf |