Claims:1. An apparatus to configure heterogenous components in an accelerator, the apparatus comprising:
a graph compiler to:
identify a workload node in a workload; and
generate a selector for the workload node; and
the selector to identify an input condition and an output condition of a compute building block, wherein the graph compiler is to, in response to obtaining the identified input condition and output condition from the selector, map the workload node to the compute building block.
, Description:FIELD OF THE DISCLOSURE
[0001] This disclosure relates generally to processing, and, more particularly, to methods and apparatus to configure heterogenous components in an accelerator.

BACKGROUND
[0002] Computer hardware manufacturers develop hardware components for use in various components of a computer platform. For example, computer hardware manufacturers develop motherboards, chipsets for motherboards, central processing units (CPUs), hard disk drives (HDDs), solid state drives (SSDs), and other computer components. Additionally, computer hardware manufacturers develop processing elements, known as accelerators, to accelerate the processing of a workload. For example, an accelerator can be a CPU, a graphics processing units (GPUs), a vision processing units (VPUs), and/or a field programmable gate arrays (FPGAs).

BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is a block diagram illustrating an example computing system to configure heterogeneous components in an accelerator.
[0004] FIG. 2 is a block diagram illustrating an example computing system including an example graph compiler and one or more example selector(s).
[0005] FIG. 3 is an example block diagram illustrating an example selector of the one or more selector(s) of FIG. 2.
[0006] FIG. 4 is an example block diagram illustrating the graph compiler of FIG. 2.
[0007] FIG. 5 is a graphical illustration of an example pipeline representative of a workload executed using an example first CBB and an example second CBB.
[0008] FIG. 6 is a flowchart representative of a process that may be executed to implement the graph compiler, the selector, and/or the one or more selector(s) of FIGS. 2, 3, and/or 4 to generate the executable of FIG. 2.
[0009] FIG. 7 is a flowchart representative of a process that may be executed to implement the credit manager and/or the configuration controller of FIG. 2 to facilitate execution of the executable of FIG. 2.
[0010] FIG. 8 is a block diagram of an example processor platform structured to execute the instructions of FIGS. 6 and/or 7 to implement the example graph compiler, the example one or more selector(s), the example selector, and/or the accelerator of FIGS. 2, 3, and/or 4.
[0011] The figures are not to scale. In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. Connection references (e.g., attached, coupled, connected, and joined) are to be construed broadly and may include intermediate members between a collection of elements and relative movement between elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and in fixed relation to each other.