Methods And Systems For Managing Memory Blocks Of Semiconductor Devices In Embedded Systems

Claims:WE CLAIM 1. A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system, the method comprising: categorizing, via an Electronic Design Automation (EDA) tool, a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category, the overlapping category comprising target design memory blocks having overlapping memory operations and the non-overlapping category comprising target design memory blocks having non-overlapping memory operation; identifying, via the EDA tool, a set of target design memory blocks from the plurality of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, wherein each target design memory block in the set is identified from the same category selected from one of the overlapping category and the non-overlapping category; designing, via the EDA tool, semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; and implementing, via the EDA tool, the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device. 2. The method of claim 1 further comprising: classifying the plurality of target design memory blocks based on capacity requirements, capacity requirement of a target design memory block comprising depth and width requirement of the target design memory block; and classifying a plurality of embedded memory blocks in the semiconductor device based on associated capacities, capacity of an embedded memory block comprising width and depth of the embedded memory block, the plurality of embedded memory blocks comprising the single embedded memory block. 3. The method of claim 2, wherein the set of target design memory blocks is identified in response to classifying the plurality of target design memory blocks and the plurality of embedded memory blocks in the semiconductor device. 4. The method of claim 1, wherein the capacity criteria of the single embedded memory block in the semiconductor device, comprise combined width of memory blocks in the set of target design memory blocks being less than or equal to width of the single embedded memory block in the semiconductor device and combined depth of the memory blocks in the set of target design memory blocks being less than or equal to depth of the single embedded memory block in the semiconductor device. 5. The method of claim 1, wherein the memory operations comprise read and write operations. 6. The method of claim 1, wherein each of the target design memory blocks in the overlapping category comprise same clock for write memory operations and same clock for read memory operations. 7. The method of claim 1, wherein the semiconductor device components are selected from a group comprising multiplexer, de-multiplexer, sequential elements, and combinatorial gates. 8. The method of claim 1, wherein number and placement of the semiconductor device components corresponds to one of the overlapping and the non-overlapping category, which the set of target design memory blocks is associated with. 9. The method of claim 1, wherein implementing comprises: placing the set of target design memory blocks and the semiconductor device components on the single embedded memory block; and performing routing in the semiconductor device in response to the placing, wherein routing accommodates the placed set of target design memory blocks and the placed semiconductor device components. 10. The method of claim 1, wherein the semiconductor device comprises Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Part (ASSP), System on Chip (SoC), and System on Programmable Chip (SoPC). 11. A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system, the method comprising: categorizing, via an Electronic Design Automation (EDA) tool, a set of target design memory blocks into overlapping memory operation patterns and non-overlapping memory operations patterns; and implementing, via the EDA tool, the set of target design memory blocks to a single embedded memory block of the semiconductor device based on the categorizing. 12. The method of claim 11, wherein the memory operations comprise a read operation and a write operation. 13. The method of claim 11, wherein the embedded system comprises a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Application Specific Standard Part (ASSP), System on Chip (SoC), and System on Programmable Chip (SoPC). 14. The method of claim 11, wherein the set of target design memory blocks satisfy the capacity criteria for the single embedded memory block. 15. The method of claim 14, wherein the capacity criteria of the single embedded memory block comprise combined width of memory blocks in the set of target design memory blocks being less than or equal to width of the single embedded memory block in the semiconductor device and combined depth of the memory blocks in the set of target design memory blocks being less than or equal to depth of the single embedded memory block in the semiconductor device. 16. The method of claim 11 further comprising designing embedded system components to be created on the embedded system to implement the set of design memory blocks to the single embedded memory block. 17. A system for mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system, the system comprising: at least one processors; and a computer-readable medium storing instructions that, when executed by the at least one processor, cause the at least one processor to perform operations comprising: categorizing a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category, the overlapping category comprising target design memory blocks having overlapping memory operations and the non-overlapping category comprising target design memory blocks having non-overlapping memory operation; identifying a set of target design memory blocks from the plurality of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, wherein each target design memory block in the set is identified from the same category selected from one of the overlapping category and the non-overlapping category; designing semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; and implementing the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device. 18. The system of claim 17, wherein the operations further comprise: classifying the plurality of target design memory blocks based on capacity requirements, capacity requirement of a target design memory block comprising depth and width requirement of the target design memory block; and classifying a plurality of embedded memory blocks in the semiconductor device based on associated capacities, capacity of an embedded memory block comprising width and depth of the embedded memory block, the plurality of embedded memory blocks comprising the single embedded memory block. 19. The system of claim 17, wherein the capacity criteria of the single embedded memory block in the semiconductor device, comprise combined width of memory blocks in the set of target design memory blocks being less than or equal to width of the single embedded memory block in the semiconductor device and combined depth of the memory blocks in the set of target design memory blocks being less than or equal to depth of the single embedded memory block in the semiconductor device. 20. The system of claim 17, wherein each of the target design memory blocks in the overlapping category comprise same clock for write memory operations and same clock for read memory operations. 21. The system of claim 17, wherein number and placement of the semiconductor device components corresponds to one of the overlapping and the non-overlapping category, which the set of target design memory blocks is associated with. 22. The system of claim 17, wherein the operation of implementing further comprises operations of: placing the set of target design memory blocks and the semiconductor device components on the single embedded memory block; and performing routing in the semiconductor device in response to the placing, wherein routing accommodates the placed set of target design memory blocks and the placed semiconductor device components.

Dated this 3rd day of August, 2016

R Ramya Rao Of K&S Partners Agent for the Applicant , Description:TECHNICAL FIELD This disclosure relates generally to embedded systems and more particularly to methods and systems for managing memory blocks of semiconductor devices in embedded systems.