Claims:WE CLAIM
1. An integrated circuit design apparatus, comprising:
one or more hardware processors; and
one or more memory units storing instructions which when executed cause the one or more hardware processors to perform acts comprising:
obtaining, via the one or more hardware processors, register transfer level code for an integrated circuit design block;
parsing, via the one or more hardware processors, the register transfer level code to extract a pragma included in the register transfer level code for the integrated circuit design block;
determining, via the one or more hardware processors, a timing constraint from the extracted pragma;
synthesizing, via the one or more hardware processors, a netlist for an integrated circuit design including at least one instance of the integrated circuit design block, using the determined timing constraint; and
providing, via the one or more hardware processors, the netlist for use in an integrated circuit manufacturing process.
2. The apparatus of claim 1, wherein the timing constraint is one of: an integrated circuit design block-level timing constraint, and an integrated circuit design-level timing constraint.
3. The apparatus of claim 1, wherein the timing constraint is one of: a clock definition; a path specification; an input/output constraint; and determined based on an operating mode.
4. The apparatus of claim 1, the one or more memory units further storing instructions which when executed cause the one or more hardware processors to perform acts comprising:
determining, via the one or more hardware processors, an integrated circuit-level timing constraint from the extracted pragma; and
synthesizing, via the one or more hardware processors, the netlist for the integrated circuit design further using the determined integrated circuit-level timing constraint.
5. The apparatus of claim 1, wherein the pragma is included as an inline comment in the register transfer level code.
6. The apparatus of claim 1, wherein the pragma includes one or more optional fields for determining the integrated circuit design block-level timing constraint.
7. The apparatus of claim 1, the one or more memory units further storing instructions which when executed cause the one or more hardware processors to perform acts comprising:
executing, via the one or more hardware processors, an electronic design automation tool for parsing the register transfer level code to extract the pragma and determining the integrated circuit design block-level timing constraint.
8. The apparatus of claim 1, wherein the determined timing constraint is usable for timing closure during physical design or layout of an integrated circuit corresponding to the synthesized integrated circuit design.
9. The apparatus of claim 1, the one or more memory units further storing instructions which when executed cause the one or more hardware processors to perform acts comprising:
obtaining, via the one or more hardware processors, a second register transfer level code for a second integrated circuit design block;
wherein the second register transfer level code for the second integrated circuit design block is obtained from a different source than the register transfer level code for the integrated circuit design block;
parsing, via the one or more hardware processors, the second register transfer level code to extract a second pragma included in the second register transfer level code for the second integrated circuit design block;
determining, via the one or more hardware processors, a second integrated circuit design block-level timing constraint from the extracted second pragma; and
synthesizing, via the one or more hardware processors, the netlist for the integrated circuit design further including at least one instance of the second integrated circuit design block, using the determined second integrated circuit design block-level timing constraint.

10. A method for designing an integrated circuit, the method comprising:
obtaining register transfer level code for an integrated circuit design block;
parsing the register transfer level code to extract a pragma included in the register transfer level code for the integrated circuit design block;
determining a timing constraint from the extracted pragma;
synthesizing a netlist for an integrated circuit design including at least one instance of the integrated circuit design block, using the determined timing constraint; and
providing the netlist for use in an integrated circuit manufacturing process.

11. The method of claim 10, wherein the timing constraint is one of: an integrated circuit design block-level timing constraint, and an integrated circuit design-level timing constraint.
12. The method of claim 10, wherein the timing constraint is one of: a clock definition; a path specification; an input/output constraint; and determined based on an operating mode.
13. The method of claim 10, further comprising:
determining an integrated circuit-level timing constraint from the extracted pragma; and
synthesizing the netlist for the integrated circuit design further using the determined integrated circuit-level timing constraint.
14. The method of claim 10, wherein the pragma is included as an inline comment in the register transfer level code.
15. The method of claim 10, wherein the pragma includes one or more optional fields for determining the integrated circuit design block-level timing constraint.
16. The method of claim 10, further comprising:
executing an electronic design automation tool for parsing the register transfer level code to extract the pragma and determining the integrated circuit design block-level timing constraint.
17. The method of claim 10, wherein the determined timing constraint is usable for timing closure during physical design or layout of an integrated circuit corresponding to the synthesized integrated circuit design.
18. The method of claim 10, further comprising:
obtaining a second register transfer level code for a second integrated circuit design block;
wherein the second register transfer level code for the second integrated circuit design block is obtained from a different source than the register transfer level code for the integrated circuit design block;
parsing the second register transfer level code to extract a second pragma included in the second register transfer level code for the second integrated circuit design block;
determining a second integrated circuit design block-level timing constraint from the extracted second pragma; and
synthesizing the netlist for the integrated circuit design further including at least one instance of the second integrated circuit design block, using the determined second integrated circuit design block-level timing constraint.

Dated this 16th day of February 2017

Swetha SN
Of K&S Partners
Agent for the Applicant
, Description:TECHNICAL FIELD
The field of the present invention relates to system-on-chip (SoC) design, wherein the SoC design involves using design blocks from multiple sources (designers). More specifically, the present invention relates to novel methods for generating timing constraints, and thus reducing the complexity of synthesis and static timing analysis (STA) in SoC design arising out of designs received from multiple sources of SoC blocks.