2
FIELD OF INVENTION
The present invention relates to a method of improving turn-off
characteristics of power semiconductor thyristor by way of control of anode-
side emitter layer.
BACKGROUND OF THE INVENTION
Thyristor, which is a three-terminal (anode, cathode and gate) semiconductor
device, is basically an on/off-switch, controllable through the gate in its
forward-bias mode. When it is turned-off by reverse-bias, it takes a finite
time termed as turn-off time (tq) before the stored charges within the
thyristor are completely cleared away. Fig-1 shows the schematic waveforms
of current and voltage during turn-off process. Fig-2 shows the schematic
diagram of n+-p-n-p-p+ thyristor structure and the carrier distributions at
various time instants defined in Fig-1.
The cross-section of a complete thyristor chip according to the prior art is
shown in Fig-3. Silicon wafer of n-type is processed through various doping
and photolithography steps to form the additional p and n+ layers that result
in n+-p-n-p-n+ structure. The n+ layer is simultaneously formed on both the
sides of the silicon wafer during a doping process that uses phosphorus as n-
type impurity. The anode-side of wafer is then brazed with a molybdenum
plate using Al-Si brazing alloy. As aluminium is a p-type dopant, the n+ on
anode-side is replaced with p+ during brazing resulting in the thyristor
structure n+-p-n-p-p+.

3
The above conventional process yields non-conformities in turn-off time,
whose value considerably exceeds the upper specification limit in the non-
conforming samples as compared to the conforming ones. Accordingly, the
manufacturing yield is adversely affected.
According to prior art JP 2002270820, US 6163040, US 4281336, JP
54129989 AND US 4066484, thyristor turn-off time is controlled by adjusting
the recombination rate of carriers (electrons and holes) within the bulk of
silicon wafer through various methods such as gold doping, electron
irradiation. However, details or discussions on the problem of excessive
turn-off time specifically arising out of anode-side emitter are not taken into
consideration in the prior art on record.
OBJECTS OF INVENTION
It is therefore an object of the invention to propose a method of improving
turn-off characteristics of power semiconductor thyristor which is based on
the phenomenon of delayed turn-off in the non-conforming thyristor samples
of a manufacturing lot.
Another object of the invention is to propose a method of improving turn-off
characteristics of power semiconductor thyristor which completely eliminates
the occurrence of non-conformities in turn-off time.
A further object of the invention is to propose a method of improving turn-off
characteristics of power semiconductor thyristor which is adaptable to
industrial manufacturing process.

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SUMMARY OF INVENTION
Accordingly there is provided a method of improving turn-off characteristics
of power semiconductor thyristor which is developed on the basis of the
phenomenon of delayed turn-off observed in the non-conforming thyristor
samples of a manufacturing lot.
The invention discloses a method which enables complete elimination of the
occurrence of turn-off time values that are strikingly well away from those of
the conforming samples.
The invention discloses a method which implements during the brazing
process complete conversion of the anode-side n+ as p+.
The invention provides a combined criticality of the thickness of silicon wafer
and the width of anode-side n+ layer.
For thinner wafers, according to the invention, formation of anode-side n+ is
avoided prior to the brazing process, as it does not affect the other
characteristics of thyristor.
For thicker wafers, the inventive process retains the n+ layer on anode-side
and incorporates compensatory adjustments in the brazing process to help
complete replacement of n+ with p+.
The invention secures the turn-off time values within the upper specification
limit for all the thyristor types thereby improving the manufacturing yield and
product reliability.

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BRIEF DESCRIPTION OF ACCOMPANYING DRAWINGS
The illustrations accompanying this invention are as follows
Fig-1 - Schematic current and voltage waveforms during turn-off phase of
thyristor operation according to prior art.
Fig-2 - Schematic diagram of n+-p-n-p-p+ thyristor structure and the carrier
distributions at various time instants defined in Fig-1.
Fig-3 - Schematic diagram of cross-section of a normal thyristor chip
according to prior art.
Fig- 4- Measured waveforms of thyristor current (a) with normal turn-off
according to prior art and (b) with delayed turn-off according to th*s
invention.
Fig-5 - Schematic diagram of cross-section of thyristor chip with incomplete
replacement of anode-side n+ with p+ according to the invention.
Table-1- Layout of experiments to identify the cause of delayed turn-off and
the summary of qualitative results for 1800V and 3200V thyristors with
respective silicon wafers of 470-μm & 800-μm thickness, according to the
invention.

6
Table-2 - Example demonstrating the combined impact of silicon wafer
thickness and anode-side n+ layer on gettering during phosphorus doping
and the resultant on-state conduction drop (UT) of thyristor, according to the
invention.
Table-3 - Example demonstrating the impact of width of anode-side n+ layer
on turn-off time (tq) for thinner silicon wafers (< ~500-μm thick), according
to the invention.
Table-4 - Example demonstrating the impact of brazing temperature on turn-
off time for thicker silicon wafers (> ~500-μm thick), according to the
invention.
DETAILED DESCRIPTION OF INVENTION
Process steps in fabrication of n+-p-n-p-p+ thyristor structure:
The conventional process steps involved in fabrication of n+-p-n-p-p+
thyristor structure using n-type silicon wafer as raw material are briefly
described as below:
Step-1: p-type diffusion
Dopants of p-type such as aluminium and boron are used to form p-n-p
structure. Typical width of p-layer = 80-100 microns.

7
Step-2: Thermal oxidation
Silicon wafers are heated to form a silicon-di-oxide (SiO2) layer all around.
Step-3: Photolithography
Selective etching of SiO2 oxide layer is achieved using photolithography to
etch away the oxide layer all around the silicon wafer except for a centre
circular region (gate) on cathode side.
Step-4: n+ phosphorus doping
Phosphorus, which is an n-type dopant, is used to form highly doped n+
layers formed all around except at the gate region where SiO2 oxide layer is
present. Typical width of n+ layer is 20-25 microns. Resultant structure is
n+-p-n-p-n+. SiO2 layer is removed after the doping process.
Step-5: Gold doping
Gold is doped into the silicon thyristor structure for control of carrier life time
that in turn determines the turn-off time (tq) and on-state conduction drop
(UT).
Step-6: Brazing of silicon wafer with Molybdenum plate
The anode-side of the fully doped n+-p-n-p-n+ structure is further brazed
with a molybdenum plate using Al-Si brazing alloy. Aluminium present in the

8
alloy forms p+ layer that replaces the previously doped n+ layer resulting in
the thyristor structure n+-p-n-p-p+.
Experimentation on turn-off characteristics:
Thyristor samples with delayed turn-off were studied in comparison with
those with normal turn-off. The measured waveform of thyristor current
during turn-off (Fig-4) revealed the difference in time-period Tl, whereas the
time-period T2 remained the same. As T2 represents period during which
the thyristor current decays due to recombination of electrons and holes, the
problem can be assumed to be not attributable to the rate of recombination,
which is determined by various doping processes especially related to
phosphorus and gold (Step-4 and Step-5). Accordingly, it can be considered
that the longer Tl portion is due to incomplete replacement of the anode-
side n+ with p+ during brazing process. In such a case, a thin layer of
uncompensated n+ that lies buried below the p+ layer (Fig-5) is the probable
cause of delayed turn-off.
In order to verify the above findings, the significance of n+ layer on anode-
side was experimented with reference to phosphorus doping and brazing
processes (Step-4 and Step-6) and in terms of the thyristor parameters viz.
gate turn-on current (IGT), on-state conduction drop (UT) and turn-off time
(tq).
Experimentation to verify the findings on anode-side n+ layer:
Experiments were conducted on two types of thyristor that differ in ratings
(1800V and 3200V). The thickness of silicon wafers of respective thyristors

9
are 470-μm and 800-μm. The process parameters experimented are as
follows:
a) Phosphorus doping process
al) Doping time (adjusted to vary the n+ layer width)
a2) Formation of n+ layer on anode-side (with and without)
b) Brazing temperature
It is to be noted that extreme values of phosphorus doping time were chosen
to simulate the well-known effect of width of cathode-side n+ layer on gate
turn-on current of thyristor.
Qualitative summary of results of the experimentation:
The summary of the results of measurement of gate turn-on current (IGT),
on-state conduction drop (UT) and turn-off time (tq) is presented in Table-1.
The results are qualitatively indicated as OK and NOK (not-OK), based on the
non-conformities observed in the respective thyristor parameters. Following
are the findings from the tabulated results:
a) Non-conformities in IGT are attributable to insufficient doping time.
b) Non-conformities in UT are attributable to absence of anode-side
n+ layer.

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c) Non-conformities in tq are attributable to longer doping time as
well as insufficient brazing temperature.
Experimental analysis of the results and conclusions:
Analysis of results of gate turn-on current (IGT)
From the fundamental principles of thyristor design, it is well known [2-4]
that the gate turn-on current (IGT) is determined by the conductivity of p-
layer lying below the n+ layer on cathode-side. Longer the phosphorus
doping, wider is the resulting n+ layer, lower are the conductivity of the
underlying p-layer and the resultant IGT. Similarly, shorter the phosphorus
doping, narrower is the resulting n+ layer, higher are the conductivity of the
underlying p-layer and the resultant IGT. For healthy operation of thyristor in
application circuits, it is necessary that IGT is maintained within the specified
lower and upper limits.
The results of experiments are demonstrative of these findings, as higher re-
values were observed for shorter doping time (4-hrs) and lower values
observed for longer time (7-hrs). Width of n+ layer on cathode-side is
therefore critical with respect to IGT. Accordingly, any change proposed on
width of anode-side n+ requires careful study, since n+ is concurrently formed
on both the sides.
Analysis of results of on-state conduction drop (UT)
Conventionally, n+ layer is formed on both the cathode and anode sides,
although the anode-side layer is later replaced with p+ layer formed during

11
brazing process. This is because, the phosphorus-silicate-glass (PSG) that
grows upon the surface of n+ layer during phosphorus doping improves the
carrier lifetime by way of gettering of metal impurities [5, 6] from the bulk of
silicon wafer, thereby establishing a rate of recombination that is slow
enough to achieve the on-state conduction drop (UT) within its upper
acceptance limit.
This phenomenon is evident from the results of UT values that exceeded the
upper limit when n+ layer was avoided on anode-side, in the case of thyristor
samples with thicker silicon wafers (800-^m). However, UT values were
observed to lie within the upper limit and in the same range irrespective of
the presence of n+ layer on anode-side, in the cases of thyristor samples with
thinner silicon wafers (470-jim).
These observations verify the well-known significance of n+ layer with regard
to UT and additionally suggest the strong influence of thickness of silicon
wafer on the gettering process.
Analysis of results of turn-off time (tq)
Turn-off time values were found to be within the upper specification limits in
all the cases except for longer doping time (7-hrs) coupled with the
formation of anode-side n+ and lower brazing temperature (700 °C).
As it is known that longer doping time offers wider n+ layer and that lower
brazing temperature offers narrower p+ layer [7], the problem of delayed
turn-off characterized by extended Tl portion of current waveform is clearly
attributable to inadequate replacement of n+ with p+. A thin n+ layer that lies

12
buried under p+ as depicted in Fig-5 is therefore the cause as hypothesised
prior to experimentation. This conclusion is further supported by the
observation that longer doping time (7-hrs) coupled with increased brazing
temperature (720 °C) has not yielded any non-conformity in turn-off time
due to off-setting effect.
Findings based on results analysis
a) Thyristors using silicon wafers with thickness below a specified value
(~500-^m) are proposed to be processed without formation of n+
layer on anode-side so as to achieve outright elimination of delayed
turn-off. Hence, for thinner wafers, the brazing temperature does not
become critical.
b) Thyristors with higher silicon wafer thickness (>~500-|am thick)
essentially require the presence of n+ layer on anode-side prior to
brazing in order to avoid increase in on-state conduction drop (UT).
An increased brazing temperature is recommended to compensate for
any increase in n+ layer sought to achieve the desired gate turn-on
current.
EXAMPLES / PREFERRED EMBODIMENT
Example demonstrating combined impact of thickness of silicon wafer and
anode-side n+ layer upon on-state conduction drop:
Thyristors of two different ratings (3200V, 1800V) were manufactured with
and without n+ layer on anode-side. The thickness of respective silicon

13
wafers are 800-μm and 470-μm. The measured values of on-state conduction
drop (UT) are tabulated in Table-2.
It is evident that UT values have crossed the upper specification limit (1.70V)
for higher wafer thickness (800-jam), when n+ layer is avoided on anode-side.
On the contrary, no impact of anode-side n+ layer is observed on UT values
for thinner wafers (470-^m).
Example demonstrating impact of width of anode-side n+ upon turn-off time
of thinner silicon wafers:
Thyristors of 1800V rating (silicon wafer thickness of 470-μm) were
manufactured with shorter and longer phosphorus doping (5-hours, 7-hours)
to demonstrate the impact of anode-side n+ layer upon turn-off time (tq).
The normal brazing temperature of 700 °C was followed.
The measured values of tq are tabulated in Table-3. The data shows that
upper specification limit of 400-μs is exceeded in the case of longer doping
(7-hours), when n+ layer is formed on anode-side, thereby suggesting
incomplete replacement of anode-side n+ with p+. However, the samples
processed with similar conditions but without n+ on anode-side are found to
exhibit values within the limit irrespective of length of doping.
It is therefore evident that n+ layer must be avoided on anode-side for
thyristors with thinner silicon wafers so as to completely get rid of delayed
turn-off irrespective of phosphorus doping time that is chosen to control the
gate turn-on current (IGT)-

14
Example showing impact of brazing temperature on turn-off time for thicker
silicon wafers:
Thyristors of 3200V rating (silicon wafer thickness of 800-μm) were
manufactured with n+ layer on anode-side. Longer phosphorus doping (7-
hours) and two different brazing temperatures (700 °C, 720 °C) were
followed.
The measured values of tq are tabulated in Table-4. The data related to the
normal brazing temperature of 700 °C shows that the upper specification
limit (500-|as) is exceeded, thereby suggesting an incomplete replacement of
anode-side n+ with p+ during brazing. On the contrary, increased
temperature of 720 °C has yielded values within the limit thereby
demonstrating complete replacement of n+ with p+ (without formation of any
buried n+ layer below p+).

15
REFERENCES
[1.1] Thyristor and manufacturing method therefor', Patent No.
JP2002270820, Publication date: Sep 20, 2002, Inventor: Suzuki
Hisashi, Tokyo Shibaura Electric Co.
[1.2] Thyristor manufacturing method and thyristor', Patent number
US6163040, Publication date: December 19, 2000, Inventors:
Akiyama Hajime; Honda Kenichi; Morita Yousuke; Yoshikawa
Mashito; Ohshima Takeshi; Mitsubishi Electric Corporation; Japan
Atomic Research Institute.
[1.3] Thyristor element with short turn-off time and method for
producing such element', US patent number 4,281,336,
Publication date: July 28, 1981, Inventors: Sommer; Karlheinz
(Warstein, DE), Sonntag; Alois (Warstein, DE).
[1.4] Thyristor', Patent number JP54129989, Publication date:
October 8, 1979, Inventor: Yamada Tomisha, Mitsubishi Electric
Corporation (Japan).
[1.5] 'Method of manufacture of a gold diffused thyristor', US patent
number 4,066,484, Publication date: January 3, 1978, inventor:
Moyson; Joseph (Union Springs, NY), General Electric Company
(Auburn, NY).

16
[2] 'High voltage thyristor with optimized doping, thickness and sheet
resistivity for cathode base layer', US patent number 4,682,199,
Publication date: July 21, 1987, Yatsuo; Tsutomu, Momma;
Naohiro, Naito; Masayoshi, Okamura; Masahiro, Hitachi Ltd
(Tokyo, Japan).
[3] Munoz-Yague, A.; Leturcq, P. 'Optimum design of thyristor gate -
Emitter geometry', IEEE Transactions on Electron Devices,
Volume 23, Issue 8, pp. 917-924, Aug 1976.
[4] Paul D. Taylor, Thyristor Design and Realization', John Wiley &
Sons, pp. 151-153, 1987.
[5] Cuevas, A.; Macdonald, D.; Kerr, M.; Samundsett, C; Sloan, A.;
Shea, S.; Leo, A.; Mrcarica, M.; Winderbaum, S.; 'Evidence of
impurity gettering by industrial phosphorus diffusion',
Photovoltaic Specialists Conference, pp: 244-247, Conference
Record of the Twenty-Eighth IEEE Issue, 2000.
[6] Bentzen, A.; Holt, A.; Kopecek, R.; Stokkan, G.; Christensen,
J.S.; Svensson, B.G.; 'Gettering of transition metal impurities
during phosphorus emitter diffusion in multicrystalline silicon
solar cell processing', Journal of Applied Physics. 99, 093509,
May 2006.

17
[7] Crees, D.E.; Humpston, G.; Jacobson, D.M.; Newcombe, D.;
'Silicon / heat-sink assemblies for high power device
applications: present technology and developments', GEC
Journal of Research, Volume 6, 1988.

18
WE CLAIM
1. A method of improving turn-off characteristics of power semiconductor
thyristor formed using silicon wafers of thickness <500>m, comprising
the steps of:
- forming p-n-p structure on the n - type silicon wafers by using
dopants of p-type;
- thermal oxidising the silicon wafers by heating to form a silicon
- di- oxide (Sio2) layer all around;
- etching away the Sio2 oxide layer by using photolithography all
around the silicon wafer except for a central circular region
(gate) on cathode side;
- forming n+ layers by phosphorus doping only on cathode-side
excluding the gate region, and essentially not on anode-side,
and for any unrestricted duration that will provide specified gate
triggered current (IGT);
- gold doping of the silicon thyristor structure for control of carrier
life time which interalia determining the turn - off time (tq) and
on-state conduction drop (UT); and
- brazing anode side of the doped silicon thyristor structure with a
molybdenum plate at a normal brazing temperature using Al-Si
brazing alloy to produce the thyristor structure n+-p-n-p+.

19
2. The method as claimed in claim 1, wherein the duration of phosphorus
doping is not critical for subsequent brazing process due to absence of
n+ on anode side.
3. The method as claimed in claim 1, wherein the normal brazing
temperature is < 700°C.
4. A method of improving turn-off characteristics of power semiconductor
thyristor formed using silicon wafers of thickness > 500μm, comprising
the steps of ;

- forming p-n-p structure on the n - type silicon wafers by using
dopants of p-type;
- thermal oxidising the silicon wafers by heating to form a silicon
- di- oxide (Sio2) layer all around;
- etching away the Sio2 oxide layer by using photolithography all
around the silicon wafer except for a central circular region
(gate) on cathode side;
- phosphorus doping essentially on both cathode and anode sides
with exception to the gate region, and for only a carefully
shortened duration that is just adequate to ensure specified
gate trigger current.
- gold doping of the silicon thyristor structure for control of carrier
life time which interalia determining the turn - off time (tq) and
on-state conduction drop (UT); and

20
- brazing anode side of the fully doped silicon thyristor structure
with a molybdenum plate at a higher brazing temperature using
Al-Si brazing alloy to produce the thyristor structure n+-p-n-p+.
5. The method as claimed in claim 4, wherein the shorter duration of the
phosphorus doping constitutes 4 to 5 hours resulting in complete
replacement of anode side n+ with p+.
6. The method as claimed in claim 4, wherein the higher brazing
temperature constitutes > 720°C which results in complete
replacement of n+ with p+.
7. A method of improving turn-off characteristics of power semiconductor
thyristor formed using silicon wafers of thickness < 500μm as
substantially described and illustrated herein with reference to the
accompanying drawings.
8. A method of improving turn-off characteristics of power semiconductor
thyristor formed using silicon wafers of thickness > 500μm, as
substantially described and illustrated herein with reference to the
accompanying drawings.

The present invention provides appropriate methods for improving the turn-
off characteristics of power semiconductor thyristors, especially where the
observed delayed turn-off is not attributable to the usual causes related to
the recombination rate of electrons and holes. The invention studies the
impacts of anode-side n+ layer formed during the doping processes as well as
silicon wafer thickness on turn-off time of thyristors. The cause of delayed
turn-off is clearly established as incomplete replacement of the anode-side n+
with p+ formed during the brazing of anode-side of silicon wafer with
molybdenum plate.
The invention recommends to avoid n+ layer on anode-side for thyristors with
silicon wafers up to ~500-μm thick. On the contrary, the invention insists on
formation of n+ layer on anode-side for thicker wafers (>~500-μm thick) in
order to achieve the on-state conduction drop within specified limits and
recommends to enhance brazing temperature to ensure complete
replacement of n+ by p+.
The manufacturing yield and the long-term product reliability of thyristors
are improved by the recommended methods that have been successfully
adapted in industrial manufacturing process.