DESC:
TECHNICAL FIELD
[1] The present disclosure relates generally to two-dimensional semiconductor devices and relates, in particular, to atomic orbital overlap engineering for two-dimensional (2D) transition-metal dichalcogenides (TMD) based ultra-low power Field Effect Transistors (FETs) demonstrating high performance.

BACKGROUND
[2] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
[3] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semi-conductive layers of material over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.
[4] Transistors are circuit components or elements that are often formed on semiconductor devices. Many transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Field Effect Transistors (FETs) are commonly known transistors. Generally, a transistor includes a gate stack formed between source and drain regions, wherein source and drain regions may include a doped region of a substrate and may exhibit a doping profile suitable for a particular application. The gate stack is positioned over the channel region and may include a gate dielectric interposed between a gate electrode and the channel region in the substrate.
[5] In recent development of transistors, Transition Metal Dichalcogenide (TMD) or Transition metal dichalcogenides (TMDCs) materials are used for forming transistors. TMDCs are a class of two-dimensional materials that have the chemical formula MX2, where M represents transition metals from group VI, V and VI, and X represents a chalcogen such as sulphur, selenium or tellurium. MoS2, MoSe2, MoTe2, WS2 and WSe2 are TMDCs. Thus, TMDCs are sometime referred to as two-dimensional (2D) transition-metal dichalcogenide (2D-TMD). TMDCs have layered structure with a plane of metal atoms in between two planes of chalcogen atoms. Each layer is bonded strongly in plane but weakly in interlayer’s. Therefore, TMDCs can be easily exfoliated into atomically thin layers through various methods. TMDCs show layer-dependent optical and electrical properties. When exfoliated into monolayer’s, the band gaps of several TMDCs change from indirect to direct, which lead to broad applications in nano-electronics and optoelectronics. The TMD materials form the active regions that include channel regions and source and drain regions.
[6] Two-dimensional FETs often suffer from high contact resistance, low ON state current, depletion mode operation and poor sub threshold slope. Techniques reported earlier to improve device performance were often parameter-specific and while they resulted in improvements in the target parameter, the overall transistor behaviour was often compromised. Alternately, the technique also failed to offer a scalable process.
[7] For example, in earlier works, techniques like molecular doping, ion doping, Nb doping during growth, phase engineering at the contact etc. have been utilised to improve ON state current of the FET. These methods however suffered from one or the other limitations like non-scalability, involvement of wet chemistry or deterioration of other figure of merit parameters.
[8] In another instance, Scandium (Sc) contacts have resulted in record high ON currents in MoS2, however, at the cost of a significant increase in OFF current. Further, Scandium is a highly unstable metal, making it unsuitable for a scalable process.
[9] Hence, the absence of lack of a scalable or CMOS compatible process to boost overall device behaviour is a bottleneck in the development of 2D TMD device technology. In order to extract maximum performance and realize the full potential of the nascent material, it is imperative to do device-material co-design, while keeping in mind the characteristics of atomic orbital’s in 2D TMDs such that the overall device performance is maximized. Exploration for a novel technique that mitigates above-mentioned limitations enhances performance and realizes the full potential of the nascent material is still continued.
[10] There is therefore a need to provide new, improved, efficient, and technically advanced TMD device that can help mitigate the above mentioned limitations along with improving overall transistor behaviour without compromising its complementary performance metrics and still enhancing performance of the overall device. Further, there is also a need to provide a TMD device that demonstrates low contact resistance to source and drain regions and, does not suffer from low ON state current and poor sub-threshold slope.
[11] In some embodiments, numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
[12] As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
[13] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
[14] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.
OBJECTS
[15] A general object of the present disclosure is to provide a transition-metal dichalcogenide (TMD) normally OFF transistor.
[16] Another object of the present disclosure is to provide a transistor with improved ON state performance.
[17] Another object of the present disclosure is to provide a transistor with engineered TMD material – metal contact in order to reduce contact resistance.
[18] Another object of the present disclosure is to provide a transistor with engineered TMD channel layer to provide improved gate control over the channel.

SUMMARY
[19] The present disclosure relates generally to two-dimensional semiconductor devices and relates, in particular, to atomic orbital overlap engineering for two-dimensional (2D) transition-metal dichalcogenides (TMD) based ultra-low power Field Effect Transistors (FETs) demonstrating high performance.
[20] In an aspect, the present disclosure provides a method of engineering a 2-D transition-metal dichalcogenide (TMD) transistor, said method comprising the steps of: exposing a TMD channel layer to a Chalcogen; and doping one or more TMD–metal interfaces.
[21] In another aspect, the TMD channel layer is exposed to a Chalcogen through adsorption, to form a Chalcogen-metal bond and to at least partially satisfy a plurality of Chalcogen vacancies in said TMD channel layer.
[22] In another aspect, the one or more TMD – metal interfaces are doped with the Chalcogen to create chalcogenide interstitials at said one or more TMD–metal interfaces, forming a doped one or more TMD–metal interfaces, to increase bonding between the one or more sets of transition-metal and contact metal and to reduce contact resistance between said one or more sets.
[23] In another aspect, said at least partial satisfaction of a plurality of Chalcogen vacancies in said TMD channel layer increases electron concentration on the surface of TMD to allow improved gate control in channel area of said transistor and to operate said transistor in enhancement mode.
[24] In another aspect, said transistor is a TMD based transistor having transition-metal as Molybdenum (Mo) or as Tungsten (W).
[25] In another aspect, said transistor is a TMD based transistor having Chalcogen as Sulphur (S) or as Selenium (Se).
[26] In another aspect, said contact-metal is selected from any or a combination of Nickel (Ni), Chromium (Cr) and Palladium (Pd).
[27] In another aspect, engineering of TMD channel layer and TMD–metal interface is through Chemical Vapour Deposition (CVD) using a Chalcogen source.
[28] In another aspect, said chalcogen is Sulphur (S) and said chalcogen source is Hydrogen Sulphide (H2S).
[29] In another aspect, said CVD occurs at a temperature range of 300 °C to 400 °C, while varying H2S partial pressure.
[30] In another aspect, the present disclosure provides a 2-D transition-metal dichalcogenide (TMD) based transistor comprising: a TMD channel layer with a plurality of intrinsic Chalcogen vacancies; and one or more contact metals disposed on said TMD channel layer to form one or more corresponding TMD–metal interfaces.
[31] In another aspect, the TMD channel layer with a plurality of intrinsic Chalcogen vacancies is exposed to a Chalcogen such that at least a part of the plurality of Chalcogen vacancies is satisfied.
[32] In another aspect, the one or more contact metals disposed on said TMD channel layer to form one or more corresponding TMD–metal interfaces is exposed to the Chalcogen to increase bonding between the one or more sets of transition-metal and contact metal and to reduce contact resistance between said one or more sets.
[33] In another aspect, said at least partial satisfaction of a plurality of Chalcogen vacancies in said TMD channel layer increases electron concentration on the surface of TMDto allow improved gate control in channel area of said transistor and to operate said transistor in enhancement mode.
[34] In another aspect, said transistor is a TMD based transistor having transition-metal as Molybdenum (Mo) or as Tungsten (W).
[35] In another aspect, said transistor is a TMD based transistor having Chalcogen as Sulphur (S) or as Selenium (Se).
[36] In another aspect, said contact-metal is selected from any or a combination of Nickel (Ni), Chromium (Cr) and Palladium (Pd).
[37] In another aspect, the engineering of TMD channel layer and TMD–metal interface is through Chemical Vapour Deposition (CVD) using a Chalcogen source.
[38] In another aspect, said chalcogen is Sulphur (S) and said chalcogen source is Hydrogen Sulphide (H2S).
[39] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF DRAWINGS
[40] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.
[41] FIG. 1 illustrates effective transmission spectrum, T(E) for various exemplary 2D TMD-metal interfaces with varying contact topologies: MoS2-Ni; MoSe2-Ni; WS2-Cr; and WSe2-Ni, in accordance with embodiments of the present disclosure.
[42] FIG. 2 illustrates partial density of states (PDOS) using different 2D TMD-metal interfaces: MoS2-Ni; MoSe2-Ni; WS2-Cr; and WSe2-Ni, in accordance with embodiments of the present disclosure.
[43] FIG. 3 illustrates current across different TMD-metal contacts with different contact topologies involving Chalcogen atoms, normalized with current across standard contact.
[44] FIG. 4 illustrates Mulliken Charge Population (MCP) extracted for all the contact topologies.
[45] FIGs. 5A – 5D illustrate an exemplary process and flow depicting process sequence involved in processing standard and engineered TMD FETs.
[46] FIG. 5E illustrates an exemplary top view SEM image of a fabricated CVD MoS2 FET, in accordance with embodiments of the present disclosure.
[47] FIG. 6 illustrates an AFM image of a MoS2 flake before (left) and after (right) the H2S based atomic orbital overlap engineering.
[48] FIGs. 7A and 7B illustrate PL spectra of WS2 and MoS2 respectively before and after H2S treatment.
[49] FIGs. 8A – 8D illustrate Raman spectra of as-exfoliated and H2S treated MoSe2, WSe2, MoS2 and WS2 flakes respectively.
[50] FIGs. 9A – 9C illustrate XPS spectra of MoS2, MoSe2 and WS2 samples respectively, before and after H2S exposure.
[51] FIGs. 10A – 10C illustrate plot of drain current vs. gate voltage for contact engineered MoS2, WS2 and MoSe2 FETs respectively.
[52] FIGs. 10D – 10F illustrate plot of drain current vs. gate voltage for channel with contact engineered MoS2, WS2 and MoSe2 FETs respectively.
[53] FIG. 11 summarises improvement in performance figure of merit parameters for various TMD FETs while using proposed contact or / and channel engineering.
[54] FIG. 12 illustrates extracted Schottky barrier heights (SBH) of standard and engineered devices with different contacting metals for WS2 FETs.
[55] FIG. 13A illustrates a plot of drain current vs. gate voltage for standard FETs and contact engineered WSe2/Ni FETs.
[56] FIG. 13B illustrates a plot of drain current vs. gate voltage for standard FETs and contact engineered WSe2/Cr FETs.
[57] FIGs. 14A and 14B illustrate performance of CVD monolayer MoS2 FETs after exposure to H2S engineering for contact and contact with channel respectively.
[58] FIG. 15 illustrates comparison of state-of-the-art 2D TMD FETs on the basis of ON current, and it can be seen that the proposed engineered TMD shows good performance.

DETAILED DESCRIPTION
[59] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.
[60] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.
[61] The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
[62] Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
[63] The present disclosure relates generally to two-dimensional semiconductor and relates, in particular to, atomic orbital overlap engineering for two-dimensional (2D) Transition metal dichalcogenides (TMD) based ultra-low power Field Effect Transistors (FETs) demonstrating record high performance.
[64] It an object of the present disclosure to solve technical problems as recited above in the background section. Accordingly, in an embodiment, in order to overcome limitations in prior art described in the background section above, and to overcome other limitations that will become apparent upon reading and understanding the present disclosure, the present disclosure provides a novel method for atomic orbital overlap engineering in TMDs, while taking advantage of TMD specific process and molecular decomposition to improve the channel and metal-TMD interface of TMD based transistors. It may be appreciated that atomic orbital overlap engineering is earlier found to be advantageous for graphene-metal contacts.
[65] An aspect of the present disclosure relates to atomic orbital overlap engineering for 2D TMD based ultra-low power FETs demonstrating record high performance.
[66] In an aspect, the present disclosure provides a new, technically advanced, technically beneficial and economically significant technique to improve overall transistor behaviour without compromising transistor’s complementary performance metrics. In an aspect, the proposed technique includes/implements a low temperature decomposition of H2S on TMD surface and quantum chemistry between TMD, Chalcogenides and metals, enabling the atomic orbital overlap engineering, both in the channel as well as contact regions and passivation of transition metal’s dangling bonds, which collectively have improved both MoS2/Se2 and WS2/Se2 FETs’ characteristics by significant margins.
[67] In an aspect, the impact of an atom of chalcogen at the interstitial sites in the TMD-metal interface is studied for various material systems using the following topologies: defect-free interface; defected interface (with chalcogen vacancy); and metal-doped interface (with Chalcogen atom at metals site).
[68] FIG. 1 illustrates effective transmission spectrum, T(E) for various exemplary 2D TMD-metal interfaces with varying contact topologies: MoS2-Ni; MoSe2-Ni; WS2-Cr; and WSe2-Ni. In an embodiment, the T(E) is calculated using Extended Huckel Semi empirical method. Higher transmission peak near Fermi-level together with wider spread across energy states can be observed in presence of Chalcogen interstitial/defect, when compared to standard contacts for all the interfaces. In another embodiment, the extent of improvement is found to be independent of TMD-Metal system.
[69] FIG. 2 illustrates partial density of states (PDOS) using the various exemplary 2D TMD-metal interfaces: MoS2-Ni; MoSe2-Ni; WS2-Cr; and WSe2-Ni, calculated for three different topologies using Extended Huckel Semi empirical method. In an embodiment, enhanced PDOS values near the Fermi level can be observed in Chalcogen interstitial contact topology.
[70] In an aspect, from FIGs. 1 and 2, it can be observed that having a Chalcogen atom at an interstitial site on the TMD surface results in significant spread in the Transmission coefficient and Density of States (DOS) across a wider range of energy levels.
[71] FIG. 3 illustrates current across different TMD-metal contacts with different contact topologies involving Chalcogen atoms, normalized with current across standard contact. Current across the contact can be seen to have an inverse relation with contact resistance. Therefore, higher current implies lower contact resistance (RC) in case of Chalcogen interstitial contact topologies when compared to that of standard contact.
[72] FIG. 4 illustrates Mulliken Charge Population (MCP) extracted for all the aforementioned contact topologies. Shift in the electron cloud towards the interface atomic species can be predicted from MCP. In an embodiment, it can be seen that for all TMD-metal interfaces, the amount of average charge shared in the contact region (i.e. at the interface) by all the constituent atoms increases from its reference value in the non-contacted bulk crystals. The increase is found to be highest for the topology with Chalcogen interstitial.
[73] In another embodiment, observation of lower contact resistance with increased charge share across atomic species at the interface can be construed as being due to enhanced orbital interaction between metal and TMD, resulting in improved bonding and contact property.
[74] In an aspect, it can be appreciated that the source of such an increase in charge around all atomic species at the interface is the semiconductor bulk and not the introduced Chalcogen atom. This can be attributed to higher electron density/concentration at the contact region, which can be considered as doping of the semiconductor crystal at the metal-TMD interface.
[75] In another embodiment, the effect of such Chalcogen assisted self-doping of TMD-metal interface on its interface properties is expected to be unique for different contact metals, depending on the available overlapping atomic orbitals for interaction or hybridization.
[76] In another aspect, the present disclosure proposes a transistor with a Chalcogen introduced at the TMD-metal interface. In an exemplary embodiment, the Chalcogen can be Sulphur (S).
[77] In another aspect, Chemical Vapour Deposition (CVD) can be an effective way to grow S based TMD. Hydrogen Sulphide (H2S) is a commonly used source of Sulphur in CVD, which partially decomposes at lower temperatures in presence of TMDs.
[78] In another aspect, beside satisfying S vacancies, H2S also tends to get adsorbed on the TMD surface, thereby forming S-S (or S-Se) bonds between S from H2S and S (or Se) bonded to an adjacent metal atom (Mo or W) in TMD.
[79] FIGs. 5A – 5D illustrate process of doping TMD surface with said Chalcogen. FIG. 5A illustrates a step of substrate cleaning, back gate metal/dielectric stack and 2D TMD transfer/exfoliation. FIG. 5B illustrates a step of S/D Lithography and S/D metal deposition and lift-off, depicting process steps for standard device without H2S assisted engineering. After this step, devices are electrically and optically characterized. In an embodiment, a portion of the same TMD layer can be used to process engineered devices, as shall be depicted.
[80] FIG. 5C illustrates a step of low temperature H2S exposure of TMD for surface engineering to enhance atomic orbital overlap. Partial decomposition of H2S on TMD surface leaves behind S species on the surface. The S atom bonds with S/Se atom of TMDs and H2 is liberated out, as depicted in (i) and (ii). In an exemplary embodiment, to uniformly introduce S doping over TMD top layer, TMD samples can be treated with H2S inside a Quartz tube at a temperature range of 300 °C to 400 °C, while varying H2S partial pressure.
[81] FIG. 5D illustrates a step of S/D metal deposition and lift-off, followed by post metallization anneal.
[82] FIG. 5E illustrates an exemplary top view SEM image of a fabricated CVD MoS2 FET, in accordance with embodiments of the present disclosure.
[83] FIG. 6 illustrates an AFM image of a MoS2 flake before (on the left) and after (on the right) the H2S based atomic orbital overlap engineering. A significant reduction in RMS surface roughness and removal of residues from the top of the MoS2 flake can be observed post the H2S based atomic orbital overlap engineering.
[84] FIGs. 7A and 7B illustrate Photo Luminescence (PL) spectra of WS2 and MoS2 respectively before and after H2S treatment. The peaks correspond to direct band gap (675 nm/1.8 eV for MoS2 and 640 nm/1.94 eV for WS2) and do not show significant shift in frequency, confirming that no change has occurred in the direct band gap of the material. This shows that, after the H2S treatment, the material is conserved without a noticeable change in its semiconducting properties.
[85] FIGs. 8A – 8D illustrate Raman spectra of as-exfoliated and H2S treated MoSe2, WSe2, MoS2 and WS2 flakes respectively. In an embodiment, narrowing of the Raman peaks along with lowering of shoulders close to peaks depict satisfaction of Chalcogen vacancies.
[86] In another embodiment, a red shift can be consistently observed for all TMDs, implying increased electron-phonon coupling. This observation corroborates the shift in electron cloud towards the surface from bulk after H2S exposure, as predicted from the MCP calculations.
[87] FIGs. 9A – 9C illustrate XPS spectra of MoS2, MoSe2 and WS2 samples respectively, before and after H2S exposure. After H2S exposure, the spectra show reduced shoulders near 3d peaks of Mo, which can imply a reduction in S vacancy/defects and presence of Mo dangling bonds in the material. This can be construed as a validation of the theory of defect curing.
[88] In another embodiment, the presence of Sulphur in engineered MoSe2 surface reveals that H2S exposure is a reliable method to introduce S atoms at the surface in order to enable charge distribution mechanism and atomic orbital overlap at the interface.
[89] In another embodiment, data from FIGs. 6 – 9 indicate that H2S assisted engineering results in: increase in the electron concentration at the surface of TMD; passivation of S-vacancies; and presence of S-S (or S-Se) bonds in S (or Se) based TMDs.
[90] FIGs. 10A – 10C illustrate plot of drain current vs. gate voltage for contact engineered MoS2, WS2 and MoSe2 FETs respectively. In an exemplary embodiment, the FETs are constructed as LG = 1 µm, VDS = 4 V, Gate dielectric = 90 nm, SiO2.
[91] In an embodiment, contact engineered MoS2 and WS2 FETs exhibit about 3x and about 5x higher ON current, respectively, without affecting OFF-state current and threshold voltage when compared with standard FETs, as shown in FIGs. 10A and 10B respectively.
[92] In another embodiment, the ON and OFF-state performance of contact engineered MoSe2 FETs show improvements of about 2x and about 5 orders, respectively, as shown in FIG. 10C.
[93] In another embodiment, improved ON-state current can be a result of S assisted charge sharing at the TMD-metal interface. In another embodiment, the OFF-state performance of contact engineered MoS2 and WS2 FETs are unaffected by H2S exposure, as the channel is masked against H2S treatment, thereby retaining its intrinsic channel properties. However, H2S assisted contact engineering on MoSe2 FET can lead to a complete device turn OFF at a VGS of about -25 V, said MoSe2 FET otherwise being ON for the entire range of VGS.
[94] In another embodiment, such a drastic reduction of OFF-state current, and enhancement mode operation can be explained to be an effect of a stronger interaction between S interstitial atom and electrons in its vicinity, due to which the device is at OFF state for a higher VGS.
[95] In another embodiment, this interaction is relatively weak in MoS2 and WS2 FETs compared to that in MoSe2 FETs due to difference in the atomic orbitals involved in Se based TMDs when compared to S based TMDs.
[96] FIGs. 10D – 10F illustrate plots of drain current vs. gate voltage for channel-with-contact engineered MoS2, WS2 and MoSe2 FETs respectively. In an exemplary embodiment, the FETs are constructed as LG = 1 µm, VDS = 4 V, Gate dielectric = 90 nm, SiO2.
[97] In another embodiment, channel-with-contact engineered MoS2 and WS2 FETs exhibit about 20x and about 80x improvement in ON state performance, and about 2 orders and about 1 order reduction in OFF state leakage respectively.
[98] In another embodiment, MoSe2 FETs have large positive VT and therefore exhibit about 5 orders of magnitude lower OFF state current when compared to standard FETs.
[99] In an exemplary embodiment, in a WS2 channel-with-contact engineered device, a drain current (ID) of about 240 µA/µm can be observed.
[100] In an aspect, generally, contacts engineered with H2S can lead to an improved contact performance of the TMDs and the proposed channel engineering can offer improved OFF state behaviour as well as improved gate control.
[101] FIG. 11 summarises improvement in performance figure of merit parameters for various TMD FETs using proposed contact and contact-with-channel engineering. Figure of merit parameters can be any or a combination of ION, gm, µ, IOFF, SS and ION/IOFF.
[102] FIG. 12 illustrates extracted Schottky barrier heights (SBH) of standard and engineered devices with different contacting metals for WS2 FETs. SBH extracted for WS2-Cr/Pd contacts before and after H2S assisted engineering show SBH to shift from positive to negative, indicating a change in nature of said contacts from Schottky to ohmic.
[103] In another embodiment, pinning factor shows stronger pinning of the Fermi-level after H2S assisted engineering of TMDs. Negative SBH is achieved after engineering which can imply presence of ohmic contact.
[104] FIG. 13A illustrates a plot of drain current vs. gate voltage for standard FETs and contact engineered WSe2/Ni FETs. In an embodiment, ON-state performance is improved by about 11x, without any noticeable change in OFF-state behaviour.
[105] FIG. 13B illustrates a plot of drain current vs. gate voltage for standard FETs and contact engineered WSe2/Cr FETs. WSe2/Cr FETs undergo a transition from n-type to p-type behaviour after H2S assisted contact engineering, which is a result of difference in atomic orbitals available for interaction between Ni and Cr, and which results in about 100x improvement in hole current.
[106] FIGs. 14A and 14B illustrate performance of a CVD monolayer MoS2 FETs after exposure to H2S engineering for contact and contact-with-channel respectively. In an embodiment, defect-limited transport can be enhanced by curing the defects present in CVD MoS2 via channel-with-contact engineering, while enhancing current injection through contacts.
[107] In another embodiment, ON state performance of CVD monolayer MoS2 FETs is found to improve by about 4x and about 3x for contact and contact-with-channel engineered FETs, respectively.
[108] In another embodiment, the OFF state leakage was found to reduce by about 1 order of magnitude for both types of engineered devices.
[109] In an aspect, typically, standard CVD monolayer MoS2 FETs are limited in terms of performance due to high defect density and high contact resistance due to large bandgap. However, due to the proposed channel engineering, the plateau in transfer curve is seen to disappear, further confirming reduction of defect states.
[110] In another aspect, a noticeable shift in threshold voltage can also be observed, leading to an enhancement mode CVD MoS2 FETs. This can also be attributed to reduction in S vacancies after channel treatment / curing of intrinsically CVD TMD material.
[111] Thus, the present disclosure provides an approach to engineer TMD/metal interface and TMD channel for different TMD materials (MoS2, WS2, MoSe2 and WSe2). Sulphur assisted enhanced orbital interaction at TMD/metal interface results in transparent contacts, which leads to improved ON-state performance. Further, Sulphur assisted channel engineering, resulting in a reduction of intrinsic defects in TMD channel, improves OFF state behaviour, leading to a controlled transition from depletion mode operation to enhancement mode operation of 2D FETs.
[112] FIG. 15 illustrates comparison of state-of-the-art 2D TMD FETs on the basis of ON current, and it can be seen that the proposed engineered TMD shows good performance.
[113] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES
[114] The present disclosure provides a transition-metal dichalcogenide (TMD) normally OFF transistor.
[115] The present disclosure provides a transistor with improved ON state performance.
[116] The present disclosure provides a transistor with engineered TMD material – metal contact in order to reduce contact resistance.
[117] The present disclosure provides a transistor with engineered TMD channel layer to provide improved gate control over the channel.

,CLAIMS:
1. A method of engineering a 2-D transition-metal dichalcogenide (TMD) transistor, said method comprising the steps of:
exposing a TMD channel layer to a Chalcogen through adsorption, to form a Chalcogen-metal bond and to at least partially satisfy a plurality of Chalcogen vacancies in said TMD channel layer; and
doping one or more TMD–metal interfaces with the Chalcogen to create chalcogenide interstitials at said one or more TMD–metal interfaces, forming a doped one or more TMD–metal interfaces, to increase bonding between the one or more sets of transition-metal and contact metal and to reduce contact resistance between said one or more sets, and
wherein said at least partial satisfaction of a plurality of Chalcogen vacancies in said TMD channel layer increases electron concentration on the surface of TMD to allow improved gate control in channel area of said transistor and to operate said transistor in enhancement mode.
2. The method of claim 1, wherein said transistor is a TMD based transistor having transition-metal as Molybdenum (Mo) or as Tungsten (W).
3. The method of claim 1, wherein said transistor is a TMD based transistor having Chalcogen as Sulphur (S) or as Selenium (Se).
4. The method of claim 1, wherein said contact-metal is selected from any or a combination of Nickel (Ni), Chromium (Cr) and Palladium (Pd).
5. The method of claim 1, wherein engineering of TMD channel layer and TMD–metal interface is through Chemical Vapour Deposition (CVD) using a Chalcogen source.
6. The method of claim 5, wherein said chalcogen is Sulphur (S) and said chalcogen source is Hydrogen Sulphide (H2S).
7. The method of claim 5, wherein said CVD occurs at a temperature range of 300 °C to 400 °C, while varying H2S partial pressure.
8. A 2-D transition-metal dichalcogenide (TMD) based transistor comprising:
a TMD channel layer with a plurality of intrinsic Chalcogen vacancies, exposed to a Chalcogen such that at least a part of the plurality of Chalcogen vacancies is satisfied; and
one or more contact metals disposed on said TMD channel layer to form one or more corresponding TMD–metal interfaces, exposed to the Chalcogen to increase bonding between the one or more sets of transition-metal and contact metal and to reduce contact resistance between said one or more sets, and
wherein said at least partial satisfaction of a plurality of Chalcogen vacancies in said TMD channel layer increases electron concentration on the surface of TMD to allow improved gate control in channel area of said transistor and to operate said transistor in enhancement mode.
9. The transistor of claim 8, wherein said transistor is a TMD based transistor having transition-metal as Molybdenum (Mo) or as Tungsten (W).
10. The transistor of claim 8, wherein said transistor is a TMD based transistor having Chalcogen as Sulphur (S) or as Selenium (Se).
11. The transistor of claim 8, wherein said contact-metal is selected from any or a combination of Nickel (Ni), Chromium (Cr) and Palladium (Pd).
12. The transistor of claim 8, wherein engineering of TMD channel layer and TMD–metal interface is through Chemical Vapour Deposition (CVD) using a Chalcogen source.
13. The transistor of claim 12, wherein said chalcogen is Sulphur (S) and said chalcogen source is Hydrogen Sulphide (H2S).