Description:[0001] The present application claims priority to U.S. Non-Provisional Patent Application No. 17/483,431 filed on 23 September 2021 and titled “METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO DETECT CODE DEFECTS” the entire disclosure of which is hereby incorporated by reference.

FIELD OF THE DISCLOSURE

[0002] This disclosure relates generally to code development improvements and, more particularly, to methods, systems, articles of manufacture and apparatus to detect code defects prior to hardware design.

BACKGROUND
[0003] In recent years, code development efforts have focused on reducing code errors in an effort to avoid and/or otherwise reduce corresponding hardware faults that are derived from faulty code. Typically, modern compilers have some degree of code error checking, such as debuggers that identify syntax errors in code.

BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 is a schematic illustration of an example environment to detect code defects.
[0005] FIG. 2 is a schematic illustration of example anomaly analyzer of FIG. 1 to detect code defects.
[0006] FIGS. 3A and 3B illustrate example DAG generation based on candidate code blocks.
[0007] FIG. 4 illustrates example DAG unification to identify invariants that are common among different code blocks.
[0008] FIGS. 5-10 are flowcharts representative of example machine readable instructions that may be executed by example processor circuitry to implement the example anomaly analyzer circuitry of FIGS. 1 and/or 2 to detect code defects.
[0009] FIG. 11 is a block diagram of an example processing platform including , C , C , Claims:1. An apparatus comprising:
processor circuitry including one or more of:
at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry to control data movement within the processor circuitry, arithmetic and logic circuitry to perform one or more first operations corresponding to instructions, and one or more registers to store a result of the one or more first operations, the instructions in the apparatus;
a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations, the storage circuitry to store a result of the one or more second operations; or
Application Specific Integrated Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;
the processor circuitry to perform at least one of the one or more first operations, the one or more second operations or the one or more third operations to instantiate:
repository interface circuitry to retrieve code repositories corresponding to a programming language of interest;
tree generating circuitry to generate parse trees corresponding to code blocks contained in the code repositories;
directed acyclic graph (DAG) circuitry to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information;
abstraction generating circuitry to abstract the DAGs;
invariant identification circuitry to extract invariants from the abstracted DAGs; and
DAG comparison circuitry to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

2. The apparatus as defined in claim 1, wherein the repository interface circuitry is to retrieve code repositories devoid of label information, the label information corresponding to code validity.

3. The apparatus as defined in claim 1, wherein the abstraction generating circuitry is to convert programming language specific code elements to normalized code elements.

4. The apparatus as defined in claim 1, wherein the abstraction generating circuitry is to identify at least one of source nodes or sink nodes in the abstracted DAGs.

5. The apparatus as defined in claim 4, wherein the abstraction generating circuitry is to replace the at least one of source nodes or sink nodes with normalized variables.

6. The apparatus as defined in claim 1, wherein the invariant identification circuitry is to identify a relationship between a sensitivity list and source nodes of the abstracted DAGs.

7. The apparatus as defined in claim 6, wherein the invariant identification circuitry is to determine a size of the sensitivity list, the size of the sensitivity list equal to a number of the source nodes of the abstracted DAGs.

8. A method comprising:
retrieving, by executing an instruction with at least one processor, code repositories corresponding to a programming language of interest;
generating, by executing an instruction with the at least one processor, parse trees corresponding to code blocks contained in the code repositories;
generating, by executing an instruction with the at least one processor, directed acyclic graphs (DAGs) corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information;
abstracting, by executing an instruction with the at least one processor, the DAGs and extract invariants from the abstracted DAGs; and
clustering, by executing an instruction with the at least one processor, respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

9. The method as defined in claim 8, further including retrieving code repositories devoid of label information, the label information corresponding to code validity.

10. The method as defined in claim 8, further including converting programming language specific code elements to normalized code elements.

11. The method as defined in claim 8, further including identifying at least one of source nodes or sink nodes in the abstracted DAGs.

12. The method as defined in claim 11, further including replacing the at least one of source nodes or sink nodes with normalized variables.

13. The method as defined in claim 8, further including identifying a relationship between a sensitivity list and source nodes of the abstracted DAGs.

14. The method as defined in claim 13, further including determining a size of the sensitivity list, the size of the sensitivity list equal to a number of the source nodes of the abstracted DAGs.

15. A system comprising:
means for interfacing to retrieve code repositories corresponding to a programming language of interest;
means for generating trees to generate parse trees corresponding to code blocks contained in the code repositories;
means for generating a directed acyclic graph (DAG) to generate DAGs corresponding to respective ones of the parse trees, the DAGs including control flow information and data flow information;
means for generating abstracted DAGs to abstract the DAGs;
means for identifying invariants to extract invariants from the abstracted DAGs; and
means for comparing DAGs to cluster respective ones of the extracted invariants to identify respective ones of the abstracted DAGs with common invariants.

16. The system as defined in claim 15, wherein the means for interfacing is to retrieve code repositories devoid of label information, the label information corresponding to code validity.

17. The system as defined in claim 15, wherein the means for generating abstracted DAGs is to convert programming language specific code elements to normalized code elements.

18. The system as defined in claim 15, wherein the means for generating abstracted DAGs is to identify at least one of source nodes or sink nodes in the abstracted DAGs.

19. The system as defined in claim 18, wherein the means for generating abstracted DAGs is to replace the at least one of source nodes or sink nodes with normalized variables.

20. The system as defined in claim 15, wherein the means for identifying invariants is to identify a relationship between a sensitivity list and source nodes of the abstracted DAGs.

21. The system as defined in claim 20, wherein the means for identifying invariants is to determine a size of the sensitivity list, the sensitivity list equal to a number of the source nodes of the abstracted DAGs.